Warping Of Semiconductor Substrate Patents (Class 438/457)
  • Patent number: 10109487
    Abstract: A method for bonding a first substrate with a second substrate at respective contact faces of the substrates with the following steps: holding the first substrate to a first sample holder surface of a first sample holder with a holding force FH1 and holding the second substrate to a second sample holder surface of a second sample holder with a holding force FH2; contacting the contact faces at a bond initiation point and heating at least the second sample holder surface to a heating temperature TH; bonding of the first substrate with the second substrate along a bonding wave running from the bond initiation point to the side edges of the substrates, wherein the heating temperature TH is reduced at the second sample holder surface during the bonding.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: October 23, 2018
    Assignee: EV Group E. Thallner GmbH
    Inventors: Florian Kurz, Thomas Wagenleitner, Thomas Plach, Jurgen Markus Suss
  • Patent number: 9827753
    Abstract: Provided are laminating apparatus and method. A laminating apparatus includes a jig assembly, which includes the first jig and an elastic member, and a second jig. A laminating method includes placing a first plate on a jig assembly, placing a second plate on a second jig which is placed to face the first jig, bringing the second plate into contact with the adhesive layer by making the jig assembly and the second jig approach each other, and, attaching the first plate and the second plate to each other by making the jig assembly and the second jig approach closer to each other. The jig assembly includes a first jig and an elastic member which comprises a top portion and sloping portions sloping downward from the top portion. An adhesive layer is disposed between the first plate and the second plate.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: November 28, 2017
    Assignees: Samsung Display Co., Ltd., Yodogawa Medec Co., Ltd.
    Inventors: Yang Han Son, Jong Hwan Kim, Young Sik Kim, Kyung Su Lee
  • Patent number: 9324612
    Abstract: In one embodiment there is disclosed a method for manufacturing an integrated circuit in a semiconductor substrate including through vias and a coplanar line, including the steps of: forming active components and a set of front metallization levels; simultaneously etching from the rear surface of the substrate a through via hole and a trench crossing the substrate through at least 50% of its height; coating with a conductive material the walls and the bottom of the hole and of the trench; and filling the hole and the trench with an insulating filling material; and forming a coplanar line extending on the rear surface of the substrate, in front of the trench and parallel thereto, so that the lateral conductors of the coplanar line are electrically connected to the conductive material coating the walls of the trench.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: April 26, 2016
    Assignee: STMicroelectronics SA
    Inventors: Sylvain Joblot, Pierre Bar
  • Patent number: 9111753
    Abstract: A method includes forming a stress compensation layer over a first side of a semiconductor substrate and forming a Group III-nitride layer over a second side of the substrate. Stress created on the substrate by the Group III-nitride layer is at least partially reduced by stress created on the substrate by the stress compensation layer. Forming the stress compensation layer could include forming a stress compensation layer from amorphous or microcrystalline material. Also, the method could include crystallizing the amorphous or microcrystalline material during subsequent formation of one or more layers over the second side of the substrate. Crystallizing the amorphous or microcrystalline material could occur during subsequent formation of the Group III-nitride layer and/or during an annealing process. The amorphous or microcrystalline material could create no or a smaller amount of stress on the substrate, and the crystallized material could create a larger amount of stress on the substrate.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: August 18, 2015
    Assignee: NATIONAL SEMICONDUCTOR CORPORATION
    Inventor: Jamal Ramdani
  • Patent number: 9029184
    Abstract: To provide a resource-saving photoelectric conversion device with excellent photoelectric conversion characteristics. Thin part of a single crystal semiconductor substrate, typically a single crystal silicon substrate, is detached to structure a photoelectric conversion device using a thin single crystal semiconductor layer, which is the detached thin part of the single crystal semiconductor substrate. The thin part of the single crystal semiconductor substrate is detached by a method in which a substrate is irradiated with ions accelerated by voltage, or a method in which a substrate is irradiated with a laser beam which makes multiphoton absorption occur. A so-called tandem-type photoelectric conversion device is obtained by stacking a unit cell including a non-single-crystal semiconductor layer over the detached thin part of the single crystal semiconductor substrate.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: May 12, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akihisa Shimomura
  • Patent number: 9006083
    Abstract: Methods and structures for GaN on silicon-containing substrates are disclosed, comprising a texturing process to generate a rough surface containing (111) surface, which then can act as an underlayer for epitaxial GaN. LED devices are then fabricated on the GaN layer. Variations of the present invention include different orientations of silicon layer instead of (100), such as (110) or others; and other semiconductor materials instead of GaN, such as other semiconductor materials suitable for LED devices.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: April 14, 2015
    Inventor: Ananda H. Kumar
  • Publication number: 20150076662
    Abstract: Provided is a composite substrate manufacturing method, including at least: a first raw board deforming step of preparing a first substrate by deforming a first raw board having at least one surface as a minor surface into a state in which the minor surface warps outward; and a joining step of joining, after the first raw board deforming step, a protruding surface of the first substrate and one surface of a second substrate to each other, thereby manufacturing a composite substrate including the first substrate and the second substrate, in which the second substrate is any one substrate selected from a substrate having both surfaces as substantially flat surfaces and a substrate that warps so that a surface thereof to be joined to the first substrate warps outward. Also provided are a semiconductor element manufacturing method, a composite substrate and a semiconductor element manufactured.
    Type: Application
    Filed: April 24, 2013
    Publication date: March 19, 2015
    Applicants: NAMIKI SEIMITSU HOUSEKI KABUSHIKIKAISHA, DISCO CORPORATION
    Inventors: Hideo Aida, Natsuko Aota, Hidetoshi Takeda, Keiji Honjo, Hitoshi Hoshino, Mai Ogasawara
  • Patent number: 8982270
    Abstract: A deformable focal plane array (DFPA) for imaging systems is disclosed. In one embodiment, the DFPA includes a detection circuitry on one side. For example, the thickness of the DFPA is in a range of about 5 to 40 microns. In one exemplary embodiment, the DFPA when warped to a desired shape provides a substantially wider field of view (FOV) than a flat focal plane array (FPA).
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: March 17, 2015
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Dennis P. Bowler, Raymond J. Silva, Gerard A. Esposito
  • Patent number: 8969931
    Abstract: A semiconductor device and a method for fabricating the semiconductor device. The device includes: a doped semiconductor having a source region, a drain region, a channel between the source and drain regions, and an extension region between the channel and each of the source and drain regions; a gate formed on the channel; and a screening coating on each of the extension regions. The screening coating includes: (i) an insulating layer that has a dielectric constant that is no greater than about half that of the extension regions and is formed directly on the extension regions, and (ii) a screening layer on the insulating layer, where the screening layer screens the dopant ionization potential in the extension regions to inhibit dopant deactivation.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mikael T. Bjoerk, Joachim Knoch, Heike E. Riel, Walter Heinrich Riess, Heinz Schmid
  • Publication number: 20150056783
    Abstract: A method for bonding a first substrate having a first surface to a second substrate having a second surface. This method includes the steps of holding the first substrate by at least two support points, positioning the first substrate and the second substrate so that the first surface and the second surface face each other, deforming the first substrate by applying between at least one pressure point and the two support points a strain toward the second substrate, bringing the deformed first surface and the second surface into contact, and progressively releasing the strain to facilitate bonding of the substrates while minimizing or avoiding the trapping of air bubbles between the substrates.
    Type: Application
    Filed: October 3, 2014
    Publication date: February 26, 2015
    Inventors: Sebastien Kerdiles, Daniel Delprat
  • Patent number: 8956952
    Abstract: A multilayer substrate structure comprises a substrate, a thermal matching layer formed on the substrate and a lattice matching layer above the thermal matching layer. The thermal matching layer includes at least one of molybdenum, molybdenum-copper, mullite, sapphire, graphite, aluminum-oxynitrides, silicon, silicon carbide, zinc oxides, and rare earth oxides. The lattice matching layer includes a first chemical element and a second chemical element to form an alloy. The first and second chemical element has similar crystal structures and chemical properties. The coefficient of thermal expansion of the thermal matching layer and the lattice parameter of the lattice matching layer are both approximately equal to that of a member of group III-V compound semiconductors. The lattice constant of the lattice matching layer is approximately equal to that of a member of group III-V compound semiconductor.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: February 17, 2015
    Assignee: Tivra Corporation
    Inventors: Francisco Machuca, Indranil De
  • Patent number: 8946678
    Abstract: Room temperature IR and UV photodetectors are provided by electrochemical self-assembly of nanowires. The detectivity of such IR detectors is up to ten times better than the state of the art. Broad peaks are observed in the room temperature absorption spectra of 10-nm diameter nanowires of CdSe and ZnS at photon energies close to the bandgap energy, indicating that the detectors are frequency selective and preferably detect light of specific frequencies. Provided is a photodetector comprising: an aluminum substrate; a layer of insulator disposed on the aluminum substrate and comprising an array of columnar pores; a plurality of semiconductor nanowires disposed within the pores and standing vertically relative to the aluminum substrate; a layer of nickel disposed in operable communication with one or more of the semiconductor nanowires; and wire leads in operable communication with the aluminum substrate and the layer of nickel for connection with an electrical circuit.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: February 3, 2015
    Assignee: Virginia Commonwealth University
    Inventors: Supriyo Bandyopadhyay, Saumil Bandyopadhyay, Pratik Agnihotri
  • Patent number: 8927319
    Abstract: There is disclosed methods of making photosensitive devices, such as flexible photovoltaic (PV) devices, through the use of epitaxial liftoff. Also described herein are methods of preparing flexible PV devices comprising a structure having a growth substrate, wherein the selective etching of protective layers yields a smooth growth substrate that us suitable for reuse.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: January 6, 2015
    Assignee: The Regents of the University of Michigan
    Inventors: Stephen R. Forrest, Jeramy Zimmerman, Kyusang Lee, Kuen-Ting Shiu
  • Patent number: 8906776
    Abstract: A method for forming an electronic circuit on a strained semiconductor substrate, including the steps of: forming, on a first surface of a semiconductor substrate, electronic components defining electronic chips to be sawn; and forming at least portions of a layer of a porous semiconductor material on the side of a second surface of the semiconductor substrate, opposite to the first surface, to bend the semiconductor substrate.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: December 9, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Daniel Bensahel, Aomar Halimaoui
  • Patent number: 8900969
    Abstract: Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. To avoid warpage, the tensile stress of a conductive layer deposited onto a GaAs substrate can be offset by depositing a compensating layer having negative stress over the GaAs substrate. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: December 2, 2014
    Assignee: Skyworks Solutions, Inc.
    Inventor: Hong Shen
  • Patent number: 8889531
    Abstract: A semiconductor body comprised of a semiconductor material includes a first monocrystalline region of the semiconductor material having a first lattice constant along a reference direction, a second monocrystalline region of the semiconductor material having a second lattice constant, which is different than the first, along the reference direction, and a third, strained monocrystalline region between the first region and the second region.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: November 18, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans-Joachim Schulze, Franz-Josef Niedernostheide, Reinhart Job
  • Patent number: 8871588
    Abstract: A method of fabricating a memory cell comprises forming a plurality of doped semiconductor layers on a carrier substrate. The method further comprises forming a plurality of digit lines separated by an insulating material. The digit lines are arrayed over the doped semiconductor layers. The method further comprises etching a plurality of trenches into the doped semiconductor layers. The method further comprises depositing an insulating material into the plurality of trenches to form a plurality of electrically isolated transistor pillars. The method further comprises bonding at least a portion of the structure formed on the carrier substrate to a host substrate. The method further comprises separating the carrier substrate from the host substrate.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: October 28, 2014
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, H. Montgomery Manning
  • Patent number: 8859334
    Abstract: An electronic device manufacturing method includes a cutting step at which a wafer is cut to obtain chips before pattern formation and a polishing step at which cut surfaces of the obtained chips are subjected in one batch to barrel polishing. The method further includes an aligning step at which the polished chips are aligned so that front surfaces thereof face in an upward direction. The method further includes a bonding step at which the cut surfaces of the aligned chips are bonded together with an adhesive to thereby form a chip assembly. The method further includes a pattern forming step at which a circuit pattern is formed on each of the chips of the chip assembly and a melting step at which the adhesive on the chip assembly is melted to thereby separate the chip assembly into chips after pattern formation.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: October 14, 2014
    Assignee: Fujitsu Limited
    Inventors: Hajime Kubota, Masayuki Itoh, Masakazu Kishi
  • Patent number: 8859335
    Abstract: A method for alignment of a first substrate coupled to a second substrate includes determining an inclination angle for the first substrate or the second substrate due to warpage. The method includes determining a joint height difference based on the inclination angle and configuring a size for one or more bond pads based on the joint height difference.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: October 14, 2014
    Assignee: Fujitsu Limited
    Inventors: Michael G. Lee, Chihiro Uchibori
  • Patent number: 8853054
    Abstract: A method is provided for preparing multilayer semiconductor structures, such as silicon-on-insulator wafers, having reduced warp and bow. Reduced warp multilayer semiconductor structures are prepared by forming a dielectric structure on the exterior surfaces of a bonded pair of a semiconductor device substrate and a semiconductor handle substrate having an intervening dielectric layer therein. Forming a dielectric layer on the exterior surfaces of the bonded pair offsets stresses that may occur within the bulk of the semiconductor handle substrate due to thermal mismatch between the semiconductor material and the intervening dielectric layer as the structure cools from process temperatures to room temperatures.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: October 7, 2014
    Assignee: SunEdison Semiconductor Limited
    Inventors: Guoqiang Zhang, Jeffrey L. Libbert
  • Patent number: 8846500
    Abstract: At least one exemplary embodiment is directed to a method of forming a multilayered gettering structure that can be used to control wafer warpage.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: September 30, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: David Lysacek, Jana Vojtechovska, Lubomir Dornak, Petr Kostelnik, Lukas Valek, Petr Panek
  • Patent number: 8835281
    Abstract: An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: September 16, 2014
    Assignee: Silanna Semiconductor U.S.A., Inc.
    Inventors: Chris Brindle, Michael A. Stuber, Stuart B. Molin
  • Patent number: 8822308
    Abstract: A method is disclosed which includes: forming at least one layer of material on at least part of a surface of a first substrate, wherein a first surface of the at least one layer of material is in contact with the first substrate thereby defining an interface; attaching a second substrate to a second surface of the at least one layer of material; forming bubbles at the interface; and applying mechanical force; whereby the second substrate and the at least one layer of material are jointly separated from the first substrate. Related arrangements are also described.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: September 2, 2014
    Assignee: Graphene Frontiers
    Inventor: Bruce Ira Willner
  • Patent number: 8822310
    Abstract: Some embodiments discussed relates to an apparatus for holding a substrate, comprising a body with a surface for a semiconductor wafer to rest on, with the surface having a first surface area on which a first area of the semiconductor wafer can rest, and a second surface area on which a second area of the semiconductor wafer can rest, wherein the second surface area protrudes with respect to the first surface area.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: September 2, 2014
    Assignee: Infineon Technologies AG
    Inventors: Gerald Lackner, Christian Maier, Francisco Javier Santos Rodriguez
  • Patent number: 8802542
    Abstract: The invention pertains to a combination of a substrate and a wafer, wherein the substrate and the wafer are arranged parallel to one another and bonded together with the aid of an adhesive layer situated between the substrate and the wafer, and wherein the adhesive is chosen such that its adhesive properties are neutralized or at least diminished when a predetermined temperature is exceeded. According to the invention, the adhesive layer is only applied annularly between the substrate and the wafer in the edge region of the wafer.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: August 12, 2014
    Inventor: Erich Thallner
  • Patent number: 8785249
    Abstract: Aspects and examples include electrical components and methods of forming electrical components. In one example, a method includes selecting a substrate, forming a pattern of a first conductive material on a top surface of the substrate, forming a pattern of a second conductive material on a bottom surface of the substrate, dicing the substrate into one or more die having a first diced surface and a second diced surface, securing the first diced surface of each of the one or more die to a retaining material, encapsulating the one or more die in an encapsulent to form a reconstituted wafer, and forming a pattern of a third conductive material on the second diced surface by metalizing a surface of the reconstituted wafer.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: July 22, 2014
    Assignee: The Charles Stark Draper Laboratory, Inc.
    Inventor: Maurice Karpman
  • Patent number: 8785292
    Abstract: An anodic bonding apparatus includes a first electrode and a second electrode. The first electrode has a first surface, and the second electrode has a second surface facing the first surface. The first surface includes a first central area; a first substrate placing area for placing a laminated substrate; and a first peripheral area surrounding the first substrate placing area. The second surface includes a second central area corresponding to the first central area; a second substrate placing area surrounding the second central area; and a second peripheral area corresponding to the first peripheral area and surrounding the second substrate placing area. Further, the second electrode includes a curved portion curved toward the first electrode, so that a distance between the first central area and the second central area becomes smaller than a distance between the first peripheral area and the second peripheral area.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: July 22, 2014
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventor: Shinichi Sueyoshi
  • Patent number: 8778774
    Abstract: Methods are provided for enhancing properties, including polarization, of thin-film ferroelectric materials in electronic devices. According to one embodiment, a process for enhancing properties of ferroelectric material in a device having completed wafer processing includes applying mechanical stress to the device, independently controlling the temperature of the device to cycle the temperature from room temperature to at or near the Curie temperature of the ferroelectric material and back to room temperature while the device is applied with the mechanical stress, and then removing the mechanical stress. Certain of the subject methods can be performed as part of a back end of line (BEOL) process, and may be performed during the testing phase at wafer or die level.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: July 15, 2014
    Assignees: University of Florida Research Foundation, Inc., Texas Instruments Incorporated
    Inventors: Toshikazu Nishida, Antonio Guillermo Acosta, John Anthony Rodriguez, Theodore Sidney Moise
  • Patent number: 8698131
    Abstract: Provided is an organic EL apparatus including: an organic EL panel including organic EL devices; a heat releasing member; and a pair of film sheets of which at least one is transparent, wherein the organic EL panel and the heat releasing member overlap and are interposed and encapsulated by the pair of film sheets in a state where a portion of the heat releasing member is exposed outside the pair of film sheets.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: April 15, 2014
    Assignee: Seiko Epson Corporation
    Inventor: Kozo Gyoda
  • Patent number: 8697543
    Abstract: A chip-to-wafer bonding method and a three-dimensional integrated semiconductor device are provided. The method comprises providing a chip and a wafer having a bonding region of the same size and shape as the chip; preparing hydrophilic areas and hydrophobic areas on the chip; preparing in the bonding region hydrophilic areas and hydrophobic areas respectively corresponding to the hydrophilic and hydrophobic areas on the chip; adding a liquid drop onto the hydrophilic areas in the bonding region; and pre-aligning and placing the chip on the bonding region of the wafer, such that the hydrophilic areas on the chip each contacts the corresponding hydrophilic area in the bonding region via the liquid. The sum of perimeters of the hydrophilic areas on the chip is larger than a perimeter of the chip. The sum of perimeters of the hydrophilic areas in the bonding region is larger than a perimeter of the bonding region.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: April 15, 2014
    Assignee: Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Yunqi Sui, Chang Liu
  • Patent number: 8691663
    Abstract: A method of processing an epistructure or processing a semiconductor device including associating a conformal and flexible handle with the epistructure and removing the epistructure and handle as a unit from the parent substrate. The method further includes causing the epistructure and handle unit to conform to a shape that differs from the shape the epistructure otherwise inherently assumes upon removal from the parent substrate. A device prepared according to the disclosed methods.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: April 8, 2014
    Assignee: Alliance for Sustainable Energy, LLC
    Inventor: Mark W. Wanlass
  • Patent number: 8685833
    Abstract: A method is provided for bonding a semiconductor chip to a packaging substrate while minimizing the variation in the solder ball heights and controlling the stress in the solder balls and the stress in the packaging substrate. During the solder reflow, the warp of the packaging substrate, including the absolute warp, thermal warp, and substrate to substrate variations of the warp, is constrained at a minimal level by providing a clamping constraint to the packaging substrate. During cool down of the solder balls, the stresses and strains of the solder joints are maintained at levels that do not cause tear of the solder joints or breakage of the packaging substrate by removing the clamping constraint. Thus, the bonding process provides both uniform solder height with minimized solder non-wets and stress minimization of the solder balls and the packaging substrate.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: April 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Vijayeshwar D. Khanna, Sri M. Sri-Jayantha
  • Patent number: 8664085
    Abstract: A composite-substrate manufacturing method is provided with: a step of carrying out implantation of ions through a surface of a bulk substrate composed of the nitride compound semiconductor; a step of setting said surface of the bulk substrate against the second substrate, and bonding the bulk substrate and the second substrate together to obtain a bonded substrate; a step of elevating the temperature of the bonded substrate to a first temperature; a step of sustaining the first temperature for a fixed time; and a step of producing a composite substrate by severing the remaining portion of the bulk substrate from the bonded substrate; characterized in that a predetermined formula as for the first temperature, the thermal expansion coefficient of the first substrate, and the thermal expansion coefficient of the second substrate is satisfied.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: March 4, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yoko Maeda, Fumitaka Sato, Akihiro Hachigo, Seiji Nakahata
  • Patent number: 8586450
    Abstract: A semiconductor device includes a first wafer having at least one first integrated-circuit chip and a first support layer surrounding the first integrated circuit chip. A first electrical-connection layer is placed on a frontside of the first wafer and includes a first electrical-connection network. A second wafer is placed on a frontside of the first electrical-connection layer. The second wafer includes at least one second integrated-circuit chip and a second support layer surrounding the second integrate circuit chip. The second integrated circuit chip has an active side facing the first electrical-connection layer, and one or more through-holes filled with a conductor forming electrical-connection vias. A second electrical-connection layer is placed on the backside of the second wafer and includes a second electrical-connection network.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: November 19, 2013
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventor: Eric Saugier
  • Patent number: 8575002
    Abstract: A method for the direct bonding of a first wafer having an intrinsic curvature before bonding to a second wafer having an intrinsic curvature before bonding, at least one of the two wafers including at least one series of microcomponents. The method includes bringing the two wafers into contact with each other so as to initiate the propagation of a bonding wave therebetween while imposing a predefined bonding curvature in the form of a paraboloid of revolution on one of the two wafers depending at least upon the intrinsic curvature before bonding of the wafer that includes the microcomponents, with the other wafer being free to conform to the predefined bonding curvature.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: November 5, 2013
    Assignee: Soitec
    Inventors: Marcel Broekaart, Gweltaz Gaudin, Arnaud Castex
  • Publication number: 20130260534
    Abstract: A method is provided for bonding a semiconductor chip to a packaging substrate while minimizing the variation in the solder ball heights and controlling the stress in the solder balls and the stress in the packaging substrate. During the solder reflow, the warp of the packaging substrate, including the absolute warp, thermal warp, and substrate to substrate variations of the warp, is constrained at a minimal level by providing a clamping constraint to the packaging substrate. During cool down of the solder balls, the stresses and strains of the solder joints are maintained at levels that do not cause tear of the solder joints or breakage of the packaging substrate by removing the clamping constraint. Thus, the bonding process provides both uniform solder height with minimized solder non-wets and stress minimization of the solder balls and the packaging substrate.
    Type: Application
    Filed: April 2, 2012
    Publication date: October 3, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Vijayeshwar D. Khanna, Sri M. Sri-Jayantha
  • Publication number: 20130256824
    Abstract: There is provided a solid-state imaging device including a sensor substrate having a sensor-side semiconductor layer including a pixel region in which a photoelectric conversion section is provided and a sensor-side wiring layer provided on an opposite surface side from a light receiving surface of the sensor-side semiconductor layer, a circuit substrate having a circuit-side semiconductor layer and a circuit-side wiring layer and provided on a side of the sensor-side wiring layer of the sensor substrate, a connection unit region in which a connection section is provided, the connection section having a first through electrode, a second through electrode, and a connection electrode connecting the first through electrode and the second through electrode, and an insulating layer having a step portion which has the connection electrode embedded therein and has a film thickness that gradually decreases from the connection unit region to the pixel region.
    Type: Application
    Filed: April 1, 2013
    Publication date: October 3, 2013
    Applicant: Sony Corporation
    Inventors: KYOHEI MIZUTA, OSAMU OKA, KAORU KOIKE, NOBUTOSHI FUJII, HIDEKI KOBAYASHI, HIROTAKA YOSHIOKA
  • Patent number: 8546238
    Abstract: A method for transferring a micro-technological layer includes preparing a substrate having a porous layer buried beneath a useful surface, forming an embrittled zone between it and the surface, bonding the substrate to a supporting substrate, causing detachment at the porous layer by mechanical stress to obtain a first substrate remnant, and a bare surfaced detached layer joined to the supporting substrate, performing technological steps on the bared surface of the detached layer, bonding the detached layer, by the surface to which the technological steps had been applied, to a second supporting substrate, causing detachment, at the embrittled zone, by heat treatment to obtain a detached layer remnant joined to the second supporting substrate, and the detached layer remnant joined to the first supporting substrate.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: October 1, 2013
    Assignee: Commissariat a l'Energie Atomique et aux Energies
    Inventors: Aurelie Tauzin, Anne-Sophie Stragier
  • Patent number: 8536022
    Abstract: A method according to embodiments of the invention includes providing an epitaxial structure comprising a donor layer and a strained layer. The epitaxial structure is treated to cause the strained layer to relax. Relaxation of the strained layer causes an in-plane lattice constant of the donor layer to change.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: September 17, 2013
    Assignee: Koninklijke Philips N.V.
    Inventor: Andrew Y. Kim
  • Patent number: 8536021
    Abstract: A trap rich layer for an integrated circuit chip is formed by chemical etching and/or laser texturing of a surface of a semiconductor layer. In some embodiments, a trap rich layer is formed by a technique selected from the group of techniques consisting of laser texturing, chemical etch, irradiation, nanocavity formation, porous Si-etch, semi-insulating polysilicon, thermal stress relief and mechanical texturing. Additionally, combinations of two or more of these techniques may be used to form a trap rich layer.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: September 17, 2013
    Assignee: IO Semiconductor, Inc.
    Inventors: Anton Arriagada, Michael A. Stuber, Stuart B. Molin
  • Patent number: 8530253
    Abstract: A method of fabricating a flexible display device includes: forming a plastic substrate on a carrier substrate, the plastic substrate including an active area and a non-active area surrounding the active area; forming an array element on the carrier substrate, the array element including a plurality of layers and having an average adhesion force among the plurality of layers; forming a first film on the array element, the first film having a first adhesion force; attaching a flexible printed circuit board to the plastic substrate; forming a second film on the first film, the second film having a second adhesion force greater than the first adhesion force; and detaching the plastic substrate from the carrier substrate.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: September 10, 2013
    Assignee: LG Display Co., Ltd.
    Inventors: Aram Shin, Tae-Joon Ahn
  • Patent number: 8524572
    Abstract: Some embodiments include methods of processing a unit containing crystalline material. A damage region may be formed within the crystalline material, and a portion of the unit may be above the damage region. A chuck may be used to bend the unit and thereby induce cleavage along the damage region to form a structure from the portion of the unit above the damage region. Some embodiments include methods of forming semiconductor-on-insulator constructions. A unit may be formed to have dielectric material over monocrystalline semiconductor material. A damage region may be formed within the monocrystalline semiconductor material, and a portion of the monocrystalline semiconductor material may be between the damage region and the dielectric material. The unit may be incorporated into an assembly with a handle component, and a chuck may be used to contort the assembly and thereby induce cleavage along the damage region.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: September 3, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Shu Qin, Ming Zhang
  • Patent number: 8518804
    Abstract: A semiconductor device manufacturing method and manufacturing apparatus with which it is possible, when a wafer has a warp, to effectively peel off an ultraviolet peelable tape with ultraviolet irradiation of a short duration. Even when a wafer has a warp, by correcting the warp of the wafer with an ultraviolet transmitting plate, and uniformly irradiating an ultraviolet peelable tape attached to the wafer with ultraviolet light, it is possible to reduce a distance between an ultraviolet light source and the ultraviolet peelable tape. Also, by blocking heat from the ultraviolet light source with the ultraviolet transmitting plate, it is possible to suppress a rise in temperature of the wafer. As a result of this, it is possible to effectively peel the ultraviolet peelable tape from the wafer with ultraviolet irradiation of a short duration without any adhesive residue remaining.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: August 27, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Yuichi Urano
  • Publication number: 20130183810
    Abstract: According to one embodiment, a system for manufacturing a semiconductor device includes a spontaneous joining unit and a deformative joining unit. The spontaneous joining unit overlaps a first substrate and a second substrate and spontaneously joins mutual center portions of respective joint faces of the first substrate and the second substrate. The deformative joining unit deforms at least one peripheral portion of the respective joint faces of the first substrate and second substrate joined by the spontaneous joining unit toward the other peripheral portion and joins the mutual peripheral portions of the respective joint faces.
    Type: Application
    Filed: May 24, 2012
    Publication date: July 18, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Satoshi HONGO, Kenji Takahashi, Kazumasa Tanida
  • Patent number: 8484846
    Abstract: A showerhead electrode for a plasma processing apparatus includes an interface gel between facing surfaces of an electrode plate and a backing plate. The interface gel maintains thermal conductivity during lateral displacements generated during temperature cycling due to mismatch in coefficients of thermal expansion. The interface gel comprises, for example, a silicone based composite filled with aluminum oxide microspheres. The interface gel can conform to irregularly shaped features and maximize surface contact area between mating surfaces. The interface gel can be pre-applied to a consumable upper electrode.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: July 16, 2013
    Assignee: Lam Research Corporation
    Inventor: Rajinder Dhindsa
  • Patent number: 8481405
    Abstract: An integrated circuit chip is formed with a circuit layer, a trap rich layer and through-semiconductor-vias. The trap rich layer is formed above the circuit layer. The through-semiconductor-vias are also formed above the circuit layer. In some embodiments, the circuit layer is included in a wafer, and the trap rich layer and through-semiconductor-vias are included in another wafer. The two wafers are bonded together after formation of the trap rich layer and through-semiconductor-vias. Additionally, in some embodiments, yet another wafer may also be bonded to the wafer that includes the trap rich layer and through-semiconductor-vias. Furthermore, in some embodiments, another circuit layer may be formed in the wafer that includes the trap rich layer and through-semiconductor-vias.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: July 9, 2013
    Assignee: IO Semiconductor, Inc.
    Inventors: Anton Arriagada, Chris Brindle, Michael A. Stuber
  • Patent number: 8481408
    Abstract: A method for relaxing a layer of a strained material. The method includes depositing a first low-viscosity layer on a first face of a strained material layer; bonding a first substrate to the first low-viscosity layer to form a first composite structure; subjecting the composite structure to heat treatment sufficient to cause reflow of the first low-viscosity layer so as to at least partly relax the strained material layer; and applying a mechanical pressure to a second face of the strained material layer wherein the second face is opposite to the first face and with the mechanical pressure applied perpendicularly to the strained material layer during at least part of the heat treatment to relax the strained material.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: July 9, 2013
    Assignee: Soitec
    Inventors: Fabrice Letertre, Carlos Mazure, Michael R. Krames, Melvin B. McLaurin, Nathan F. Gardner
  • Patent number: 8475612
    Abstract: A method for bonding a first wafer on a second wafer by molecular adhesion, where the wafers have an initial radial misalignment between them. The method includes bringing the two wafers into contact so as to initiate the propagation of a bonding wave between the two wafers while a predefined bonding curvature is imposed on at least one of the two wafers during the contacting step as a function of the initial radial misalignment.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: July 2, 2013
    Assignee: Soitec
    Inventor: Gweltaz Gaudin
  • Patent number: 8461614
    Abstract: A packaging substrate device includes: a first laminate including a first ceramic substrate and a first copper pattern disposed on an upper surface of the first ceramic substrate; and a second laminate disposed over the first copper pattern and including a second ceramic substrate, a second copper pattern that is disposed on an upper surface of the second ceramic substrate, and a through hole extending through the second ceramic substrate and the second copper pattern to expose a copper portion of the first copper pattern. A light emitting semiconductor die can be mounted on the copper portion within the through hole. Efficient heat dissipation can be achieved through the first laminate.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: June 11, 2013
    Assignee: Tong Hsing Electronic Industries, Ltd.
    Inventors: Wen-Chung Chiang, Keng-Chung Wu, Ying-Chi Hsieh, Cheng-Kang Lu, Ming-Huang Fu
  • Patent number: 8431467
    Abstract: An object to be processed is restrained from warping at the time of laser processing. A modified region M2 is formed within a wafer 11, and fractures a2, b2 extending in directions parallel to the thickness direction of the wafer 11 and tilted with respect to a plane including lines 5 are generated from the modified region M2. A modified region M3 is formed within the wafer 11, and a fracture a3 extending in a direction parallel to the thickness direction of the wafer 11 and tilted with respect to the plane including the lines 5 is generated from the modified region M3 so as to connect with the fracture b2. That is, the fractures a2, a3, b2 are generated so as to be connected together.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: April 30, 2013
    Assignee: Hamamatsu Photonics K.K.
    Inventor: Takeshi Sakamoto