Abstract: A semiconductor device and a method for manufacturing such semiconductor device are provided. Specifically, in the semiconductor manufacture, a recessed alignment mark is formed on a front plane of a high distortion point glass substrate as a target for alignment for bonding, and the recessed alignment mark is permitted to have a shape which extends to an external side of the semiconductor device. Thus, excellent bonding between the high distortion point glass substrate and the semiconductor device can be provided, and at the same time, since the recessed alignment mark is not sealed, the bonding state can be maintained even when the high distortion point glass substrate is exposed under the high temperature condition after bonding the semiconductor device.

Abstract: To provide a manufacturing method of a semiconductor device using an SOI substrate, by which mobility can be improved. A plurality of semiconductor films formed using a plurality of bond substrates (semiconductor substrates) are bonded to one base substrate (support substrate). At least one of the plurality of bond substrates has a crystal plane orientation different from that of the other bond substrates. Accordingly, at least one of the plurality of semiconductor films formed over one base substrate has a crystal plane orientation different from that of the other semiconductor films. The crystal plane orientation of the semiconductor film is determined in accordance with the polarity of a semiconductor element formed using the semiconductor film. For example, an n-channel element in which electrons are majority carriers is formed using a semiconductor film having a face {100}, and a p-channel element in which holes are majority carriers is formed using a semiconductor film having a face {110}.

Abstract: A heat treatment apparatus is disclosed, which enables suppression of a warp of a base substrate to which a plurality of single crystal semiconductor substrates are bonded. An example of the apparatus comprises a treatment chamber, a supporting base provided in the treatment chamber, a plurality of supports which are provided over the supporting base and are arranged to support the base substrate, and a heating unit for heating the base substrate, where each position of the plurality of supports can be changed over the supporting base. The use of this apparatus contributes to the reduction in the region where the base substrate and the supports are in contact with each other, which allows uniform heating of the base substrate, leading to the formation of an SOI substrate with high quality.

Abstract: Methods of producing CdZnTe (CZT) layers for the epitaxial growth of HgCdTe thereon include implanting ions into a CZT substrate at a low temperature to form a damaged layer underneath a CZT surface layer, bonding a wafer to the CZT substrate about the CZT surface layer using a bonding material, and, annealing the CZT substrate for a time sufficient to facilitate the splitting of the CZT substrate at the damaged layer from the CZT surface layer.

Abstract: In a method for manufacturing a micromechanical structure, first a two-dimensional structure is formed in a substrate. The two-dimensional structure is deflected from the substrate plane by action of force and fixed in the deflected state.

Abstract: A single crystal semiconductor substrate including an embrittlement layer is attached to a base substrate with an insulating layer interposed therebetween, and the single crystal semiconductor layer is separated at the embrittlement layer by heat treatment; accordingly, a single crystal semiconductor layer is fixed over the base substrate. The single crystal semiconductor layer is irradiated with a laser beam so that the single crystal semiconductor layer is partially melted and then is re-single crystallized, whereby crystal defects are removed. In addition, an island-shaped single crystal semiconductor layer for forming an n-channel transistor is channel-doped using a photomask and then is etched back using the photomask so that the island-shaped single crystal semiconductor layer for forming an n-channel transistor is thinner than the island-shaped single crystal semiconductor layer for forming a p-channel transistor.

Abstract: A broad crystal display panel having a color filter substrate is supported by supporting nails and the middle portion of a supporting span is pressed by a loading bar. From this state, the supporting nails are removed to release the supporting, and subsequently the supporting nails are also removed to release the supporting the color filter substrate. While preventing the displacement between the color filter substrate and a TFT array substrate, the color filter substrate and the TFT array substrate can be stacked with a specified distance.

Abstract: A silicon layer having a conductivity type opposite to that of a bulk is provided on the surface of a silicon substrate and hydrogen ions are implanted to a predetermined depth into the surface region of the silicon substrate through the silicon layer to form a hydrogen ion-implanted layer. Then, an n-type germanium-based crystal layer whose conductivity type is opposite to that of the silicon layer and a p-type germanium-based crystal layer whose conductivity type is opposite to that of the germanium-based crystal layer are successively vapor-phase grown to provide a germanium-based crystal. The surface of the germanium-based crystal layer and the surface of the supporting substrate are bonded together. In this state, impact is applied externally to separate a silicon crystal from the silicon substrate along the hydrogen ion-implanted layer, thereby transferring a laminated structure composed of the germanium-based crystal and the silicon crystal onto the supporting substrate.

Abstract: Techniques for integrated circuit device fabrication are provided. In one aspect, an integrated circuit device comprises a base, at least one die attached to the base, and a counterbalancing layer on at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die. In another aspect, warping of an integrated circuit device comprising at least one die attached to a base is controlled by applying a counterbalancing layer to at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die.

Abstract: A method of processing a wafer including a plurality of integrated circuit devices on a front side of the wafer, may include thinning the wafer from a back side opposite the front side. After thinning the wafer, a back side layer may be provided on the back side of the thinned wafer opposite the front side, and the back side layer may be configured to counter stress on the front side of the wafer including the plurality of integrated circuit devices thereon. After providing the back side layer, the plurality of integrated circuit devices may be separated. Related structures are also discussed.

Abstract: A method of producing a strained layer on a substrate includes assembling a layer with a first structure or first means of straining including at least one substrate or one layer capable of being deformed within a plane thereof under the influence of an electric or magnetic field or a photon flux. The layer is strained by modifying the electric or magnetic field or the photon flux. The strained layer is assembled with a transfer substrate and all or part of the first straining structure is removed.

Abstract: In a stacking semiconductor device in which a first-layer and a second-layer semiconductor devices are stacked and bonded with a solder, warpage occurs due to a difference in thermal expansion coefficient of constituent members or a difference in elastic modulus of individual members. Therefore, between the first-layer and the second-layer semiconductor devices are provided an external connection terminal of solder and a thermosetting resin, and the stacking semiconductor device is heated at 150 to 180° C., which are the temperatures of preheating for reflow of the solder, for 30 to 90 seconds. Thereby the warpage of the first-layer semiconductor device is reduced and the thermosetting resin is cured completely in this state. Then, the temperature is raised to a reflow temperature of the solder and solder bonding using the external connection terminal is performed. Thereby, the bonding reliability of a solder-bonded portion of the stacking semiconductor device is considerably improved.

Abstract: In one example embodiment, a process for cleaving a wafer cell includes several acts. First a wafer cell is affixed to an adhesive film. Next, the adhesive film is stretched substantially uniformly. Then, the adhesive film is further stretched in a direction that is substantially orthogonal to a predetermined reference direction. Next, the wafer cell is scribed to form a notch that is oriented substantially parallel to the predetermined reference direction. Finally, the wafer cell is cleaved at a location substantially along the notch.

Abstract: A method for forming bonded substrates includes providing a plurality of substrates, each of which having a top surface. A characteristic length for each of the plurality of substrates is determined by: determining a topographical profile of the top surface of the substrate from an interior portion to an edge portion along a radial direction, determining a highest point of the profile, and defining the characteristic length as a distance from the highest point to the edge portion. A first substrate and a second substrate are selected where at least one of the first or the second substrates has a characteristic length shorter than a predetermined length. The first substrate and the second substrate are brought into contact and form bonded substrates, with the top surface of the first substrate facing the top surface of the second substrate.

Abstract: A thin-film circuit device includes a substrate and a thin-film circuit layer, disposed on the substrate, having an element region and a low-strength region. The element region includes thin-film elements. The low-strength region extends between an end portion of the thin-film circuit layer and the element region and has a mechanical strength less than that of the surroundings of the low-strength region.

Abstract: To improve bonding strength and improve reliability of an SOI substrate in bonding a semiconductor substrate and a base substrate to each other even when an insulating film containing nitrogen is used as a bonding layer, an oxide film is provided on the semiconductor substrate side, a nitrogen-containing layer is provided on the base substrate side, and the oxide film formed on the semiconductor substrate and the nitrogen-containing layer formed over the base substrate are bonded to each other. Further, plasma treatment is performed on at least one of the oxide film and the nitrogen-containing layer before bonding the oxide film formed on the semiconductor substrate and the nitrogen-containing layer formed over the base substrate to each other. Plasma treatment can be performed in a state in which a bias voltage is applied.

Abstract: A processing time required for regeneration of a layer transferred wafer is reduced and the regeneration cost is lowered, while a removal amount at the regeneration is decreased the number of regeneration times is increased. A main surface of a semiconductor wafer (13) has a main flat portion (13d) and a chamfered portion (13c) formed in the periphery of the main flat portion (13d), an ion implanted area (13b) is formed by implanting ions only into the main flat portion (13d), a laminated body (16) is formed by laminating the main flat portion (13d) on a main surface of a support wafer (14), and moreover, the semiconductor wafer (13) is separated from a thin layer (17) in the ion implanted area (13b) by heat treatment at a predetermined temperature so as to obtain a thick layer transferred wafer (12), which is to be regenerated.

Abstract: After the plurality of single-crystal semiconductor layers are provided adjacent to each other with a certain distance over a glass substrate which is a support substrate, heat treatment is performed on the glass substrate. The support substrate shrinks by this heat treatment, and the adjacent single-crystal semiconductor layers are in contact with each other due to the shrink. Energy beam irradiation is performed with the plurality of single-crystal semiconductor layers being in contact with each other, the plurality of single-crystal semiconductor layers are integrated, and thus a continuous single-crystal semiconductor layer is formed.

Abstract: On a surface of a resin base material (11), a first resin coating film (19) having a larger thickness and a larger area than a second resin coating film (20) formed on the other surface of the resin base material (11) is continuously formed. The second resin coating film (20) is formed so as to be separated into a plurality of portions.

Abstract: A planarizing method performed on a non-planar wafer involves forming electrically conductive posts extending through a removable material, each of the posts having a length such that a top of each post is located above a plane defining a point of maximum deviation for the wafer, concurrently smoothing the material and posts so as to form a substantially planar surface, and removing the material. An apparatus includes a non planar wafer having contacts thereon, the wafer having a deviation from planar by an amount that is greater than a height of at least one contact on the wafer, and a set of electrically conductive posts extending away from a surface of the wafer, the posts each having a distal end, the distal ends of the posts collectively defining a substantially flat plane.

Abstract: A bonded wafer formed by directly bonding a wafer for active layer and a wafer for support substrate without an insulating film and thinning the wafer for active layer is evaluated by a method comprising steps of removing native oxide from a surface of an active layer in the bonded wafer, subjecting the bonded wafer to an etching with an etching liquid having an etching rate to a material constituting the wafer faster than that to an oxide of the material to remove at least a whole of the active layer, and detecting island-shaped oxides exposed by the etching, in which the etching is carried out so as to satisfy a relation of T?X?T+500 nm wherein T is a thickness of the active layer (nm) and X is an etching depth (nm) to detect the number and size of the island-shaped oxides.

Abstract: The main objective of present invention is to provide a manufacturing method of light emitting diode that utilizes metal diffusion bonding technology. AlInGaP light emitting diode epitaxial structure on a temporary substrate is bonded to a permanent substrate having a thermal expansion coefficient similar to that of the epitaxial structure, and then the temporary substrate is removed to produce an LED having a vertical structure and better performance. The other objective of the present invention is to provide a high performance LED that uses metal diffusion technology and wet chemical etching technology to roughen the LED surface in order to improve light extraction efficiency.

Abstract: A method of fabricating a memory cell comprises forming a plurality of doped semiconductor layers on a carrier substrate. The method further comprises forming a plurality of digit lines separated by an insulating material. The digit lines are arrayed over the doped semiconductor layers. The method further comprises etching a plurality of trenches into the doped semiconductor layers. The method further comprises depositing an insulating material into the plurality of trenches to form a plurality of electrically isolated transistor pillars. The method further comprises bonding at least a portion of the structure formed on the carrier substrate to a host substrate. The method further comprises separating the carrier substrate from the host substrate.

Abstract: For providing a flexible printed circuit board in which the distance between each of plural wiring patterns is a desired distance by cutting the flexible printed circuit board having plural wiring patterns, plural wiring patterns are formed so as to extend on the surface of an electrically insulative base film, and each of the plural wiring patterns is formed so as to include a portion where the distance between each of them is narrowed along the extending direction of the base film.

Abstract: The main objective of present invention is to provide a manufacturing method of light emitting diode that utilizes metal diffusion bonding technology. AlInGaP light emitting diode epitaxial structure on a temporary substrate is bonded to a permanent substrate having a thermal expansion coefficient similar to that of the epitaxial structure, and then the temporary substrate is removed to produce an LED having a vertical structure and better performance. The other objective of the present invention is to provide a high performance LED that uses metal diffusion technology and wet chemical etching technology to roughen the LED surface in order to improve light extraction efficiency.

Abstract: Exemplary embodiments provide a semiconductor fabrication method including a combination of monolithic integration techniques with wafer bonding techniques. The resulting semiconductor devices can be used in a wide variety of opto-electronic and/or electronic applications such as lasers, light emitting diodes (LEDs), phototvoltaics, photodetectors and transistors. In an exemplary embodiment, the semiconductor device can be formed by first forming an active-device structure including an active-device section disposed on a thinned III-V substrate. The active-device section can include OP and/or EP VCSEL devices. A high-quality monolithic integration structure can then be formed with low defect density through an interfacial misfit dislocation. In the high-quality monolithic integration structure, a thinned III-V mating layer can be formed over a silicon substrate.

Abstract: Methods for forming copper interconnects for semiconductor devices are provided. In an exemplary embodiment, a method for forming a copper interconnect comprises depositing copper into a trench formed in a dielectric material overlying a semiconductor material. A force is applied to the semiconductor material and stress is induced within the copper deposited in the trench. Recrystallization and grain growth are effected within the copper and the stress is removed.

Abstract: An approach where items of different temperatures are bonded to each other such that upon cooling down they contract in size resulting in zero residual stress between the bonded items at an ambient temperature. If materials of the bonded items have different thermal expansion coefficients and the items are put together at different bonding temperatures, then they may have insignificant residual stress upon cooling down to the ambient temperature (e.g., room temperature) because the different ranges of the temperature drops compensate for the different contractions.

Abstract: Provided is a method and apparatus for close alignment of two or more electrically conductive wafers which are positioned face-to-face in closely spaced opposition, the wafers having position marks on corresponding portions thereof, the wafers being aligned as to their mating components, as guided by optically comparing the alignment of the respective position marks; deflecting an interior portion of one of the wafers into contact with the other wafer, to partially bond the wafers to each other, then fully contacting and bonding the rest of the wafer pair and then optically checking the resulting wafer alignment to see if same is acceptable.

Abstract: A classification apparatus for the semiconductor substrate is provided with a bow measuring section which accepts silicon substrates and measures respective bows thereof. The classification apparatus is also provided with a bow judging section which, based on one or more standard value(s) set in advance, checks a measurement result by the bow measuring section against the standard value(s). The bow judging section judges to which of ranges defined based on the standard value(s) of the bow the measurement result by the bow measuring section belongs. Further, the classification apparatus is provided with a sorting section which accepts the silicon substrate having been measured by the bow measuring section and sorts the accepted silicon substrates based on the judgment results by the bow judging section. In other words, silicon substrates are grouped according to the bows by the sorting section. Then, respective silicon substrates are discharged in a grouped state.

Abstract: The transfer of strained semiconductor layers from one substrate to another substrate involves depositing a multilayer structure on a substrate having surface contaminants. An interface that includes the contaminants is formed in between the deposited layer and the substrate. Hydrogen atoms are introduced into the structure and allowed to diffuse to the interface. Afterward, the deposited multilayer structure is bonded to a second substrate and is separated away at the interface, which results in transferring a multilayer structure from one substrate to the other substrate. The multilayer structure includes at least one strained semiconductor layer and at least one strain-induced seed layer. The strain-induced seed layer can be optionally etched away after the layer transfer.

Abstract: The present invention relates to a method for laminating substrates, including locating positioning a surface of a first substrate and a surface of a second substrate at positions close to each other, or partially bringing them in partial contact with each other; supplying a volatile liquid between the surface of the first substrate and the surface of the second substrate; and evaporating the volatile liquid so as to laminate the substrates with each other.

Abstract: A strip level substrate is manufactured by: applying solder resist on a substrate including a plurality of unit substrate divided by a scribe line; and patterning the applied solder resist to expose an electrode terminal and a ball land in each unit substrate, wherein the patterning of the solder resist is performed to be removed together with a solder resist part applied on the scribe line in order to reduce an early warpage of the strip level substrate.

Abstract: A spatial light modulator is fabricated by bonding a capping layer over a wafer bearing active reflecting surfaces utilizing a low temperature bonding agent capable of providing a hermetic seal, such as a glass frit. The low temperature bonding agent may be B-stage cured after application to the capping layer, prior to any exposure to the substrate bearing the reflecting surfaces. In accordance with one embodiment of the present invention, the capping layer may comprise a glass wafer pre-bonded with an interposer spacer layer to provide sufficient stand-off between the capping layer and the underlying reflecting structures. In accordance with an alternative embodiment of the present invention, the capping layer may comprise a glass wafer alone, and the bonding agent may include additional materials such as beads or balls to provide the necessary stand-off between the capping layer and the underlying reflective structures.

Abstract: An adhesive bonding sheet having an optically transmitting supporting substrate and an adhesive bonding layer, and being used in both a dicing step and a semiconductor element adhesion step, wherein the adhesive bonding layer comprises: a polymer component (A) having a weight average molecular weight of 100,000 or more including functional groups; an epoxy resin (B); a phenolic epoxy resin curing agent (C); a photoreactive monomer (D), wherein the Tg of the cured material obtained by ultraviolet light irradiation is 250° C. or more; and a photoinitiator (E) which generates a base and a radical by irradiation with ultraviolet light of wavelength 200-450 nm.

Abstract: Methods are provided of fabricating compound nitride semiconductor structures. A group-III precursor and a nitrogen precursor are flowed into a processing chamber to deposit a first layer over a surface of a first substrate with a thermal chemical-vapor-deposition process. A second layer is deposited over a surface of a second substrate with the thermal chemical-vapor-deposition process using the first group-III precursor and the first nitrogen precursor. The first and second substrates are different outer substrates of a plurality of stacked substrates disposed within the processing chamber as a stack so that the first and second layers are deposited on opposite sides of the stack. Deposition of the first layer and deposition of the second layer are performed simultaneously.

Abstract: A substrate gap adjusting device adjusts a gap between first and second substrates in a composite substrate. In the substrate gap adjusting device, the composite substrate includes the first substrate; the second substrate that is oppositely bonded to the first substrate through a sealant, the second substrate having a smaller area than the first substrate; and liquid crystal that is injected into a space surrounded by the first substrate, the second substrate, and the sealant.

Abstract: A method and apparatus for underfilling a gap between a semiconductor die or device and a substrate, where the semiconductor die or device is electrically connected to the substrate so that an active surface of the semiconductor die is facing a top surface of the substrate with the gap therebetween. A silane layer is applied to the active surface of the semiconductor die, the upper surface of the substrate, and/or both to increase the surface tension thereon. The increased surface tension thereby allows the underfill material to fill the gap via capillary action in a lesser flow time more effectively, and therefore, is more efficient than conventional underfilling methods.

Abstract: A flip chip assembly having reduced stress and warpage comprises a flip chip package including an organic substrate and an integrated circuit chip, a temporary structure having a coefficient of thermal expansion that is substantially similar to a coefficient of thermal expansion of the integrated circuit chip, and a cap member coupled to a top side of the organic substrate. A bottom side of the integrated circuit chip is bonded to the top side of the organic substrate with controlled chip collapse columns. Additionally, a bottom side of the organic substrate is soldered to a top side of the temporary structure with solder interconnections that are applied to a plurality of solder pads on the top side of the temporary structure, the position of the solder pads on the temporary structure mirroring the position of a plurality of solder pads on the bottom side of the organic substrate.

Abstract: The object of the invention is to provide a method for fabricating a semiconductor device having a peeled layer bonded to a base material with curvature. Particularly, the object is to provide a method for fabricating a display with curvature, more specifically, a light emitting device having an OLED bonded to a base material with curvature. An external force is applied to a support originally having curvature and elasticity, and the support is bonded to a peeled layer formed over a substrate. Then, when the substrate is peeled, the support returns into the original shape by the restoring force, and the peeled layer as well is curved along the shape of the support. Finally, a transfer object originally having curvature is bonded to the peeled layer, and then a device with a desired curvature is completed.

Abstract: A method for producing a direct bonded wafer comprising: forming a thermal oxide film or a CVD oxide film on a surface of at least one of a bond wafer and a base wafer, and bonding the wafer to the other wafer via the oxide film; subsequently thinning the bond wafer to prepare a bonded wafer; and thereafter conducting a process of annealing the bonded wafer under an atmosphere including any one of an inert gas, hydrogen and a mixed gas of an inert gas and hydrogen so that the oxide film between the bond wafer and the base wafer is removed to bond the bond wafer directly to the base wafer. Thereby, there is provided a method for producing a direct bonded wafer in which generation of voids is reduced, and a direct bonded wafer with a low void count.

Abstract: The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Stretchable semiconductors and electronic circuits of the present invention preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention may be adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

Abstract: The invention relates to a process for fabricating a semiconductor structure, which comprises: a step a) of providing an Si substrate having a front face and a rear face; and a step b) that includes the epitaxial deposition, on the front face of the Si substrate, of a thick Ge layer, of an SiGe virtual substrate or of a multilayer comprising at least one thick Ge layer or at least one SiGe virtual substrate, and which is characterized in that it further includes the deposition, on the rear face of the Si substrate, of a layer or a plurality of layers generating, on this rear face, flexural stresses that compensate for the flexural stresses that are exerted on the front face of said substrate after step b). The invention also relates to a process for fabricating semiconductor-on-insulator substrates implementing the above process. Applications in microelectronics and optoelectronics.

Abstract: A principal surface at one side of a support substrate has thereon an adjustment layer made of material having a higher thermal expansion coefficient than that of the support substrate. Then, a nitride-base semiconductor element layer and the support substrate on a growth substrate are joined via an adhesion layer. Next, the support substrate is joined to the nitride-base semiconductor element layer via the adhesion layer. Next, the growth substrate is separated from the joined nitride-base semiconductor element layer and the support substrate.

Abstract: Embodiments in accordance with the present invention relate to methods and apparatuses for bonding together substrates in a manner that suppresses the formation of voids between them. In a specific embodiment, a backside of each substrate is adhered to a front area of flexible, porous chuck having a rear area in pneumatic communication with a vacuum. Application of the vacuum causes the chuck and the associated substrate to slightly bend. Owing to this bending, physical contact between local portions on the front side of the flexed substrates may be initiated, while maintaining other portions on front side of the substrates substantially free from contact with each other. A bond wave is formed and maintained at a determined velocity to form a continuous interface joining the front sides of the substrates, without formation of voids therebetween.

Abstract: A method for reducing stress and warpage in flip chip packages comprising providing a flip chip package including an organic substrate, an integrated circuit chip, and a cap member, providing a temporary structure having a coefficient of thermal expansion that is substantially similar to a coefficient of thermal expansion of the integrated circuit chip, soldering a bottom side of the organic substrate to a top side of the temporary structure, bonding a bottom side of the integrated circuit chip to a top side of the organic substrate with controlled chip collapse columns, coupling the cap member to the top side of the organic substrate, applying force to the flip chip package in a first direction, and applying force to the temporary structure in a second direction opposite the first direction in order to shear the top side of the temporary structure from the bottom side of the organic substrate to remove the temporary structure from the flip chip package.

Abstract: Methods are provided of fabricating a nitride semiconductor structure. A group-III precursor and a nitrogen precursor are flowed into a processing chamber to deposit a first layer over one side of the substrate with a thermal chemical-vapor-deposition process. A second layer is similarly deposited over an opposite side of the substrate using the group-III precursor and the nitrogen precursor. The substrate is cooled after depositing the first and second layers without substantially deforming a shape of the substrate.

Abstract: A semiconductor device with a chip (505), its position defining a plane, and an insulating substrate (503) with first and second surfaces; the substrate is substantially coplanar with the chip, without warpage. One of the chip sides is attached to the first substrate surface using adhesive material (504), which has a thickness. The thickness of the adhesive material is distributed so that the thickness (504b) under the central chip area is equal to or smaller than the material thickness (504a) under the peripheral chip areas. Encapsulation compound (701) is embedding all remaining chip sides and the portions of the first substrate surface, which are not involved in the chip attachment. When reflow elements (720) are attached to the substrate contact pads, they are substantially coplanar with the chip.

Abstract: A method of dividing a wafer whose strength is reduced along a plurality of dividing lines formed in a lattice pattern on the front surface, along the dividing lines, comprising the steps of: a tape affixing step for affixing a protective tape to one side of the wafer; a wafer holding step for holding the wafer affixed to the protective tape on both sides of each dividing line through the protective tape; and a breaking step for dividing the wafer along each dividing line by sucking, along each dividing line, the wafer held through the protective tape.

Abstract: A method for making a silicon substrate having a buried thin silicon oxide film is described. The method consists of: a) producing a first element having a first silicon body whereof the main surface is coated, in succession, with a buffer layer of germanium, or of an alloy of germanium and silicon, and with a thin silicon film; b) producing a second element, having a silicon body whereof a main surface is coated with a thin silicon oxide film; c) linking the first element with the second element such that the thin silicon film of the first element is in contact with the thin silicon oxide film of the second element; and d) eliminating the buffer layer to recuperate the silicon substrate having a buried thin silicon oxide film and a reusable silicon substrate. The method may be useful in making microelectronic devices such as CMOS and MOSFET devices.