Abstract: One aspect disclosed herein relates to a method for forming a strained semiconductor structure. In various embodiments of the method, a number of recesses are formed in a surface of a first semiconductor wafer such that the surface of the first semiconductor wafer has a number of raised areas and a number of recessed areas. A surface of a second semiconductor wafer is bonded to the raised areas of the first semiconductor wafer in an environment having a first pressure. The surface of the second semiconductor wafer is bonded to the recessed areas of the first semiconductor wafer in an environment having a second pressure. The second pressure is greater than the first pressure to influence the second semiconductor wafer into contact with the first semiconductor wafer in the recesses in the surface of the first semiconductor wafer. Other aspects are provided herein.

Abstract: The invention provides integrated semiconductor devices that are formed upon an SOI substrate having different crystal orientations that provide optimal performance for a specific device. Specifically, an integrated semiconductor structure including at least an SOI substrate having a top semiconductor layer of a first crystallographic orientation and a semiconductor material of a second crystallographic orientation, wherein the semiconductor material is substantially coplanar and of substantially the same thickness as that of the top semiconductor layer and the first crystallographic orientation is different from the second crystallographic orientation is provided. The SOI substrate is formed by forming an opening into a structure that includes at least a first semiconductor layer and a second semiconductor layer that have different crystal orientations. The opening extends to the first semiconductor layer.

Abstract: Processes that may be used in producing electronic, opotoelectronic, or optical components may be provided. The processes may involve preparing a reusable donor wafer for donating a thin layer of semiconductor material by assembling a donor layer of a semiconductor material having a thickness of plural thin layers onto a support layer of. The semiconductor material for the support layer may be selected to be less precious or to have a lower quality than the donor layer. The support layer may have sufficient mechanical characteristics for supporting the donor layer during desired semiconductor processing treatments.

Abstract: A wafer structure is deposited on a composite substrate structure having at least two substrate layers bonded together. A first substrate layer is made of a first substrate material having a first-substrate-layer material transverse coefficient of thermal expansion, greater than the wafer transverse coefficient of thermal expansion, and a second substrate layer is made of a second substrate material having a second-substrate-layer material transverse coefficient of thermal expansion, measured parallel to the transverse direction, less than the wafer transverse coefficient of thermal expansion. The substrate layers are present in relative proportions such that the substrate transverse coefficient of thermal expansion differs from the wafer transverse coefficient of thermal expansion by not more than about 2×10−6/° F.

Abstract: A method for forming a multi-layer semiconductor device (1) having a lower silicon layer (4), an intermediate silicon layer (5) within which micro-mirrors (10) are formed and an upper spacer layer (6) of silicon for spacing another component from the micro-mirrors (10). First and second etch stop layers (8,9) of oxide act as insulation between the respective layers (4,5,6). In order to minimize damage to the micro-mirrors (10), the formation of the micro-mirrors (10) is left to the end of the forming process. An assembly of the lower layer (4) and the intermediate layer (5) with the first etch stop layer (8) is formed, and the second etch stop layer (9) is then grown and patterned on the intermediate layer (5) for subsequent formation of the micro-mirrors (10). The upper layer (5) is then bonded by an annealing process to the patterned second etch stop layer (9).

Abstract: Methods are provided for adjusting and controlling the stress between layers of material in a multilayer structure. A first stress is configured in a region of stress on the substrate material. A second material is then deposited over the substrate. A second stress results between the substrate and the second material such that a net stress results where the net stress is a function of said first and second stresses. As such, the first stress can be configured to achieve a predetermined, desired net stress. For example, the first stress can be configured to cancel out the second stress such that the net stress is substantially zero.

Abstract: An array of crystalline silicon dies on a substrate and a method for yielding the array are provided. The method comprises: delineating an array of die areas on a crystalline semiconductor wafer; implanting the die areas with hydrogen ions; overlying the die areas with a layer of polymer to form, for each die, an aggregate including a die area first wafer layer; polymerically bonding an optically clear carrier to the die areas; thermally annealing the wafer to induce breakage in the wafer; forming, for each die, an aggregate wafer second layer with a thickness less than the die thickness; and, for each die, conformably attaching the aggregate wafer second layer to a substrate. The substrate can have an area of up to approximately two square meters and the wafer second layer can have a thickness of greater than and equal to approximately 20 nanometers.

Abstract: A multilayer structure with controlled internal stresses comprising, in this order, a first main layer (110a), at least a first constraint adaptation layer (130) in contact with the first main layer, at least a second stress adaptation layer (120) put into contact by adhesion with said first stress adaptation layer, and a second main layer (110b) in contact with the second stress adaptation layer, the first and second stress adaptation layers having contact stresses with the first and second main layers. Application to the realization of electronic circuits and membrane devices.

Abstract: A method of fabricating a film of active devices is provided. First damaged regions are formed, in a substrate, underneath first areas of the substrate where active devices are to be formed. Active devices are formed onto the first areas. Second damaged regions are formed, in the substrate, between the first damaged regions. The film is caused to detach from a rest of the substrate at a location where the first and second damaged regions are formed.

Abstract: In a method for reclaiming a delaminated wafer produced as a by-product in the production of bonded wafer by the ion implantation and delamination method, at least ion-implanted layer on a chamfered portion of the delaminated wafer is removed, and then a surface of the wafer is polished. Specifically, at least a chamfered portion of the delaminated wafer is subjected to an etching treatment and/or processing by chamfering, and then a surface of the wafer is polished. Alternatively, the delaminated wafer is subjected to a heat treatment, and then polished. There are provided a method for reclaiming a delaminated wafer, which provides a reclaimed wafer of high quality that does not generate particles even when it is subjected to a heat treatment with good yield, and such a reclaimed wafer.

Abstract: The spaces in chuck grooves 3a and 3b are evacuated to chuck the entire surface of a wafer 1 to the chuck surface of a wafer support table 3 and curve the wafer 1. A wafer 2 is horizontally opposed to the wafer 1, and the center of the wafer 2 is pressed by a press pin 6a. The centers of the two wafers 1 and 2 are contacted, and the contact portion gradually spreads to the vicinity of the periphery of a central portion 3c and takes a substantially circular shape. After that, the chuck by the chuck grooves 3a is stopped. Consequently, the wafer 1 flattens, and the entire surfaces of the wafers 1 and 2 are contacted.

Abstract: A wafer pair comprising a substantially defect-free germanium wafer and methods of making the same. The wafer pair comprises the substantially defect-free germanium wafer directly bonded to a silicon wafer. The method of making the wafer pair comprises placing the silicon wafer in a wafer-bonding chamber, placing the germanium wafer on top or on bottom of the silicon wafer, and applying a local force to either the germanium wafer or to the silicon wafer to initiate bonding of the germanium wafer to the silicon wafer. The bonding occurs under a temperature ranging from about 23° C. to about 600° C. and under a vacuum condition inside a wafer-bonding chamber.

Abstract: A process for producing a semiconductor article is provided which comprises the steps of bonding a film onto a substrate having a porous semiconductor layer, and separating the film from the substrate at the porous semiconductor layer by applying a force to the film in a peeling direction.

Abstract: A microelectronic assembly is made by bonding the tip ends of leads on a first element to bonding contacts on a second element. The tip ends of the leads are releasably connected to the first element, so that the leads are held in place during the bonding process. After bonding, the first and second elements are heated or cooled to cause differential thermal expansion, which breaks at least some of the releasable attachments of the tip ends, leaving the leads free to flex.

Abstract: In a method of manufacturing a bonded substrate stack by bonding a first substrate having a porous layer to a second substrate to prepare a bonded substrate stack, and separating the bonded substrate stack into two substrates at the porous layer, defects in the separation step are prevented. A first substrate having a porous layer inside, a single-crystal Si layer on the porous layer, and an SiO2 layer on the single-crystal Si layer is bonded to a second substrate. The outer peripheral portion of the substrate is oxidized to make the outer peripheral edge of the single-crystal Si layer retreat toward the inside to prepare a bonded substrate stack in which the outer peripheral edge of the single-crystal Si layer is located inside the outer peripheral edge of the bonding region. After that, the bonded substrate stack is separated into two substrates at the porous layer.

Abstract: A method for making a silicon substrate having a buried thin silicon oxide film is described. The method consists of: a) producing a first element having a first silicon body whereof the main surface is coated, in succession, with a buffer layer of germanium, or of an alloy of germanium and silicon, and with a thin silicon film; b) producing a second element, having a silicon body whereof a main surface is coated with a thin silicon oxide film; c) linking the first element with the second element such that the thin silicon film of the first element is in contact with the thin silicon oxide film of the second element; and d) eliminating the buffer layer to recuperate the silicon substrate having a buried thin silicon oxide film and a reusable silicon substrate. The method may be useful in making microelectronic devices such as CMOS and MOSFET devices.

Abstract: An electrode connecting method of connecting a first electrode and a second electrode is disclosed. The respective bonding surfaces of the first and second electrodes are activated. Then, each of the first and second electrodes having the activated surfaces is coated with a coating member for maintaining an activated state. A solid state bond between the first electrode and the second electrode is formed by pressure welding the first electrode and the second electrode so that the first and second electrodes break through the coating members.

Abstract: In a method for reclaiming a delaminated wafer produced as a by-product in the production of bonded wafer by the ion implantation and delamination method, at least ion-implanted layer on a chamfered portion of the delaminated wafer is removed, and then a surface of the wafer is polished. Specifically, at least a chamfered portion of the delaminated wafer is subjected to an etching treatment and/or processing by chamfering, and then a surface of the wafer is polished. Alternatively, the delaminated wafer is subjected to a heat treatment, and then polished. There are provided a method for reclaiming a delaminated wafer, which provides a reclaimed wafer of high quality that does not generate particles even when it is subjected to a heat treatment with good yield, and such a reclaimed wafer.

Abstract: An insulating substrate has a plurality of semiconductor chip mounting sections arranged one by one along a predetermined direction extending from one to the other end of the substrate, and a resin transmitting port. The resin transmitting port is located at a position in the vicinity of the one end along the predetermined direction and other than the semiconductor chip mounting section arranged nearest to the one end. A semiconductor chip is mounted on a respective semiconductor chip mounting section. A mold defines a cavity, including first and second cavity sections on the respective surfaces of the substrate, in such a manner that the first and second cavities communicates with each other by means of the resin transmitting port. A sealing resin is injected into the cavity, so that the resin flows through the resin transmitting port to fill both of the first and second cavity sections with the sealing resin.

Abstract: A method for manufacturing a bonded wafer, in which when a bonded wafer is manufactured using an ion implantation separation method, impurities attached in the ion implantation step can be removed effectively, and less failure called a void is generated on the bonding surface. Impurities such as particles or organic substances attached in ion implantation step (c) are removed using a physical removal method (d). The surface of a first wafer (1) subjected to impurities removal is closely contacted onto the surface of a second wafer (2) for heat treatment (e). The first wafer is separated in a thin-film form at a micro bubble layer (f).

Abstract: A method for making an array of thin single-crystal substrates on a handle substrate comprising the steps: attaching a plurality of single-crystal substrates to a face of a support wafer; polishing said plurality of attached single-crystal substrates so that said single-crystal substrates surfaces are coplanar on said support surface and to a selected surface roughness; implanting a hydrogen to a selected depth into said attached single-crystal substrates; bonding said polished and hydrogen implanted attached single-crystal substrates to a first handle substrate; and splitting said polished and hydrogen implanted attached single-crystal substrates at said selected depth thereby forming an array of thin single-crystal substrates on said first handle substrate and a support wafer having a remaining portion of said attached single-crystal substrates.

Abstract: A semiconductor device is manufactured by an integrated circuit forming process, and a series of subsequent steps. In the series of steps, a protection tape 18 is adhered onto a first surface of a semiconductor substrate on which a plurality of semiconductor elements are formed, and the second surface of the semiconductor substrate is ground so that the semiconductor substrate has a desired thickness, the semiconductor substrate is then conveyed while controlling the temperature of the semiconductor substrate. The semiconductor substrate is then separated into a plurality of semiconductor elements. The occurrence of warping on the semiconductor substrate during conveyance of the semiconductor substrate is thus prevented.

Abstract: A method for fabricating semiconductor wafers as multiple-depth structure (i.e., having portions of varying height). The method includes patterning a first substrate and bonding a second substrate to the first. This process creates a subsurface patterned layer. Portions of the second substrate may then be etched, exposing the subsurface patterned layer for selective processing. For example, the layered structure may then be repeatedly etched to produce a multiple depth structure. Or, for example, exposed portions of the first substrate may have material added to them to create multiple-depth structures. This method of fabrication provides substantial advantages over previous methods.

Abstract: A process for producing a semiconductor article is provided which comprises the steps of bonding a film onto a substrate having a porous semiconductor layer, and separating the film from the substrate at the porous semiconductor layer by applying a force to the film in a peeling direction.

Abstract: Systems for assembling wafer stacks are provided. An embodiment of the system includes a vacuum chamber, a media deposition component and a wafer stack assembly component. The media deposition component is arranged within the vacuum chamber and is configured to deposit storage media upon a first wafer. The wafer stack assembly component also is arranged within the vacuum chamber. The wafer stack assembly component is configured to align the first wafer and a second wafer relative to each other and bond the first wafer and the second wafer together while at least a portion of the vacuum chamber is maintained under vacuum pressure. So configured, the interior chamber of the wafer stack can be formed as well as maintained under vacuum pressure. Methods also are provided.

Abstract: A new method of producing strained crystalline semiconductor microelectronic devices. Microelectronic devices can either be formed within a membrane, prior to straining or processed after straining. The method includes the steps of straining a membrane along at least one axis and straining using wafer-bonding techniques.

Abstract: A method of improving the physical and/or electrical and/or magnetic properties of a thin film material formed on a substrate, wherein the properties of the thin film material are stress-dependent, by selectively applying force to the substrate during the film formation and/or thereafter during the cooling of the film in the case of a film formed at elevated temperature, to impose through the substrate an applied force condition opposing or enhancing the retention of stress in the product film. The method of the invention has particular utility in the formation of ferroelectric thin films which are grown at temperature above the Curie temperature, and which may be placed in tension during the cooling of the film to provide ferroelectric domains with polarization in the plane of the film.

Abstract: In pre-treating a surface of a substrate in a process of forming a narrowed thin film pattern on the surface of the substrate from a solution such as a plating liquid, a mask with an opening corresponding to the thin film pattern to be formed later is formed on the surface of the substrate. Then, by micronizing a pre-treating liquid such as a water, a plating liquid, an acidic liquid ad an alkaline liquid, an atmosphere containing microparticles having diameters smaller than the minimum distance of the opening of the mask is produced. The substrate is positioned into the atmosphere, and the microparticles of the pre-treating liquid are stuck on the surface of the substrate exposing to the lower part of the opening of the mask. In using a water as the pre-treating liquid, the substrate is positioned into an atmosphere containing moisture vapor and the water particles are stuck on the surface of the substrate through their condensation.

Abstract: In the previously known methods, the buried layers, such as suicide for example, are produced on SOI wafers by thinning the wafer bonded onto the SOI wafer to the desired thickness, and then isolating the layers grown on the SOI wafer by means of a trench process.

Abstract: A semiconductor device substrate which can be easily conveyed and a semiconductor device fabrication method using the substrate. The semiconductor device fabrication method includes forming a solder resist on a semiconductor element mounting plate-shaped substrate having major and minor sides and containing organic matter, having a linear expansion coefficient A different from that of the substrate, warping the substrate along a minor-side direction, and conveying the warped substrate.

Abstract: In a multi-layer interconnection structure, the wiring length is to be reduced, and the interconnection is to be straightened, at the same time as measures need to be taken against radiation noise. To this end, there is disclosed a semiconductor device in which plural semiconductor substrates, each carrying semiconductor elements, are bonded together. On each semiconductor substrate is deposited an insulating layer through which is formed a connection wiring passed through the insulating layer so as to be connected to the interconnection layer of the semiconductor element. On a junction surface of at least one of the semiconductor substrates is formed an electrically conductive layer of an electrically conductive material in which an opening is bored in association with the connection wiring. The semiconductor substrates are bonded together by the solid state bonding technique to interconnect the connection wirings formed on each semiconductor substrate.

Abstract: A method of producing a strained crystalline semiconductor microelectronic device(s). Microelectronic device(s) are formed within a membrane. The method includes the steps of straining a membrane along at least one axis and bonding the membrane to a base substrate.

Abstract: The spaces in chuck grooves 3a and 3b are evacuated to chuck the entire surface of a wafer 1 to the chuck surface of a wafer support table 3 and curve the wafer 1. A wafer 2 is horizontally opposed to the wafer 1, and the center of the wafer 2 is pressed by a press pin 6a. The centers of the two wafers 1 and 2 are contacted, and the contact portion gradually spreads to the vicinity of the periphery of a central portion 3c and takes a substantially circular shape. After that, the chuck by the chuck grooves 3a is stopped. Consequently, the wafer 1 flattens, and the entire surfaces of the wafers 1 and 2 are contacted.

Abstract: A thin transition-metal based scattering layer of a mask blank for use in EPL systems is formed by providing the thin transition-metal scattering layer directly over membrane layers on a lot of substrates, thereby forming a continuous contact between the single transition metal-based scattering layer and the membrane layer. Preferably, the single transition metal-based scattering layer is a single tantalum-silicon composite scattering layer having a stoichiometry of TaxSi. The deposition parameters for depositing the thin transition-metal based scattering layer are adjusted to provide the scattering layer uniformly over all substrates within the lot. A first substrate from the lot of substrates is then selected, an initial stress measurement of the scattering layer is determined and then the substrate is annealed at a first temperature.

Abstract: An integrated circuit chip wherein one or more semiconductor devices are completely isolated from bulk effects of other semiconductor devices in the same circuit and a method of making the integrated circuit chip. The devices may be passive devices such as resistors, or active devices such as diodes, bipolar transistors or field effect transistors (FETs). A multi-layer semiconductor body is formed of, preferably silicon and silicon dioxide. A conducting region or channel is formed in one or more of the layers. For the FET, silicon above and below the channel region provides controllable gates with vertically symmetrical device characteristics. Buried insulator layers may be added to isolate the lower gate of individual devices from each other and to create multiple vertically stacked isolated devices. Both PFET and NFET devices can be made with independent doping profiles in both depletion and accumulation modes.

Abstract: There is provided a method of fabricating an SOI wafer having high quality by hydrogen ion delamination method wherein a damage layer remaining on the surface of the SOI layer after delamination and surface roughness are removed maintaining thickness uniformity of the SOI layer. According to the present invention, there are provided a method of fabricating an SOI wafer by hydrogen ion delamination method wherein an oxide film is formed on an SOI layer by heat treatment in an oxidizing atmosphere after bonding heat treatment, then the oxide film is removed, and subsequently heat treatment in a reducing atmosphere is performed; a method of fabricating an SOI wafer by hydrogen ion delamination method wherein an oxide film is formed on an SOI layer by heat treatment in an oxidizing atmosphere after delaminating heat treatment, then the oxide film is removed, and subsequently heat treatment in a reducing atmosphere is performed; and an SOI wafer fabricated by the methods.

Abstract: On the scribe line area formed between a plurality of semiconductor clip areas on a semiconductor wafer, there is provided a chipping prevention portion constituted by a double groove consisting of the first and second grooves. Thus, the entry of chipping into the semiconductor chip area is prevented when dicing the semiconductor wafer along the scribe line area provided between each of the semiconductor chip areas. In this respect, an insulating film may be formed on the surface of the semiconductor wafer on the side of an element forming area.

Abstract: A substrate containing a compound semiconductor layer comprises a substrate layer 11, a first semiconductor layer 12 formed on the substrate layer 11, and a second semiconductor layer 13 made of a Group III nitride-based compound semiconductor formed on the first semiconductor layer 12. The semiconductor layer 12 is provided with a plurality of pores 14. Thus, a compound semiconductor layer containing a Group III nitride-based compound semiconductor with excellent surface planarity and crystallinity can be provided, as well as a method for manufacturing the same, and a semiconductor device using the same.

Abstract: In a semiconductor device including a substrate which has a primary surface, a conduction wire formed on the primary surface, a semiconductor element which has a secondary surface, a projective electrode formed on the secondary surface, an insulative resin for adhesion which is applied between the primary surface and the secondary surface and which shrinks by hardening thereof, the substrate and the semiconductor element are adhered to each other by the hardening of the insulative resin with the projective electrode and the conduction wire corresponding with each other, so that an electrical connection between the projective electrode and the conduction wire is achieved and that a residual stress is generated in the insulative resin. The residual stress has a maximum value thereof around the projective electrode.

Abstract: There is disclosed a method of recycling a delaminated wafer produced as a by-product in producing an SOI wafer according to a hydrogen ion delaminating method by reprocessing it for reuse as a silicon wafer, wherein at least polishing of the delaminated wafer for removing of a step in the peripheral part of the delaminated wafer and heat treatment in a reducing atmosphere containing hydrogen are conducted as the reprocessing. There are provided a method of appropriately reprocessing a delaminated wafer produced as a by-product in a hydrogen ion delaminating method to reuse it as a silicon wafer actually, and particularly, a method of reprocessing an expensive wafer such as an epitaxial wafer many times for reuse, to improve productivity of SOI wafer having a high quality SOI layer, and to reduce producing cost.

Abstract: A method of preparing a semiconductor wafer includes the step of forming first and second layers of a first material on opposing respective first and second faces of the semiconductor wafer. The second layer of the first material is then removed from the second face of the semiconductor wafer. More particularly, the first material can be polysilicon. Warping of the semiconductor wafer can thus be reduced.

Abstract: This invention relates to a composite member separating method in which a first member (1) having a separation layer (4) and a transfer layer (5) on the separation layer (4) is bonded to a second member (2) is separated at a position different from the bonding interface between the first member (1) and the second member (2), the method comprising the steps of, applying a force asymmetric with respect to the interface to the end portion of the composite member to form a crack (7A) that runs from the surface of the first member (1) to the separation layer (4) through the transfer layer (5), and then, growing the crack is grown along the separation layer (4) to completely separate the composite member.

Abstract: In accordance with the present invention, a preferred method for bonding a single crystal membrane to a supporting structure having a curved surface includes the steps of segmenting a unitary wafer of a single crystal, for example semiconductor material, into a plurality of semi-attached wafer segments and then aligning a supporting structure with each of the wafer segments. The wafer segments are then detached from each other and are individually bonded to one of the supporting structures. In the case of silicon, lattice strain each of the segments is relieved by depositing a layer of germanium onto the surface of the silicon membrane and then thermally processing the assembly so that germanium atoms are either nucleate on the surface to form quantum wires or diffused into the lattice to relieve the lattice strain.

Abstract: A method of improving the physical and/or electrical and/or magnetic properties of a thin film material formed on a substrate, wherein the properties of the thin film material are stress-dependent, by selectively applying force to the substrate during the film formation and/or thereafter during the cooling of the film in the case of a film formed at elevated temperature, to impose through the substrate an applied force condition opposing or enhancing the retention of stress in the product film. The method of the invention has particular utility in the formation of ferroelectric thin films which are grown at temperature above the Curie temperature, and which may be placed in tension during the cooling of the film to provide ferroelectric domains with polarization in the plane of the film.

Abstract: The method of the present invention provides a process for manufacturing MEMS devices having more precisely defined mechanical and/or electromechanical members. The method of the present invention begins by providing a partially sacrificial substrate and a support substrate. In order to space the mechanical and/or electromechanical members of the resulting MEMS device above the support substrate, mesas are formed on the support substrate. By forming the mesas on the support substrate instead of the partially sacrificial substrate, the mechanical and/or electromechanical members can be more precisely formed from the partially sacrificial substrate since the inner surface of the partially sacrificial substrate is not etched and therefore remains planar. As such, trenches can be precisely etched through the planar inner surface of the partially sacrificial substrate to define mechanical and/or electromechanical members of the MEMS device.

Abstract: In a process for producing a semiconductor substrate, comprising sealing surface pores of a porous silicon layer and thereafter forming a single-crystal layer on the porous silicon layer by epitaxial growth, intermediate heat treatment is carried out after the sealing and before the epitaxial growth and at a temperature higher than the temperature at the time of the sealing. This process improves crystal quality of the semiconductor substrate having the single-crystal layer formed by epitaxial growth and improves smoothness at the bonding interface when applied to bonded wafers this process enables the detection of the smaller particles on the surface by a laser light scattering method.

Abstract: A compound semiconductor pellet for a high electron mobility transistor is bonded to a metal plate heat sink of gold, and the metal plate heat sink is soldered to a package, wherein the metal plate heat sink is subjected to an orientation under application of heat before the soldering so as to cure warp of the compound semiconductor pellet, thereby decreasing the thermal stress due to the heat during the soldering.

Abstract: A device for bending a flat, round disc element, especially for forming a widened gap between two adjacent, facing disc elements which are to be glued together, includes a first part for contact with a first portion of the disc element, a second part for contact with a second portion of the disc element. The second, radially outer part is axially movable relative to the first part. A vacuum source is disposed to bend the radially outer portion of the disc element as the second part is retracted.

Abstract: A method for fabricating an interconnected multiple circuit chip structure by etching a first substrate to form protrusions on its surface. Then the protrusions are preferentially etched to produce a selected shape such as a tetragonal protrusion and an integrated circuit is then fabricated on the substrate. A second substrate is preferentially etched to form recesses having a selected shape that is the complement of the selected shape of the protrusions of the first substrate and then an integrated circuit is fabricated on the second substrate. The protrusions and recesses are coated with an electrically conductive metal such as aluminum. The first and second substrates are joined and aligned together such that the protrusions mate with the recesses and the structure is annealed such that the metal coatings thereon come into contact to electrically connect the integrated circuits on the substrates. The method can also be used to electrically connect multiple chips mounted back to front.

Abstract: A process for producing a semiconductor article is provided which comprises the steps of bonding a film onto a substrate having a porous semiconductor layer, and separating the film from the substrate at the porous semiconductor layer by applying a force to the film in a peeling direction.