Subsequent Separation Into Plural Bodies (e.g., Delaminating, Dicing, Etc.) Patents (Class 438/458)
  • Patent number: 11887968
    Abstract: A semiconductor package includes a base structure having a base pad, a first semiconductor chip on the base structure, and having a first connection pad bonded to the base pad, a first bonding structure including an base insulation layer of a base structure and a first lower insulation layer of the first semiconductor chip bonded to the base insulation layer, a second semiconductor chip on the first semiconductor chip, and having a second connection pad connected to the first through-electrode, and a second bonding structure including a first upper insulation layer of the first semiconductor chip, and a second lower insulation layer of the second semiconductor chip bonded to the first upper insulation layer, and the first upper insulation layer has a dummy insulation portion extending onto the base structure around the first semiconductor chip.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: January 30, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji Hwan Hwang, Ji Hoon Kim, Ji Seok Hong, Tae Hun Kim, Hyuek Jae Lee
  • Patent number: 11856800
    Abstract: A semiconductor device and method of manufacture are provided wherein the semiconductor device includes a first system on chip device bonded to a first memory device, a second system on chip device bonded to the first memory device, a first encapsulant surrounding the first system on chip device and the second system on chip device, a second encapsulant surrounding the first system on chip device, the second system on chip device, and the first memory device, and a through via extending from a first side of the second encapsulant to a second side of the first encapsulant, the through via being located outside of the first encapsulant.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Hsien-Wei Chen, Wen-Chih Chiou, Ming-Fa Chen, Sung-Feng Yeh
  • Patent number: 11851321
    Abstract: A micro electro mechanical system (MEMS) includes a circuit substrate comprising electronic circuitry, a support substrate having a recess, a bonding layer disposed between the circuit substrate and the support substrate, through holes passing through the circuit substrate to the recess, a first conductive layer disposed on a front side of the circuit substrate, and a second conductive layer disposed on an inner wall of the recess. The first conductive layer extends into the through holes and the second conductive layer extends into the through holes and coupled to the first conductive layer.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ting-Li Yang, Kai-Di Wu, Ming-Da Cheng, Wen-Hsiung Lu, Cheng Jen Lin, Chin Wei Kang
  • Patent number: 11823924
    Abstract: In one embodiment, a semiconductor manufacturing apparatus includes a reformer configured to partially reform a first substrate to form a reformed layer between a first portion and a second portion in the first substrate. The apparatus further includes a joiner configured to form a joining layer between the first portion and a second substrate to join the first portion and the second substrate. The apparatus further includes a remover configured to remove the second portion from a surface of the second substrate while making the first portion remain on the surface of the second substrate by separating the first portion and the second portion.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: November 21, 2023
    Assignee: Kioxia Corporation
    Inventor: Aoi Suzuki
  • Patent number: 11735411
    Abstract: A method for manufacturing a semiconductor device includes chucking in which a semiconductor device wafer is attached to an upper surface of a chuck mechanism with its device surface down; and edge trimming performed after the chucking, wherein the edge trimming comprises: rotating the semiconductor device water horizontally by the chuck mechanism; rotating a rotating blade horizontally by a vertical spindle to which an ultrasonic wave is applied and trimming a circumferential side surface of the semiconductor device wafer by the rotating blade.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: August 22, 2023
    Assignee: OKAMOTO MACHINE TOOL WORKS, LTD.
    Inventors: Eiichi Yamamoto, Takahiko Mitsui, Tsubasa Bando
  • Patent number: 11688622
    Abstract: In a laser irradiation apparatus 1 according to one embodiment, each of first and second flotation units 30a, 30b includes a base 31, and a porous plate 32 bonded to an upper surface of the base 31 by an adhesive layer 34, the base 31 includes a rising portion 312 protruding upward at an outer periphery facing at least the gap, and the porous plate 32 includes a cutout portion 321 configured to fit to the rising portion 312, and the adhesive layer 34 is formed along an inner wall of the rising portion 312 having fitted to the cutout portion 321.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: June 27, 2023
    Assignee: JSW AKTINA SYSTEM CO., LTD
    Inventor: Yuki Suzuki
  • Patent number: 11610993
    Abstract: Aspects of the disclosure provide a method of forming a semiconductor apparatus including a first portion and a second portion. The first portion is formed on a first substrate and includes at least one first semiconductor device. The second portion is formed on a second substrate including a bulk substrate material and includes at least one second semiconductor device. A carrier substrate is attached to the second portion. The bulk substrate material is removed from the second substrate. The first portion and the second portion are bonded to form the semiconductor apparatus where the at least one second semiconductor device is stacked above the at least one first semiconductor device along a Z direction substantially perpendicular to a substrate plane of the first substrate. The at least one first semiconductor device and the at least one second semiconductor device are positioned between the carrier substrate and the first substrate.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: March 21, 2023
    Assignee: Tokyo Electron Limited
    Inventors: Mark I. Gardner, H. Jim Fulford
  • Patent number: 11610806
    Abstract: A production method for a semi-conductor-on-insulator type multilayer stack includes ion implantation in a buried portion of a superficial layer of a support substrate, so as to form a layer enriched with at least one gas, intended to form a porous semi-conductive material layer, the thermal oxidation of a superficial portion of the superficial layer to form an oxide layer extending from the surface of the support substrate, the oxidation and the implantation of ions being arranged such that the oxide layer and the enriched layer are juxtaposed, and the assembly of the support substrate and of a donor substrate.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: March 21, 2023
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Shay Reboh, Pablo Acosta Alba
  • Patent number: 11575006
    Abstract: An electronic or optoelectronic device includes: (1) a layer of a first material; and (2) a layer of a second material disposed on the layer of the first material, wherein the first material is different from the second material, and the layer of the first material is spaced from the layer of the second material by a gap.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: February 7, 2023
    Assignee: The Regents of the University of California
    Inventors: Xiangfeng Duan, Yu Huang, Yuan Liu
  • Patent number: 11575020
    Abstract: A method of forming a bipolar transistor with a vertical collector contact requires providing a transistor comprising a plurality of epitaxial semiconductor layers on a first substrate, and providing a host substrate. A metal collector contact is patterned on the top surface of the host substrate, and the plurality of epitaxial semiconductor layers is transferred from the first substrate onto the metal collector contact on the host substrate. The first substrate is suitably the growth substrate for the plurality of epitaxial semiconductor layers. The host substrate preferably has a higher thermal conductivity than does the first substrate, which improves the heat dissipation characteristics of the transistor and allows it to operate at higher power densities. A plurality of transistors may be transferred onto a common host substrate to form a multi-finger transistor.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: February 7, 2023
    Assignee: Teledyne Scientific & Imaging, LLC
    Inventors: Miguel Urteaga, Andy Carter
  • Patent number: 11575063
    Abstract: The invention relates to a method for fabricating a thermal detector (1), comprising the following steps: forming a first stack (10), comprising a thermal detector (20), a mineral sacrificial layer (15) and a thin encapsulation layer (16) having a lateral vent (17.1); forming a second stack (30), comprising a thin sealing layer (33) and a getter portion (34); eliminating the mineral sacrificial layer (15); assembling by direct bonding the thin sealing layer (33), brought into contact with the thin encapsulation layer (16) and blocking the lateral vent (17.1), the getter portion (34) being located in the lateral vent (17.1).
    Type: Grant
    Filed: November 27, 2020
    Date of Patent: February 7, 2023
    Assignee: Commissariat à l'Energie Atomique et aux Energies Alternatives
    Inventors: Sébastien Becker, Frank Fournel
  • Patent number: 11557506
    Abstract: Methods for processing a semiconductor substrate are proposed. An example of a method includes forming cavities in the semiconductor substrate by implanting ions through a first surface of the semiconductor substrate. The cavities define a separation layer in the semiconductor substrate. A semiconductor layer is formed on the first surface of the semiconductor substrate. Semiconductor device elements are formed in the semiconductor layer. The semiconductor substrate is separated along the separation layer into a first substrate part including the semiconductor layer and a second substrate part.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: January 17, 2023
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Werner Schustereder, Alexander Breymesser, Mihai Draghici, Tobias Franz Wolfgang Hoechbauer, Wolfgang Lehnert, Hans-Joachim Schulze, Marko David Swoboda
  • Patent number: 11552123
    Abstract: A front-side type image sensor may include a substrate successively including: a P? type doped semiconducting support substrate, an electrically insulating layer and a semiconducting active layer, and a matrix array of photodiodes in the active layer of the substrate. The substrate may include, between the support substrate and the electrically insulating layer, a P+ type doped semiconducting epitaxial layer.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: January 10, 2023
    Assignee: Soitec
    Inventor: Walter Schwarzenbach
  • Patent number: 11508612
    Abstract: A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel comprises a charge trapping layer (CTL).
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: November 22, 2022
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Igor Peidous, Andrew M Jones, Srikanth Kommu, Horacio Josue Mendez
  • Patent number: 11476137
    Abstract: A dividing apparatus includes a table having a transparent plate having a holding surface for holding a workpiece thereon and a lower illumination unit for illuminating the holding surface from below, a first storage section for storing a first image including a white portion where illumination light from the lower illumination unit is transmitted through the workpiece and displayed as white and a black portion where the illumination light is blocked by the workpiece and displayed as black when an image of a kerf defined by a dividing unit in the workpiece held on the holding surface is captured by an image capturing unit with the lower illumination unit being energized, and a white pixel detecting section for detecting whether or not there are pixels in the white portion of the first image in directions perpendicular to directions along which a street extends.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: October 18, 2022
    Assignee: DISCO CORPORATION
    Inventors: Hironari Ohkubo, Ken Jou
  • Patent number: 11393772
    Abstract: The present disclosure provides a bonding method for a semiconductor substrate, which may improve flatness of a bonded substrate. The present disclosure further provides a bonded semiconductor substrate. The semiconductor substrate is thermally treated prior to bonding, and oxygen precipitates in the semiconductor substrate are partially or totally converted to interstitial oxygen atoms in the thermal treatment.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: July 19, 2022
    Assignee: Shanghai Simgui Technology Co., Ltd.
    Inventors: Xing Wei, Xin Su, Hongtao Xu, Meng Chen, Nan Gao
  • Patent number: 11387629
    Abstract: An intermediate ultraviolet laser diode device includes a gallium and nitrogen containing substrate member comprising a surface region, a release material overlying the surface region, an n-type gallium and nitrogen containing material; an active region overlying the n-type gallium and nitrogen containing material; a p-type gallium and nitrogen containing material; a first transparent conductive oxide material overlying the p-type gallium and nitrogen containing material; and an interface region overlying the first transparent conductive oxide material.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: July 12, 2022
    Assignee: KYOCERA SLD Laser, Inc.
    Inventors: James W. Raring, Melvin McLaurin, Paul Rudy, Po Shan Hsu, Alexander Sztein
  • Patent number: 11373898
    Abstract: A method for manufacturing a semiconductor on insulator type structure by transfer of a layer from a donor substrate onto a receiver substrate, comprises: a) the supply of the donor substrate and the receiver substrate, b) the formation in the donor substrate of an embrittlement zone delimiting the layer to transfer, c) the bonding of the donor substrate on the receiver substrate, the surface of the donor substrate opposite to the embrittlement zone with respect to the layer to transfer being at the bonding interface, and d) the detachment of the donor substrate along the embrittlement zone. A step of controlled modification of the curvature of the donor substrate and/or the receiver substrate is performed before the bonding step.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: June 28, 2022
    Assignee: Soitec
    Inventors: Daniel Delprat, Damien Parissi, Marcel Broekaart
  • Patent number: 11355664
    Abstract: In various embodiments, extraction efficiency of light-emitting devices fabricated on aluminum nitride substrates is enhanced via removal of at least a portion of the substrate.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: June 7, 2022
    Assignee: CRYSTAL IS, INC.
    Inventors: James R. Grandusky, Leo J. Schowalter, Craig Moe
  • Patent number: 11355487
    Abstract: An integrated circuit includes a semiconductor substrate, transistors on the semiconductor, horizontal routing tracks extending in a first direction in a first metal layer, and one or more backside routing tracks extending in the first direction in a backside metal layer. Each transistor has a gate terminal, a source terminal, and a drain terminal. A first transistor has a first terminal, a second terminal, and a third terminal. A first horizontal routing track of the horizontal routing tracks is conductively connected to the first terminal of the first transistor through a via connector. A first backside routing track is conductively connected to the second terminal of the first transistor through a backside via connector. The backside metal layer and the first metal layer are formed at opposite sides of the semiconductor substrate.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: June 7, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-An Lai, Shih-Wei Peng, Wei-Cheng Lin, Jiann-Tyng Tzeng
  • Patent number: 11322405
    Abstract: According to an embodiment of inventive concepts, a substrate dicing method may include forming reformed patterns in a substrate using a laser beam, grinding a bottom surface of the substrate to thin the substrate, and expanding the substrate to divide the substrate into a plurality of semiconductor chips. The forming of the reformed patterns may include forming a first reformed pattern in the substrate and providing an edge focused beam to a region crossing the first reformed pattern to form a second reformed pattern in contact with the first reformed pattern.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: May 3, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Junho Yoon, Jungchul Lee, Byungmoon Bae, Junggeun Shin, Hyunsu Sim
  • Patent number: 11315790
    Abstract: A method may include providing a substrate in a plasma chamber, the substrate comprising a monocrystalline semiconductor, having an upper surface. The method may include initiating a plasma in the plasma chamber, the plasma comprising an amorphizing ion species, and applying a pulse routine to the substrate, the pulse routine comprising a plurality of extraction voltage pulses, wherein a plurality of ion pulses are directed to the substrate, and wherein an ion dose per pulse is greater than a threshold for low dose amorphization.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: April 26, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Supakit Charnvanichborikarn, Christopher R. Hatem
  • Patent number: 11309399
    Abstract: A process for preparing a thin layer made of ferroelectric material based on alkali metal, exhibiting a determined Curie temperature, transferred from a donor substrate to a carrier substrate by using a transfer technique including implanting light species into the donor substrate in order to produce an embrittlement plane, the thin layer having a first, free face and a second face that is arranged on the carrier substrate. The process comprises a first heat treatment of the transferred thin layer at a temperature higher than the Curie temperature, the thin layer exhibiting a multi-domain character upon completion of the first heat treatment, and introducing, after the first heat treatment, protons into the thin layer, followed by applying a second heat treatment of the thin layer at a temperature lower than the Curie temperature to generate an internal electric field that results in the thin layer being made single domain.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: April 19, 2022
    Assignee: Soitec
    Inventor: Alexis Drouin
  • Patent number: 11294272
    Abstract: The present application discloses a donor substrate for depositing a deposition material on an acceptor substrate. The donor substrate includes a base substrate; a patterned thermal barrier layer on the base substrate; and a plurality of openings each of which extending through the patterned thermal barrier layer.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: April 5, 2022
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Lujiang Huangfu
  • Patent number: 11276605
    Abstract: A method of fabricating a semiconductor substrate includes the following activities: a) providing a donor substrate with a weakened zone inside the donor substrate, the weakened zone forming a border between a layer to be transferred and the rest of the donor substrate, b) attaching the donor substrate to a receiver substrate, the layer to be transferred being located at the interface between the donor substrate and the receiver substrate; c) detaching the receiver substrate along with the transferred layer from the rest of the donor substrate, at the weakened zone; and d) at least one step of smoothing the surface of the transferred layer, wherein the semiconductor substrate obtained from step c) is kept, at least from the moment of detachment until the end of the smoothing step, in a non-oxidizing inert atmosphere or in a mixture of non-oxidizing inert gases. Semiconductor substrates are fabricated using such a method.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: March 15, 2022
    Assignee: Soitec
    Inventors: Oleg Kononchuk, Didier Landru, Nadia Ben Mohamed
  • Patent number: 11264279
    Abstract: Systems and methods for manufacturing flexible electronics are described herein. Methods in accordance with embodiments of the present technology can include disposing electrical features, such as thin film circuits, on a first side of a glass substrate, applying a first protective material over the electronic features, and exposing a second side of the glass substrate to a chemical etching tank to thin the glass substrate to a predetermined thickness. The thinning process can remove cracks and other defects from the second side of the glass substrate and enhance the flexibility of the electronic assembly. A second protective material can be disposed on the second side of the thinned glass substrate to maintain the enhanced backside surface of the glass substrate. In some embodiments, the method also includes singulating the plurality of electronic features into individual electronic components by submerging the electronic assembly into a chemical etching tank.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: March 1, 2022
    Assignee: NEXT Biometrics Group ASA
    Inventors: Tian Xiao, King Hong Kwan, Sheng-Hsiang Hung, Mark W. Naumann
  • Patent number: 11257801
    Abstract: A stacked semiconductor package includes a first semiconductor chip having a first active surface over which first bonding pads including peripheral bonding pads and central bonding pads are arranged, a first encapsulation member, two second semiconductor chips having second active surfaces over which second bonding pads are arranged at one side peripheries and disposed to be separated from each other such that the second active surfaces face the first active surface and the second bonding pads overlap with the peripheral bonding pads, first coupling members interposed between the peripheral bonding pads and the second bonding pads, a second encapsulation member formed over second side surfaces of the second semiconductor chips including a region between the second semiconductor chips, and a mold via formed through a portion of the second encapsulation member in the region between the second semiconductor chips and coupled with the central bonding pads.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: February 22, 2022
    Assignee: SK hynix Inc.
    Inventors: Sang-Eun Lee, Hyung-Dong Lee, Eun Ko
  • Patent number: 11251175
    Abstract: A three-dimensional integrated structure is formed by a first substrate with first components oriented in a first direction and a second substrate with second components oriented in a second direction. An interconnection level includes electrically conducting tracks that run in a third direction. One of the second direction and third direction forms a non-right and non-zero angle with the first direction. An electrical link formed by at least one of the electrically conducting tracks electrically connected two points of the first or of the second components.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: February 15, 2022
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexandre Ayres, Bertrand Borot
  • Patent number: 11245036
    Abstract: A semiconductor device according to the present disclosure includes an active region including a channel region and a source/drain region adjacent the channel region, a vertical stack of channel members over the channel region, a gate structure over and around the vertical stack of channel members, a bottom dielectric feature over the source/drain region, a source/drain feature over the bottom dielectric feature, and a germanium layer disposed between the bottom dielectric feature and the source/drain region.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: February 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Cheng Chen, Kuo-Cheng Chiang, Zhi-Chang Lin
  • Patent number: 11232975
    Abstract: Various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) substrate without bond interface voids and/or without delamination between layers. In some embodiments, a first high ? bonding structure is formed over a handle substrate. A device layer is formed over a sacrificial substrate. Outer most sidewalls of the device layer are between outer most sidewalls of the sacrificial substrate. A second high ? bonding structure is formed over the device layer. The first high ? bonding structure is bonded to the second high ? bonding structure, such that the device layer is between the sacrificial substrate and the handle substrate. A first removal process is performed to remove the sacrificial substrate. The first removal process comprises performing a first etch into the sacrificial substrate until the device layer is reached.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: January 25, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Ying Tsai, Yeur-Luen Tu
  • Patent number: 11222864
    Abstract: A semiconductor wafer support arrangement and method for processing a semiconductor wafer including an adhesive sheet may comprise: a layer of wafer supporting adhesive that has certain characteristics that permit wafer processing, e.g., wafer thinning, and removal of the processed wafer in condition for use without cleaning. The carrier or substrate for the wafer processing may be reusable, and the adhesive sheet may have plural layers and may include a flexible substrate.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: January 11, 2022
    Assignee: Amerasia International Technology
    Inventors: Kevin Kwong-Tai Chung, Frederick Lo
  • Patent number: 11211516
    Abstract: A stack-like III-V semiconductor product comprising a substrate and a sacrificial layer region arranged on an upper side of the substrate and a semiconductor layer arranged on an upper side of the sacrificial layer region. The substrate, the sacrificial layer region and the semiconductor layer region each comprise at least one chemical element from the main groups III and a chemical element from the main group V. The sacrificial layer region differs from the substrate and from the semiconductor layer in at least one element. An etching rate of the sacrificial layer region differs from an etching rate of the substrate and from an etching rate of the semiconductor layer region at least by a factor of ten. The sacrificial layer region is adapted in respect of its lattice to the substrate and to the semiconductor layer region.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: December 28, 2021
    Assignee: AZUR SPACE Solar Power GmbH
    Inventor: Gerhard Strobl
  • Patent number: 11177253
    Abstract: An electronic device includes a MOS transistor with a source and a drain, and a capacitor with a first plate connected directly to the source, and a second plate connected directly to the drain. A method to fabricate an electronic device includes fabricating a MOS transistor on or in a semiconductor structure, and fabricating a capacitor having a first plate connected directly to a source of the MOS transistor, and a second plate connected directly to a drain of the MOS transistor.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: November 16, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Christopher Boguslaw Kocon
  • Patent number: 11177434
    Abstract: An integrated fan-out package including an integrated circuit, a plurality of memory devices, an insulating encapsulation, and a redistribution circuit structure is provided. The memory devices are electrically connected to the integrated circuit. The integrated circuit and the memory devices are stacked, and the memory devices are embedded in the insulating encapsulation. The redistribution circuit structure is disposed on the insulating encapsulation, and the redistribution circuit structure is electrically connected to the integrated circuit and the memory devices. Furthermore, methods for fabricating the integrated fan-out package are also provided.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: November 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee
  • Patent number: 11168234
    Abstract: The present invention relates to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: November 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: James L. Hedrick, Robert D. Miller, Deborah A. Neumayer, Sampath Purushothaman, Mary E. Rothwell, Willi Volksen, Roy R. Yu
  • Patent number: 11158607
    Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: October 26, 2021
    Assignee: Apple Inc.
    Inventors: Sanjay Dabral, Jun Zhai, Kwan-Yu Lai, Kunzhong Hu, Vidhya Ramachandran
  • Patent number: 11146243
    Abstract: A bulk acoustic wave (BAW) filter for passing through electric signals in a preset frequency range is provided. The BAW filter includes: a diamond substrate; a passivation layer formed on the diamond substrate; a first metal layer formed on the passivation layer; a piezoelectric layer formed on the first metal layer; a second metal layer formed on a piezoelectric layer and a metal pad formed on the first metal layer. The metal pad, first metal layer, piezoelectric layer and second metal layer form an electrical path that allows an electrical signal within a preset frequency range to pass therethrough.
    Type: Grant
    Filed: February 2, 2020
    Date of Patent: October 12, 2021
    Assignee: RFHIC Corporation
    Inventor: Won Sang Lee
  • Patent number: 11107846
    Abstract: A technique is described in which a transistor formed using an oxide semiconductor film, a transistor formed using a polysilicon film, a transistor formed using an amorphous silicon film or the like, a transistor formed using an organic semiconductor film, a light-emitting element, or a passive element is separated from a glass substrate by light or heat. An oxide layer is formed over a light-transmitting substrate, a metal layer is selectively formed over the oxide layer, a resin layer is formed over the metal layer, an element layer is formed over the resin layer, a flexible film is fixed to the element layer, the resin layer and the metal layer are irradiated with light through the light-transmitting substrate, the light-transmitting substrate is separated, and a bottom surface of the metal layer is made bare.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: August 31, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideaki Kuwabara, Hiroki Adachi, Satoru Idojiri
  • Patent number: 11107672
    Abstract: In a method of cleaning a substrate, a solution including a size-modification material is applied on a substrate, on which particles to be removed are disposed. Size-modified particles having larger size than the particles are generated, from the particles and the size-modification material. The size-modified particles are removed from the substrate.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: August 31, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Chung-Chieh Lee
  • Patent number: 11084127
    Abstract: A laser lift-off method is disclosed. The laser lift-off method includes: controlling a laser beam to penetrate a substrate along a first irradiation direction, so as to scan an interface between a material layer and the substrate stacked on each other, wherein there is at least one particle on a side of the substrate away from the material layer, and a region of the interface not irradiated by the laser beam along the first irradiation direction is an occluded region; controlling another laser beam to penetrate the substrate along a second irradiation direction, so as to scan the interface between the material layer and the substrate, so that at least a part of the occluded region is irradiated by the another laser beam along the second irradiation direction; and separating the material layer from the substrate.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: August 10, 2021
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Ting Wang, Zhiliang Jiang, Zhenli Zhou
  • Patent number: 11081521
    Abstract: A method for manufacturing a plurality of crystalline semiconductor islands having different lattice parameters includes providing a relaxation substrate comprising a support and a flow layer on the support that includes first and second groups of blocks having different viscosities at a relaxation temperature. The relaxation substrate also comprises a plurality of strained crystalline semiconductor islands on the flow layer, the islands of a first group being located on the first group of blocks and islands of a second group being located on the second group of blocks. The relaxation substrate is then heat treated at a relaxation temperature higher than or equal to the glass transition temperature of at least one block of the flow layer to cause differentiated lateral expansion of the first and second groups of islands such that the first and second groups of relaxed islands then have different lattice parameters.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: August 3, 2021
    Assignee: Soitec
    Inventor: Jean-Marc Bethoux
  • Patent number: 11081382
    Abstract: A method for processing a substrate assembly with a semiconductor device layer includes: arranging an auxiliary carrier at the substrate assembly such that a connection surface of the auxiliary carrier and a first surface of the substrate assembly directly adjoin each other; fixedly attaching the auxiliary carrier to the substrate assembly by melting a carrier portion of the auxiliary carrier and a substrate portion of the substrate assembly that directly adjoins the carrier portion such that the auxiliary carrier and the substrate assembly locally fuse only in fused portions of the auxiliary carrier and the substrate assembly, wherein the fused portions are laterally separated from each other by at least one unfused portion; and processing the semiconductor device layer of the substrate assembly with the auxiliary carrier fixedly attached to the substrate assembly.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: August 3, 2021
    Assignee: Infineon Technologies AG
    Inventors: Francisco Javier Santos Rodriguez, Peter Irsigler
  • Patent number: 11069574
    Abstract: A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of cutting the wafer by using a cutting apparatus to thereby divide the wafer into individual device chips, and a pickup step of applying an ultrasonic wave to the polyester sheet, pushing up each device chip through the polyester sheet, and then picking up each device chip from the polyester sheet.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: July 20, 2021
    Assignee: DISCO CORPORATION
    Inventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
  • Patent number: 11069672
    Abstract: A laminated element manufacturing method includes a first forming step of forming a first gettering region for each of functional elements by irradiating a semiconductor substrate of a first wafer with a laser light, a first grindsing step of grinding the semiconductor substrate of the first wafer and removing a portion of the first gettering region, a bonding step of bonding a circuit layer of a second wafer to the semiconductor substrate of the first wafer, a second forming step of forming a second gettering region for each of the functional elements by irradiating the semiconductor substrate of the second wafer with a laser light, and a second grinding step of grinding the semiconductor substrate of the second wafer and removing a portion of the second gettering region.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: July 20, 2021
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Takeshi Sakamoto, Ryuji Sugiura, Yuta Kondoh, Naoki Uchiyama
  • Patent number: 11056374
    Abstract: A protective member forming method includes forming a water film on a flat holding surface of a support base, placing a wafer on the water film formed on the holding surface and next freezing the water film in a condition where the wafer floats on an upper surface of the water film owing to the surface tension of the water film, thereby forming an ice layer and fixing the wafer on the ice layer, supplying a liquid resin curable by the application of ultraviolet light to the upper surface of the wafer, opposing a transparent sheet to the wafer with the liquid resin interposed therebetween, and applying ultraviolet light to the liquid resin, thereby curing the liquid resin to form a protective member on a whole of the upper surface of the wafer.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: July 6, 2021
    Assignee: DISCO CORPORATION
    Inventor: Kazuma Sekiya
  • Patent number: 11049772
    Abstract: A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side or a front side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form modified layers in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of picking up each device chip from the polyester sheet.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: June 29, 2021
    Assignee: DISCO CORPORATION
    Inventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
  • Patent number: 11049757
    Abstract: A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form division grooves in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of applying an ultrasonic wave to the polyester sheet in each region of the polyester sheet corresponding to each device chip, pushing up each device chip from the polyester sheet side to pick up each device chip from the polyester sheet.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: June 29, 2021
    Assignee: DISCO CORPORATION
    Inventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
  • Patent number: 11021336
    Abstract: A sheet transfer apparatus and a method for transferring a sheet using a sheet transfer apparatus are provided. A sheet transfer apparatus includes: a table on which two or more sheets, which are continuously laminated, are configured to be seated; a sheet adsorbing part on the table to adsorb a first sheet, which is at an uppermost portion, of the two or more laminated sheets at a pressure; and an air discharge part on the table and adjacent to the sheet adsorbing part, and the air discharge part is configured to discharge air to a surface of the first sheet adsorbed to the sheet adsorbing part.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: June 1, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Gyuwon Park, Hoeoun Kim, Jungsoo Ok, Pilseon Ji
  • Patent number: 11018059
    Abstract: An SiC substrate processing method for producing an SiC substrate from an SiC ingot. The SiC substrate processing method includes a separation layer forming step of setting a focal point of a laser beam having a transmission wavelength to SiC inside the SiC ingot at a predetermined depth from the upper surface of the SiC ingot and next applying the laser beam LB to the SiC ingot to thereby form a separation layer for separating the SiC substrate from the SiC ingot, a substrate attaching step of attaching a substrate to the upper surface of the SiC ingot, and a separating step of applying an external force to the separation layer to thereby separate the SiC substrate with the substrate from the SiC ingot along the separation layer.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: May 25, 2021
    Assignee: DISCO CORPORATION
    Inventor: Kazuma Sekiya
  • Patent number: 11018058
    Abstract: A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form division grooves in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of cooling the polyester sheet in each region of the polyester sheet corresponding to each device chip, pushing up each device chip from the polyester sheet side to pick up each device chip from the polyester sheet.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: May 25, 2021
    Assignee: DISCO CORPORATION
    Inventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae