Subsequent Separation Into Plural Bodies (e.g., Delaminating, Dicing, Etc.) Patents (Class 438/458)
  • Patent number: 10770655
    Abstract: An integrated fan-out package including an integrated circuit, a plurality of memory devices, an insulating encapsulation, and a redistribution circuit structure is provided. The memory devices are electrically connected to the integrated circuit. The integrated circuit and the memory devices are stacked, and the memory devices are embedded in the insulating encapsulation. The redistribution circuit structure is disposed on the insulating encapsulation, and the redistribution circuit structure is electrically connected to the integrated circuit and the memory devices. Furthermore, methods for fabricating the integrated fan-out package are also provided.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: September 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee
  • Patent number: 10770289
    Abstract: A graphene-based layer transfer (GBLT) technique is disclosed. In this approach, a device layer including a III-V semiconductor, Si, Ge, III-N semiconductor, SiC, SiGe, or II-VI semiconductor is fabricated on a graphene layer, which in turn is disposed on a substrate. The graphene layer or the substrate can be lattice-matched with the device layer to reduce defect in the device layer. The fabricated device layer is then removed from the substrate via, for example, a stressor attached to the device layer. In GBLT, the graphene layer serves as a reusable and universal platform for growing device layers and also serves a release layer that allows fast, precise, and repeatable release at the graphene surface.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: September 8, 2020
    Assignee: Massachusetts Institute of Technology
    Inventor: Jeehwan Kim
  • Patent number: 10727299
    Abstract: A lateral bipolar junction transistor (LBJT) device that may include a dielectric stack including a pedestal of a base region passivating dielectric and a nucleation dielectric layer; and a base region composed of a germanium containing material or a type III-V semiconductor material in contact with the pedestal of the base region passivating dielectric. An emitter region and collector region may be present on opposing sides of the base region contacting a sidewall of the pedestal of the base region passivating dielectric and an upper surface of the nucleation dielectric layer.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: July 28, 2020
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Kevin K. Chan, Pouya Hashemi, Tak H. Ning, Alexander Reznicek
  • Patent number: 10727127
    Abstract: A method of processing a substrate, having a first surface with at least one division line formed thereon and a second surface opposite the first surface, includes applying a pulsed laser beam to the substrate from the side of the first surface, at least in a plurality of positions along the at least one division line, so as to form a plurality of modified regions in the substrate, each modified region extending at least from the first surface towards the second surface. Each modified region is formed by melting substrate material by means of the pulsed laser beam and allowing the molten substrate material to resolidify. The method further comprises removing substrate material along the at least one division line where the plurality of modified regions has been formed.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: July 28, 2020
    Assignee: DISCO CORPORATION
    Inventors: Hiroshi Morikazu, Karl Heinz Priewasser, Nao Hattori
  • Patent number: 10700012
    Abstract: A method of dicing a semiconductor wafer may include forming a porous silicon layer along an outline of dies singulated from the semiconductor wafer. The method may include sealing an active surface of the semiconductor wafer, including the porous silicon layer. The method may further include back grinding a rear surface of the semiconductor wafer to expose the porous silicon layer along the outline of the dies. The method also includes etching the semiconductor wafer to release the dies.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: June 30, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Stephen Alan Fanelli, Richard Hammond
  • Patent number: 10676386
    Abstract: The present invention relates to a method for separating solid-body slices (1) from a donor substrate (2). The method comprises the steps of: producing modifications (10) within the donor substrate (2) by means of laser beams (12), wherein a detachment region is predefined by the modifications (10), along which detachment region the solid-body layer (1) is separated from the donor substrate (2), and removing material from the donor substrate (2), starting from a surface (4) extending in the peripheral direction of the donor substrate (2), in the direction of the centre (Z) of the donor substrate (2), in particular in order to produce a peripheral indentation (6).
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: June 9, 2020
    Assignee: Siltectra GmbH
    Inventors: Marko Swoboda, Christian Beyer, Franz Schilling, Jan Richter
  • Patent number: 10658240
    Abstract: In a described example, a method includes: forming stress induced dislocations along scribe lanes between semiconductor dies on a semiconductor wafer using a laser; mounting a first side of the semiconductor wafer on the first side of a first dicing tape; removing a backgrinding tape from the semiconductor wafer; attaching a second dicing tape to a second side of the semiconductor wafer opposite the first side, the second dicing tape adhering to portions of the first dicing tape that are spaced from the semiconductor wafer, forming a dual taped wafer dicing assembly; separating the semiconductor dies by stretching the first dicing tape and stretching the second dicing tape; removing the second dicing tape from the semiconductor dies; and removing the semiconductor dies from the first dicing tape.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: May 19, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Shoichi Iriguchi, Hiroyuki Sada, Genki Yano
  • Patent number: 10658226
    Abstract: A method for preparing an SOI wafer by using rapid thermal processing includes: taking a silicon wafer as a raw material, sequentially performing process steps of oxidation, H+ implantation and bonding to obtain a bonded wafer with an H+ implantation layer; and then splitting the bonded wafer by using rapid thermal processing and microwaves to obtain a required SOI wafer. In the present invention, an SOI film after wafer splitting has better thickness uniformity and lower roughness. The present invention may improve lattice damage after implantation and reduce SOI surface defects after wafer splitting and thus improve the SOI surface quality. The present invention is high in wafer-splitting speed and thus reduces silicon wafer contamination. The present invention has high efficiency and an excellent comprehensive technical effect.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: May 19, 2020
    Assignee: Shenyang Silicon Technology Co., Ltd.
    Inventor: Jie Li
  • Patent number: 10641962
    Abstract: A mirror and method of fabricating the mirror, the method comprising: providing a silicon-on-insulator substrate, the substrate comprising: a silicon support layer; a buried oxide (BOX) layer on top of the silicon support layer; and a silicon device layer on top of the BOX layer; creating a via in the silicon device layer, the via extending to the BOX layer; etching away a portion of the BOX layer starting at the via and extending laterally away from the via in a first direction to create a channel between the silicon device layer and silicon support layer; applying an anisotropic etch via the channel to regions of the silicon device layer and silicon support layer adjacent to the channel; the anisotropic etch following an orientation plane of the silicon device layer and silicon support layer to create a cavity underneath an overhanging portion of the silicon device layer; the overhanging portion defining a planar underside surface for vertically coupling light into and out of the silicon device layer; and a
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: May 5, 2020
    Assignee: Rockley Photonics Limited
    Inventors: Henri Nykänen, John Paul Drake, Evie Kho, Damiana Lerose, Sanna Leena Mäkelä, Amit Singh Nagra
  • Patent number: 10643836
    Abstract: A method is disclosed that includes operations as follows. With an ion-implanted layer which is disposed between an epitaxial layer and a first semiconductor substrate, the epitaxial layer is bonded directly to a second semiconductor substrate. The ion-implanted layer is split to separate the first semiconductor substrate from the epitaxial layer completely.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: May 5, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jing-Cheng Lin
  • Patent number: 10644193
    Abstract: A method of manufacturing a light-emitting element includes: providing a wafer including: a substrate, and a semiconductor structure; forming a plurality of modified regions inside the substrate of the wafer by irradiating the substrate with a laser beam; and separating the wafer into a plurality of light-emitting elements after said irradiating the substrate with the laser beam. Said forming the plurality of modified regions includes: scanning the laser beam along a plurality of first lines, the plurality of first lines extending in a first direction and being arranged in a second direction, the first direction being parallel to the first surface, the second direction intersecting the first direction and being parallel to the first surface, and scanning the laser beam along a plurality of second lines, the plurality of second lines extending in the second direction and being arranged in the first direction.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: May 5, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Kazuki Yamaguchi, Haruki Takeda, Yoshitaka Sumitomo
  • Patent number: 10625257
    Abstract: Techniques for use of wafer bonding techniques for sealing of microfluidic chips are provided. In one aspect, a wafer bonding sealing method includes the steps of: forming a first oxide layer coating surfaces of a first wafer, the first wafer having at least one fluidic chip; forming a second oxide layer on a second wafer; and bonding the first wafer to the second wafer via an oxide-to-oxide bond between the first oxide layer and the second oxide layer to form a bonded wafer pair, wherein the second oxide layer seals the at least one fluidic chip on the first wafer. The second wafer can be at least partially removed after performing the bonding, and fluidic ports may be formed in the second oxide layer. A fluidic chip device is also provided.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: April 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Joshua T. Smith, Cornelia K. Tsang, Chao Wang, Benjamin H. Wunsch
  • Patent number: 10615139
    Abstract: A wafer-to-wafer semiconductor device includes a first wafer substrate having a first bonding layer formed on a first bulk substrate layer. A second wafer substrate includes a second bonding layer formed on a second bulk substrate layer. The second bonding layer is bonded to the first bonding layer to define a bonding interface. At least one of the first wafer substrate and the second wafer substrate includes a crack-arresting film layer configured to increase a bonding energy of the bonding interface.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: April 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wei Lin, Leathen Shi, Spyridon Skordas, Kevin R. Winstel
  • Patent number: 10600677
    Abstract: A method for manufacturing a bonded SOI wafer including a step of performing a heat treatment to each bonded SOI wafer having an oxide film on a back surface thereof in an argon atmosphere to flatten a front surface of an SOI layer, wherein, at the time of performing the heat treatment in the argon atmosphere in a batch processing heat treatment furnace, a silicon wafer is arranged as a dummy wafer between the adjacent bonded SOI wafers housed in the batch processing heat treatment furnace to perform the heat treatment. Consequently, there is the method for manufacturing an SOI wafer which enables suppressing an increase in LPDs at the step of performing the heat treatment to a bonded SOI wafer having an oxide film on a back surface thereof in an argon atmosphere in a batch processing heat treatment furnace to flatten a front surface of an SOI layer.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: March 24, 2020
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Toru Ishizuka, Setsuya Hama
  • Patent number: 10593843
    Abstract: A method of manufacturing an optical component for an optical semiconductor includes: providing a joined body including: a first member having light transmissivity and containing at least one element selected from the group consisting of oxygen, fluorine, and nitrogen, and a second member, wherein the first member and the second member are joined together via a metal joining member made by directly bonding a first metal film formed on the first member and a second metal film formed on the second member; and irradiating the joining member with a laser beam or a microwave.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: March 17, 2020
    Assignee: NICHIA CORPORATION
    Inventor: Masatsugu Ichikawa
  • Patent number: 10586505
    Abstract: A transistor whose channel region includes an oxide semiconductor is used as a pull down transistor. The band gap of the oxide semiconductor is 2.0 eV or more, preferably 2.5 eV or more, more preferably 3.0 eV or more. Thus, hot carrier degradation in the transistor can be suppressed. Accordingly, the circuit size of the semiconductor device including the pull down transistor can be made small. Further, a gate of a pull up transistor is made to be in a floating state by switching of on/off of the transistor whose channel region includes an oxide semiconductor. Note that when the oxide semiconductor is highly purified, the off-state current of the transistor can be 1 aA/?m (1×10?18 A/?m) or less. Therefore, the drive capability of the semiconductor device can be improved.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: March 10, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsushi Umezaki, Hajime Kimura
  • Patent number: 10586726
    Abstract: Various embodiments process semiconductor devices. In one embodiment, a release layer is applied to a handler. The release layer comprises at least one additive that adjusts a frequency of electro-magnetic radiation absorption property of the release layer. The additive comprises, for example, a 355 nm chemical absorber and/or chemical absorber for one of more wavelengths in a range comprising 600 nm to 740 nm. The at least one singulated semiconductor device is bonded to the handler. The at least one singulated semiconductor device is packaged while it is bonded to the handler. The release layer is ablated by irradiating the release layer through the handler with a laser. The the at least one singulated semiconductor device is removed from the transparent handler after the release layer has been ablated.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Paul S. Andry, Bing Dang, Jeffrey Donald Gelorme, Li-Wen Hung, John U. Knickerbocker, Cornelia Tsang Yang
  • Patent number: 10564356
    Abstract: A heterogeneous semiconductor structure, including a first integrated circuit and a second integrated circuit, the second integrated circuit being a photonic integrated circuit. The heterogeneous semiconductor structure may be fabricated by bonding a multi-layer source die, in a flip-chip manner, to the first integrated circuit, removing the substrate of the source die, and fabricating one or more components on the source die, using etch and/or deposition processes, to form the second integrated circuit. The second integrated circuit may include components fabricated from cubic phase gallium nitride compounds, and configured to operate at wavelengths shorter than 450 nm.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: February 18, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Daniel N. Carothers
  • Patent number: 10535843
    Abstract: A method includes steps of (a) forming a substrate layer 10 above a support substrate 8 which is transparent, and then a thin-film element above the substrate layer 10; and (b) emitting laser beams La and Lb to a face of the support substrate 8 opposite to another face of the support substrate to which the substrate layer 10 and the thin-film element are formed, and delaminating the substrate layer 10 and the thin-film element from the support substrate 8. In step (b), the laser beams La and Lb are emitted from different directions.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: January 14, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tetsunori Tanaka, Wataru Nakamura, Shoji Okazaki, Masaki Fujiwara
  • Patent number: 10516001
    Abstract: According to a flexible OLED device production method of the present disclosure, after an intermediate region (30i) and flexible substrate regions (30d) of a plastic film (30) of a multilayer stack (100) are divided from one another, the interface between the flexible substrate regions (30d) and a glass base (10) is irradiated with laser light. The multilayer stack (100) is separated into a first portion (110) and a second portion (120) while the multilayer stack (100) is in contact with a stage (210). The first portion (110) includes a plurality of OLED devices (1000) which are in contact with the stage (210). The OLED devices (1000) include a plurality of functional layer regions (20) and the flexible substrate regions (30d). The second portion (120) includes the glass base (10) and the intermediate region (30i).
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: December 24, 2019
    Assignee: Sakai Display Products Corporation
    Inventors: Kohichi Tanaka, Katsuhiko Kishimoto
  • Patent number: 10490440
    Abstract: Method for manufacturing bonded SOI wafer by bonding bond wafer and base wafer each composed of silicon single crystal with insulator film being interposed therebetween, including steps of: depositing polycrystalline silicon layer on bonding surface side of base wafer; polishing surface of polycrystalline silicon layer to obtain polished surface; forming thermal oxide film on polished surface; forming insulator film on bonding surface of bond wafer; bonding step of bonding bond and base wafers by bringing insulator and oxide films into close contact with each other; and thinning bonded bond wafer to form SOI layer, wherein silicon single crystal wafer having resistivity of 100 ?·cm or more is used as base wafer, thermal oxide film formed on polished surface has thickness of 15 nm or more with RMS of 0.6 nm or less, and any heat treatment after bonding step is performed with maximum treatment temperature of 1150° C. or less.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: November 26, 2019
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Norihiro Kobayashi, Hiroji Aga
  • Patent number: 10475955
    Abstract: A method for producing a plurality of components and a component are disclosed. In an embodiment the method includes providing a carrier composite comprising a base body and a planar connecting surface, providing a wafer composite comprising a semiconductor body composite and a planar contact surface, connecting the wafer composite to the carrier composite thereby forming a joint composite so that the planar contact surface and the planar connecting surface are joined forming a joint boundary surface. The method further includes reducing inner mechanical stress in the joint composite so that a material of the carrier composite is removed in places, wherein the joint composite is thermally treated in order to form a permanent mechanically-stable connection between the wafer composite and the carrier composite, and wherein reducing inner stress is effected prior to the thermal treatment.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: November 12, 2019
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Sophia Huppmann, Simeon Katz, Marcus Zenger, Dominik Scholz
  • Patent number: 10475694
    Abstract: A method is provided for preparing a high resistivity silicon handle substrate for use in semiconductor-on-insulator structure. The handle substrate is prepared to comprise thermally stable charge carrier traps in the region of the substrate that will be at or near the buried oxide layer (BOX) of the final semiconductor-on-insulator structure. The handle substrate comprising the stable carrier traps is manufactured by hydrogen ions implantation occurring using at least two different energies, followed by a 2-step thermal treatment. The thermally stable defect structures prepared thereby is stable to anneal at temperatures of at least 1180° C. The defect structure comprises 3-dimensional network of nano-cavities interconnected by dislocations. This wafer can be used as a handle wafer for fabricating silicon-on-insulator (SOI) wafers and further fabricating radio frequency (RF) semiconductor devices.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: November 12, 2019
    Assignee: GlobalWafers Co., Ltd.
    Inventor: Alex Usenko
  • Patent number: 10439028
    Abstract: A semiconductor film, a sheet like object, and a semiconductor device are provided that have inhibited semiconductor properties, particularly leakage current, and excellent withstand voltage and heat dissipation. A crystalline semiconductor film or a sheet like object includes a corundum structured oxide semiconductor as a major component, wherein the film has a film thickness of 1 ?m or more. Particularly, the semiconductor film or the object includes a semiconductor component of oxide of one or more selected from gallium, indium, and aluminum as a major component. A semiconductor device has a semiconductor structure including the semiconductor film or the object.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: October 8, 2019
    Assignee: FLOSFIA, INC.
    Inventors: Toshimi Hitora, Masaya Oda, Akio Takatsuka
  • Patent number: 10427898
    Abstract: A sheet transfer apparatus and a method for transferring a sheet using a sheet transfer apparatus are provided. A sheet transfer apparatus includes: a table on which two or more sheets, which are continuously laminated, are configured to be seated; a sheet adsorbing part on the table to adsorb a first sheet, which is at an uppermost portion, of the two or more laminated sheets at a pressure; and an air discharge part on the table and adjacent to the sheet adsorbing part, and the air discharge part is configured to discharge air to a surface of the first sheet adsorbed to the sheet adsorbing part.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: October 1, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Gyuwon Park, Hoeoun Kim, Jungsoo Ok, Pilseon Ji
  • Patent number: 10407598
    Abstract: In a method in which a workpiece, while being temporarily fixed on a support via a temporary fixing material, is processed and/or transported and thereafter the support and the workpiece are separated from each other by an irradiation separation method, a technique is shown which prevents the photo-degradation of the workpiece. A workpiece treating method includes a step of forming a stack including a support, a temporary fixing material and a workpiece wherein the temporary fixing material includes a layer (I) that contains a polymer (A) including a structural unit (A1); a step of processing the workpiece and/or transporting the stack; a step of applying light to the layer (I) through the support; and a step of separating the support and the workpiece from each other.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: September 10, 2019
    Assignee: JSR CORPORATION
    Inventors: Takashi Mori, Hikaru Mizuno
  • Patent number: 10403537
    Abstract: Embodiments relate to transferring dies or other electronic components from a carrier substrate to a target substrate of a device as part of chip assembly for the device. Bonding material is applied to selected dies on a carrier substrate by direct boning, or to corresponding die transfer locations on a target substrate. The carrier substrate is then brought into contact with the target substrate to transfer each of the selected dies to the carrier substrate. Dies can also be directly bonded to the target substrate even in the presence of other die in situ (e.g., from a previous bonding cycle), hence, enables more than one direct bond cycle to be carried out for a target substrate. As such, multi-color (RGB) display elements can be assembled in stages (e.g., separate bonding cycles) in a flexible manner to provide redundancy or to replace inoperative LED dies.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: September 3, 2019
    Assignee: Facebook Technologies, LLC
    Inventors: William Padraic Henry, Patrick Joseph Hughes, Vincent Brennan
  • Patent number: 10403544
    Abstract: Implementations of a method of singulating a plurality of die may include: providing a semiconductor wafer including a plurality of die located on a first side of the semiconductor wafer where the plurality of die include a desired thickness. The method may include etching a plurality of trenches into the semiconductor wafer only from the first side of the semiconductor wafer where the plurality of trenches is located adjacent to a perimeter of the plurality of die. A depth of the plurality of trenches may be greater than the desired thickness of the plurality of die. The method may also include mounting the first side of the semiconductor wafer to a backgrinding tape. The method may also include thinning a second side of the semiconductor wafer to a predetermined distance to the depth of the plurality of trenches to singulate the plurality of die.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: September 3, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael John Seddon
  • Patent number: 10348943
    Abstract: An electronic device may have components such as a display, a camera, a button, and other electrical components. A transparent crystalline member such as a layer of aluminum oxide, zirconium oxide, or other crystalline dielectric structure may overlap an electrical component and may serve as a display cover layer, button cover member, or window member. An annealed adhesion layer such as an annealed inorganic layer may be formed on a crystalline dielectric member. The annealed adhesion layer may help adhere an oleophobic coating to the transparent crystalline member.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: July 9, 2019
    Assignee: Apple Inc.
    Inventors: Matthew S. Rogers, Naoto Matsuyuki, Que Anh S. Nguyen
  • Patent number: 10340319
    Abstract: It is an object to provide a flexible light-emitting device with long lifetime in a simple way and to provide an inexpensive electronic device with long lifetime using the flexible light-emitting device. A flexible light-emitting device is provided, which includes a substrate having flexibility and a light-transmitting property with respect to visible light; a first adhesive layer over the substrate; an insulating film containing nitrogen and silicon over the first adhesive layer; a light-emitting element including a first electrode, a second electrode facing the first electrode, and an EL layer between the first electrode and the second electrode; a second adhesive layer over the second electrode; and a metal substrate over the second adhesive layer, wherein the thickness of the metal substrate is 10 ?m to 200 ?m inclusive. Further, an electronic device using the flexible light-emitting device is provided.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: July 2, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kaoru Hatano, Satoshi Seo, Takaaki Nagata, Tatsuya Okano
  • Patent number: 10340389
    Abstract: The present disclosure discloses in embodiments a thin film transistor and a manufacturing method thereof, an array substrate. The thin film transistor comprises: a base substrate, an active layer, a source, a gate, and a drain. Two ends of the active layer are connected to the source and the drain, respectively. The gate comprises a top gate and a bottom gate arranged opposite to each other in a direction perpendicular to the base substrate, the top gate comprising a top gate top portion and a top gate side portion connected to the top gate top portion, the top gate side portion extending from the top gate top portion towards the base substrate. The active layer is sandwiched between the top gate top portion and the bottom gate. A sidewall of the active layer is at least partially surrounded by the top gate side portion.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: July 2, 2019
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Xiangyong Kong, Xiaming Zhu, Xiaodi Liu
  • Patent number: 10319940
    Abstract: An organic EL display device includes a rectangular first substrate, an organic EL diode unit formed on the first substrate, a rectangular second substrate formed on the organic EL diode unit, a frame-shaped adhesive section configured to attach the first substrate to the second substrate to surround the organic EL diode unit, an extraction interconnection group constituted by a plurality of extraction interconnections extracted from the organic EL diode unit, and a dummy interconnection group formed at an adhesive region at which the adhesive section of the first substrate is attached and constituted by a plurality of dummy interconnections that are separated from each other, wherein the extraction interconnection and the dummy interconnection cross the adhesive section in the same direction.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: June 11, 2019
    Assignee: FUTABA CORPORATION
    Inventors: Shinji Ide, Ikuo Ohmori, Nobuko Hayakawa
  • Patent number: 10318880
    Abstract: Materials, devices, methods of use and fabrication thereof are disclosed. The materials are particularly well suited for application in superconducting devices and quantum computing, due to ability to avoid undesirable effects from inherent noise and decoherence. The materials are formed from select isotopes having zero nuclear spin into a single crystal-phase film or layer of thickness depending on the desired application of the resulting device. The film/layer may be suspended or disposed on a substrate. The isotopes may be enriched from naturally-occurring sources of isotopically mixed elemental material(s). The single crystal is preferably devoid of structural defects such as grain boundaries, inclusions, impurities and lattice vacancies. Device configurations may be formed from the layer according to a predetermined pattern using lithographic and/or milling techniques.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: June 11, 2019
    Assignee: Lawrence Livermore National Security, LLC
    Inventor: Sergey Pereverzev
  • Patent number: 10290533
    Abstract: A single crystal semiconductor handle substrate for use in the manufacture of semiconductor-on-insulator (e.g., silicon-on-insulator (SOI)) structure is etched to form a porous layer in the front surface region of the wafer. The etched region is oxidized and then filled with a semiconductor material, which may be polycrystalline or amorphous. The surface is polished to render it bondable to a semiconductor donor substrate. Layer transfer is performed over the polished surface thus creating semiconductor-on-insulator (e.g., silicon-on-insulator (SOI)) structure having 4 layers: the handle substrate, the composite layer comprising filled pores, a dielectric layer (e.g., buried oxide), and a device layer. The structure can be used as initial substrate in fabricating radiofrequency chips. The resulting chips have suppressed parasitic effects, particularly, no induced conductive channel below the buried oxide.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: May 14, 2019
    Assignee: GlobalWafers Co., Ltd.
    Inventor: Alex Usenko
  • Patent number: 10259206
    Abstract: Epitaxial lift off systems and methods are presented. In one embodiment a tape is disposed on the opposite side of the epitaxial material than the substrate is used to hold the epitaxial material during the etching and removal steps of the ELO process. In various embodiments, the apparatus for removing the ELO film from the substrates without damaging the ELO film may include an etchant reservoir, substrate handling and tape handling mechanisms, including mechanisms to manipulate (e.g., cause tension, peel, widen the etch gap, etc.) the lift off component during the lift off process.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: April 16, 2019
    Assignee: ALTA DEVICES, INC.
    Inventors: Brian Brown, Brian Burrows, David Berkstressor, Gang He, Thomas J Gmitter
  • Patent number: 10236210
    Abstract: The method is carried out of a first substrate having a first layer made of a first material with a second substrate having a second layer made of a second material, the first material and the second material being of different natures and selected from alloys of elements of columns III and V, the method having the steps of: a) providing the first substrate and the second substrate, b) bringing the first substrate into contact with the second substrate so as to form a bonding interface between the first layer and the second layer, c) performing a first heat treatment at a first predefined temperature, d) thinning one of the substrates, e) depositing, at a temperature less than or equal to the first predefined temperature, a barrier layer, on the thinned substrate, and f) performing a second heat treatment at a second predefined temperature, greater than the first predefined temperature.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: March 19, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Aurélie Tauzin, Bruno Imbert
  • Patent number: 10228575
    Abstract: The present application discloses a separating apparatus for separating an object to be separated including two plate-shaped structures stacked on each other. The separating apparatus includes: an electrical signal generating unit and an acoustic wave signal output unit connected to each other, the electrical signal generating unit is configured to generate a target electrical signal; and the acoustic wave signal output unit is configured to convert the target electrical signal into a target acoustic wave, and output the target acoustic wave to the object to be separated, wherein a frequency of the target acoustic wave is different from a natural frequency of any one of the two plate-shaped structures.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: March 12, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Qian Jia
  • Patent number: 10211178
    Abstract: A wafer-to-wafer semiconductor device includes a first wafer substrate having a first bonding layer formed on a first bulk substrate layer. A second wafer substrate includes a second bonding layer formed on a second bulk substrate layer. The second bonding layer is bonded to the first bonding layer to define a bonding interface. At least one of the first wafer substrate and the second wafer substrate includes a crack-arresting film layer configured to increase a bonding energy of the bonding interface.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: February 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wei Lin, Leathen Shi, Spyridon Skordas, Kevin R. Winstel
  • Patent number: 10192778
    Abstract: A method is provided for preparing a semiconductor-on-insulator structure comprising a sacrificial layer.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: January 29, 2019
    Assignee: GlobalWafers Co., Ltd.
    Inventor: Sasha Joseph Kweskin
  • Patent number: 10164141
    Abstract: A semiconductor device includes a carrier wafer, a device layer, a first semiconductor layer and a second semiconductor layer. The device layer is disposed on the carrier wafer. The first semiconductor layer is disposed on the device layer, and has a first side face and a second side face opposite to the first side face, in which the first side face is adjacent to the device layer. The second semiconductor layer is disposed on the first semiconductor layer, and has a third side face and a fourth side face opposite to the third side face, in which the fourth side face of the second semiconductor layer is adjacent to the second side face of the first semiconductor layer, and the second semiconductor layer is implanted and annealed.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Nan Tu, Yu-Lung Yeh, Hsing-Chih Lin, Chien-Chang Huang
  • Patent number: 10163682
    Abstract: The present disclosure relates to a process for the manufacture of a high resistivity semiconductor substrate, comprising the following stages: providing a first substrate with an in-depth weakened layer; providing a second substrate with a layer of an oxide at the surface; attaching the first substrate to the second substrate so as to form a compound substrate comprising a layer of buried oxide; and cleaving the compound substrate at the level of the weakened layer. The process additionally comprises at least one stage of stabilization, in particular, a stabilization heat treatment, of the second substrate with the layer of oxide before the stage of cleaving at the level of the weakened layer.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: December 25, 2018
    Assignee: Soitec
    Inventors: Cédric Malaquin, Ludovic Ecarnot, Damien Parissi
  • Patent number: 10156765
    Abstract: An electrophoretic display apparatus, adapted to be electrically connected with an external circuit, includes a driving array substrate, an electrophoretic display layer, and a first optical adhesive layer. The electrophoretic display layer includes a flexible substrate and a display medium layer. The flexible substrate has a configuration area and a bonding area. The external circuit is disposed between the flexible substrate and the driving array substrate. The external circuit is located in the bonding area and extends outside the driving array substrate. The display medium layer is disposed between the flexible substrate and the driving array substrate and located in the configuration area. The first optical adhesive layer is disposed between the display medium layer and the driving array substrate. A thickness of the external circuit is smaller than a sum of a thickness of the display medium layer and a thickness of the first optical adhesive layer.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: December 18, 2018
    Assignee: E Ink Holdings Inc.
    Inventor: Chi-Ming Wu
  • Patent number: 10153457
    Abstract: A flexible display device comprises a flexible substrate including a display area and a non-display area; a display layer in the display area on a first surface of the flexible substrate; a polarizing plate on the display layer; and a cover coat in the non-display area on the first surface of the flexible substrate, the cover coat including a first end portion overlapping with the polarizing plate. At least a portion of the non-display area of the flexible substrate and the cover coat are bendable in a bending direction.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: December 11, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: HaeJoon Son, SieHyug Choi, JuhnSuk Yoo, MoonGoo Kim, Jehong Park, Chiwoong Kim
  • Patent number: 10083849
    Abstract: A method of processing a wafer includes placing a supporting substrate in confronting relation to a face side of the wafer and integrally bonding the supporting substrate to the face side of the wafer with a bonding material, grinding a reverse side of the wafer to thin the wafer, cutting the wafer along division lines from the reverse side of the wafer into chips that carry individual devices thereon, placing a protective member on the reverse side of the wafer, applying a laser beam having a wavelength which is able to transmit the supporting substrate in the condition where a focused spot of the laser beam is set in the bonding material, thereby breaking the bonding material, and peeling the supporting substrate off from the devices to separate the chips that carry the individual devices thereon.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: September 25, 2018
    Assignee: Disco Corporation
    Inventor: Hiroshi Morikazu
  • Patent number: 10079179
    Abstract: A wafer is divided into a plurality of individual devices along a plurality of division lines, the wafer being composed of a substrate and a functional layer formed on the upper surface of the substrate through a buffer layer. The functional layer is partitioned by the division lines to define a plurality of separate regions where the devices are formed on the front side of the wafer. At least the functional layer is cut along the division lines. A protective member is provided on the front side of the wafer. The buffer layer is broken by applying a laser beam having a transmission wavelength to the substrate with the focal point of the laser beam set in the buffer layer, thereby breaking the buffer layer. The substrate is peeled from the functional layer, thereby forming the individual devices from the functional layer.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: September 18, 2018
    Assignee: Disco Corporation
    Inventor: Hiroshi Morikazu
  • Patent number: 10070568
    Abstract: Methods and apparatus for use in the manufacture of a display element. Some embodiments include a method for selective pick up of a subset of a plurality of electronic devices adhered to a handle layer. The method comprises modifying a level of adhesion between one or more electronic devices of the plurality of electronic devices adhered to the handle layer, such that the subset of the plurality of electronic devices has a level of adhesion to the handle layer that is less than a force applied by a pick up tool, PUT. This enables selective pick up of the subset of the plurality of electronic devices from the handle layer by the PUT.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: September 4, 2018
    Assignee: Oculus VR, LLC
    Inventors: Allan Pourchet, William Padraic Henry, Patrick Joseph Hughes, Joseph O'Keeffe
  • Patent number: 10060049
    Abstract: A method of making a joint between parts is provided, wherein the surface of at least one of the parts comprises aluminum oxide such as alpha aluminum oxide in the form of sapphire. A layer of aluminum nitride is provided between the surfaces of the parts where these contact. The method comprises the steps of bringing the parts into contact whereby the aluminum nitride layer is sandwiched between the parts and is in contact with the aluminum oxide surface, and performing localized heating of the aluminum nitride. The aluminum nitride is heated to at least the melting temperature of the aluminum nitride aluminum oxide eutectic, such that the aluminum nitride and adjacent aluminum oxide mix and melt to form an aluminum oxy-nitride bond. On cooling, the aluminum oxynitride forms a solid joint between the parts.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: August 28, 2018
    Inventor: Roger Ian Lounsbury
  • Patent number: 10049947
    Abstract: A method of manufacturing a substrate is disclosed. The method comprises: providing a first semiconductor substrate, which includes an at least partially processed CMOS device layer and a layer of first wafer material; bonding a handle substrate to the partially processed CMOS device layer and removing the layer of first wafer material; providing a second semiconductor substrate having a layer of second wafer material which is different to silicon; bonding the first and second semiconductor substrates to form a combined substrate by bonding the layer of second wafer material to the partially processed CMOS device layer; and removing the handle substrate from the combined substrate to expose at least a portion of the partially processed CMOS device layer.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: August 14, 2018
    Assignees: Massachusetts Institute of Technology, Nanyang Technological University
    Inventors: Kwang Hong Lee, Chuan Seng Tan, Eugene A. Fitzgerald, Eng Kian Kenneth Lee
  • Patent number: 10043975
    Abstract: [Problem] To provide a technology that allows a film or glass to be bonded to a transport substrate and to be easily separated during the manufacture of a substrate. [Solution] Provided is a method for manufacturing a substrate having an electronic device formed on a surface, the method comprising a formation step for forming an inorganic material layer on at least one of a bonding surface by which the substrate having an electronic device formed on a surface is to be bonded to a transport substrate, and a bonding surface on the transport substrate for transporting the substrate; a bonding step for pressing the substrate and the transport substrate against each other and bonding the substrate and the transport substrate by the inorganic material layer; and a separation step for separating the substrate and the transport substrate.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: August 7, 2018
    Assignee: LAN TECHNICAL SERVICE CO., LTD.
    Inventors: Tadatomo Suga, Yoshiie Matsumoto
  • Patent number: 10026642
    Abstract: A method is provided for preparing a semiconductor-on-insulator structure comprising a sacrificial layer.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: July 17, 2018
    Assignee: SunEdison Semiconductor Limited (UEN201334164H)
    Inventor: Sasha Joseph Kweskin