Subsequent Separation Into Plural Bodies (e.g., Delaminating, Dicing, Etc.) Patents (Class 438/458)
  • Patent number: 11177434
    Abstract: An integrated fan-out package including an integrated circuit, a plurality of memory devices, an insulating encapsulation, and a redistribution circuit structure is provided. The memory devices are electrically connected to the integrated circuit. The integrated circuit and the memory devices are stacked, and the memory devices are embedded in the insulating encapsulation. The redistribution circuit structure is disposed on the insulating encapsulation, and the redistribution circuit structure is electrically connected to the integrated circuit and the memory devices. Furthermore, methods for fabricating the integrated fan-out package are also provided.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: November 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee
  • Patent number: 11177253
    Abstract: An electronic device includes a MOS transistor with a source and a drain, and a capacitor with a first plate connected directly to the source, and a second plate connected directly to the drain. A method to fabricate an electronic device includes fabricating a MOS transistor on or in a semiconductor structure, and fabricating a capacitor having a first plate connected directly to a source of the MOS transistor, and a second plate connected directly to a drain of the MOS transistor.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: November 16, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Christopher Boguslaw Kocon
  • Patent number: 11168234
    Abstract: The present invention relates to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: November 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: James L. Hedrick, Robert D. Miller, Deborah A. Neumayer, Sampath Purushothaman, Mary E. Rothwell, Willi Volksen, Roy R. Yu
  • Patent number: 11158607
    Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: October 26, 2021
    Assignee: Apple Inc.
    Inventors: Sanjay Dabral, Jun Zhai, Kwan-Yu Lai, Kunzhong Hu, Vidhya Ramachandran
  • Patent number: 11146243
    Abstract: A bulk acoustic wave (BAW) filter for passing through electric signals in a preset frequency range is provided. The BAW filter includes: a diamond substrate; a passivation layer formed on the diamond substrate; a first metal layer formed on the passivation layer; a piezoelectric layer formed on the first metal layer; a second metal layer formed on a piezoelectric layer and a metal pad formed on the first metal layer. The metal pad, first metal layer, piezoelectric layer and second metal layer form an electrical path that allows an electrical signal within a preset frequency range to pass therethrough.
    Type: Grant
    Filed: February 2, 2020
    Date of Patent: October 12, 2021
    Assignee: RFHIC Corporation
    Inventor: Won Sang Lee
  • Patent number: 11107846
    Abstract: A technique is described in which a transistor formed using an oxide semiconductor film, a transistor formed using a polysilicon film, a transistor formed using an amorphous silicon film or the like, a transistor formed using an organic semiconductor film, a light-emitting element, or a passive element is separated from a glass substrate by light or heat. An oxide layer is formed over a light-transmitting substrate, a metal layer is selectively formed over the oxide layer, a resin layer is formed over the metal layer, an element layer is formed over the resin layer, a flexible film is fixed to the element layer, the resin layer and the metal layer are irradiated with light through the light-transmitting substrate, the light-transmitting substrate is separated, and a bottom surface of the metal layer is made bare.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: August 31, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideaki Kuwabara, Hiroki Adachi, Satoru Idojiri
  • Patent number: 11107672
    Abstract: In a method of cleaning a substrate, a solution including a size-modification material is applied on a substrate, on which particles to be removed are disposed. Size-modified particles having larger size than the particles are generated, from the particles and the size-modification material. The size-modified particles are removed from the substrate.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: August 31, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Chung-Chieh Lee
  • Patent number: 11084127
    Abstract: A laser lift-off method is disclosed. The laser lift-off method includes: controlling a laser beam to penetrate a substrate along a first irradiation direction, so as to scan an interface between a material layer and the substrate stacked on each other, wherein there is at least one particle on a side of the substrate away from the material layer, and a region of the interface not irradiated by the laser beam along the first irradiation direction is an occluded region; controlling another laser beam to penetrate the substrate along a second irradiation direction, so as to scan the interface between the material layer and the substrate, so that at least a part of the occluded region is irradiated by the another laser beam along the second irradiation direction; and separating the material layer from the substrate.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: August 10, 2021
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Ting Wang, Zhiliang Jiang, Zhenli Zhou
  • Patent number: 11081521
    Abstract: A method for manufacturing a plurality of crystalline semiconductor islands having different lattice parameters includes providing a relaxation substrate comprising a support and a flow layer on the support that includes first and second groups of blocks having different viscosities at a relaxation temperature. The relaxation substrate also comprises a plurality of strained crystalline semiconductor islands on the flow layer, the islands of a first group being located on the first group of blocks and islands of a second group being located on the second group of blocks. The relaxation substrate is then heat treated at a relaxation temperature higher than or equal to the glass transition temperature of at least one block of the flow layer to cause differentiated lateral expansion of the first and second groups of islands such that the first and second groups of relaxed islands then have different lattice parameters.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: August 3, 2021
    Assignee: Soitec
    Inventor: Jean-Marc Bethoux
  • Patent number: 11081382
    Abstract: A method for processing a substrate assembly with a semiconductor device layer includes: arranging an auxiliary carrier at the substrate assembly such that a connection surface of the auxiliary carrier and a first surface of the substrate assembly directly adjoin each other; fixedly attaching the auxiliary carrier to the substrate assembly by melting a carrier portion of the auxiliary carrier and a substrate portion of the substrate assembly that directly adjoins the carrier portion such that the auxiliary carrier and the substrate assembly locally fuse only in fused portions of the auxiliary carrier and the substrate assembly, wherein the fused portions are laterally separated from each other by at least one unfused portion; and processing the semiconductor device layer of the substrate assembly with the auxiliary carrier fixedly attached to the substrate assembly.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: August 3, 2021
    Assignee: Infineon Technologies AG
    Inventors: Francisco Javier Santos Rodriguez, Peter Irsigler
  • Patent number: 11069574
    Abstract: A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of cutting the wafer by using a cutting apparatus to thereby divide the wafer into individual device chips, and a pickup step of applying an ultrasonic wave to the polyester sheet, pushing up each device chip through the polyester sheet, and then picking up each device chip from the polyester sheet.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: July 20, 2021
    Assignee: DISCO CORPORATION
    Inventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
  • Patent number: 11069672
    Abstract: A laminated element manufacturing method includes a first forming step of forming a first gettering region for each of functional elements by irradiating a semiconductor substrate of a first wafer with a laser light, a first grindsing step of grinding the semiconductor substrate of the first wafer and removing a portion of the first gettering region, a bonding step of bonding a circuit layer of a second wafer to the semiconductor substrate of the first wafer, a second forming step of forming a second gettering region for each of the functional elements by irradiating the semiconductor substrate of the second wafer with a laser light, and a second grinding step of grinding the semiconductor substrate of the second wafer and removing a portion of the second gettering region.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: July 20, 2021
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Takeshi Sakamoto, Ryuji Sugiura, Yuta Kondoh, Naoki Uchiyama
  • Patent number: 11056374
    Abstract: A protective member forming method includes forming a water film on a flat holding surface of a support base, placing a wafer on the water film formed on the holding surface and next freezing the water film in a condition where the wafer floats on an upper surface of the water film owing to the surface tension of the water film, thereby forming an ice layer and fixing the wafer on the ice layer, supplying a liquid resin curable by the application of ultraviolet light to the upper surface of the wafer, opposing a transparent sheet to the wafer with the liquid resin interposed therebetween, and applying ultraviolet light to the liquid resin, thereby curing the liquid resin to form a protective member on a whole of the upper surface of the wafer.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: July 6, 2021
    Assignee: DISCO CORPORATION
    Inventor: Kazuma Sekiya
  • Patent number: 11049757
    Abstract: A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form division grooves in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of applying an ultrasonic wave to the polyester sheet in each region of the polyester sheet corresponding to each device chip, pushing up each device chip from the polyester sheet side to pick up each device chip from the polyester sheet.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: June 29, 2021
    Assignee: DISCO CORPORATION
    Inventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
  • Patent number: 11049772
    Abstract: A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side or a front side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form modified layers in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of picking up each device chip from the polyester sheet.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: June 29, 2021
    Assignee: DISCO CORPORATION
    Inventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
  • Patent number: 11021336
    Abstract: A sheet transfer apparatus and a method for transferring a sheet using a sheet transfer apparatus are provided. A sheet transfer apparatus includes: a table on which two or more sheets, which are continuously laminated, are configured to be seated; a sheet adsorbing part on the table to adsorb a first sheet, which is at an uppermost portion, of the two or more laminated sheets at a pressure; and an air discharge part on the table and adjacent to the sheet adsorbing part, and the air discharge part is configured to discharge air to a surface of the first sheet adsorbed to the sheet adsorbing part.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: June 1, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Gyuwon Park, Hoeoun Kim, Jungsoo Ok, Pilseon Ji
  • Patent number: 11018058
    Abstract: A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form division grooves in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of cooling the polyester sheet in each region of the polyester sheet corresponding to each device chip, pushing up each device chip from the polyester sheet side to pick up each device chip from the polyester sheet.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: May 25, 2021
    Assignee: DISCO CORPORATION
    Inventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
  • Patent number: 11018059
    Abstract: An SiC substrate processing method for producing an SiC substrate from an SiC ingot. The SiC substrate processing method includes a separation layer forming step of setting a focal point of a laser beam having a transmission wavelength to SiC inside the SiC ingot at a predetermined depth from the upper surface of the SiC ingot and next applying the laser beam LB to the SiC ingot to thereby form a separation layer for separating the SiC substrate from the SiC ingot, a substrate attaching step of attaching a substrate to the upper surface of the SiC ingot, and a separating step of applying an external force to the separation layer to thereby separate the SiC substrate with the substrate from the SiC ingot along the separation layer.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: May 25, 2021
    Assignee: DISCO CORPORATION
    Inventor: Kazuma Sekiya
  • Patent number: 11004744
    Abstract: A wafer processing method includes a polyolefin sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyolefin sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyolefin sheet as applying a pressure to the polyolefin sheet to thereby unite the wafer and the ring frame through the polyolefin sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form division grooves in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of applying an ultrasonic wave to the polyolefin sheet in each region of the polyolefin sheet corresponding to each device chip, pushing up each device chip from the polyolefin sheet side to pick up each device chip from the polyolefin sheet.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: May 11, 2021
    Assignee: DISCO CORPORATION
    Inventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
  • Patent number: 10998232
    Abstract: A wafer processing method includes a polyolefin sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyolefin sheet on a back side or a front side of the wafer and on a back side of the ring frame, a uniting step of heating the polyolefin sheet as applying a pressure to the polyolefin sheet to thereby unite the wafer and the ring frame through the polyolefin sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form modified layers in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of picking up each device chip from the polyolefin sheet.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: May 4, 2021
    Assignee: DISCO CORPORATION
    Inventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
  • Patent number: 10991587
    Abstract: A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form division grooves in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of picking up each device chip from the polyester sheet.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: April 27, 2021
    Assignee: DISCO CORPORATION
    Inventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
  • Patent number: 10991624
    Abstract: A wafer processing method includes a polyolefin sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyolefin sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyolefin sheet as applying a pressure to the polyolefin sheet to thereby unite the wafer and the ring frame through the polyolefin sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form division grooves in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of cooling the polyolefin sheet in each region of the polyolefin sheet corresponding to each device chip, pushing up each device chip from the polyolefin sheet side to pick up each device chip from the polyolefin sheet.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: April 27, 2021
    Assignee: DISCO CORPORATION
    Inventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
  • Patent number: 10985066
    Abstract: A wafer processing method includes a polyolefin sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyolefin sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyolefin sheet as applying a pressure to the polyolefin sheet to thereby unite the wafer and the ring frame through the polyolefin sheet by thermocompression bonding, a dividing step of cutting the wafer by using a cutting apparatus to thereby divide the wafer into individual device chips, and a pickup step of applying an ultrasonic wave to the polyolefin sheet, pushing up each device chip through the polyolefin sheet, and then picking up each device chip from the polyolefin sheet.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: April 20, 2021
    Assignee: DISCO CORPORATION
    Inventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
  • Patent number: 10964524
    Abstract: A back surface of a wafer is formed with a ring-shaped projecting portion. The wafer is cut with a blade from a side of a front surface of the wafer in a state where the projecting portion of the wafer with a back surface facing upward is supported.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: March 30, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tsuyoshi Osaga, Yasuo Ata
  • Patent number: 10923630
    Abstract: Disclosed herein are techniques for improving performance of micro light emitting diodes. According to certain embodiments, a semi-polar-oriented light emitting diode (LED) (e.g., grown on (2021) plane or (1122) plane) includes a buried p-GaN layer that is grown before the active region and the n-GaN layer of the LED are grown, such that the polarization-induced (including strain-induced piezoelectric polarization and spontaneous polarization) electrical field and the built-in depletion field in the active region are in opposite directions during normal operations, thereby reducing or minimizing the overall internal electric field that can contribute to Quantum-Confined Stark Effect. The buried p-GaN layer is grown on an n-i-n sacrificial etch junction, which can be laterally wet-etched to separate the semi-polar-oriented LED from the underlying substrate and expose the p-GaN layer for planar or vertical (rather than horizontal or lateral) activation.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: February 16, 2021
    Assignee: FACEBOOK TECHNOLOGIES, LLC
    Inventors: Christopher Pynn, Anneli Munkholm, David Hwang
  • Patent number: 10916416
    Abstract: A semiconductor wafer and a semiconductor wafer fabrication method are provided. The wafer includes a supporting substrate, a semiconductor substrate and a contact layer. The supporting substrate has a first surface and a second surface opposite to the first surface. The semiconductor substrate is disposed on the first surface of the supporting substrate, in which the semiconductor substrate is configured to form plural devices. The contact layer is disposed on the second surface of the supporting substrate to contact the supporting substrate, in which the contact layer is configured to contact an electrostatic chuck and has a resistivity of the contact layer smaller than a resistivity of the supporting substrate. In semiconductor wafer fabrication method, at first, a raw wafer is provided. Then, the contact layer is formed by using an implantation operation or a deposition operation.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: February 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yao-Wen Hsu, Ching-Hung Kao, Po-Jen Wang, Tsung-Han Tsai
  • Patent number: 10916679
    Abstract: An optical device wafer processing method for transferring an optical device layer of an optical device wafer onto a transfer member includes: a dividing groove forming step of forming dividing grooves in a buffer layer; a transfer member joining step of joining the transfer member to a front surface of the optical device layer; and a laser beam applying step of applying a pulsed laser beam from a back surface side of a crystalline substrate. In the laser beam applying step, the buffer layer, or the buffer layer and part of the optical device layer, left without being divided in the dividing groove forming step, are modified in nature.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: February 9, 2021
    Assignee: DISCO CORPORATION
    Inventor: Tasuku Koyanagi
  • Patent number: 10910451
    Abstract: A method for fabricating a flexible display substrate is provided. The method includes: forming a separation structure on a rigid substrate such that the separation structure includes a first separation layer and a second separation layer; forming a flexible substrate on the separation structure; forming a display element on the flexible substrate; and separating the first separation layer and the second separation layer of the separation structure mechanically to separate the rigid substrate from the flexible substrate.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: February 2, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jing Yang, Mingche Hsieh
  • Patent number: 10903263
    Abstract: A front-side type image sensor includes a substrate successively comprising a P? type doped semiconducting support substrate, an electrically insulating layer and a semiconducting active layer, and a matrix array of photodiodes in the active layer of the substrate, wherein the substrate comprises, between the support substrate and the electrically insulating layer, a P+ type doped semiconducting epitaxial layer A method of forming such a structure includes epitaxially growing a P+ type doped semiconducting layer on a P? type doped semiconducting support substrate, providing an electrically insulating layer and an active layer over the P+ type doped semiconducting layer, and forming photodiodes in the active layer.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: January 26, 2021
    Assignee: Soitec
    Inventor: Walter Schwarzenbach
  • Patent number: 10832906
    Abstract: A method for direct growth of a patterned transition metal dichalcogenide monolayer, the method including the steps of providing a substrate covered by a mask, the mask having a pattern defined by one or more shaped voids; thermally depositing a salt on the substrate through the one or more shaped voids such that a deposited salt is provided on the substrate in the pattern of the mask; and thermally co-depositing a transition metal oxide and a chalcogen onto the deposited salt to form the patterned transition metal dichalcogenide monolayer having the pattern of the mask. Also provided is a patterned transition metal dichalcogenide monolayer prepared according to the method.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: November 10, 2020
    Assignee: HONDA MOTOR CO., LTD.
    Inventors: Xufan Li, Avetik Harutyunyan
  • Patent number: 10832920
    Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor layer on the semiconductor substrate and having an exposed portion of a lower surface, a capping layer on the first semiconductor layer, a second semiconductor layer below the capping layer and having a side surface substantially in full contact with the capping layer, a cavity defined by the first semiconductor layer, the second semiconductor layer, and the capping layer, and a through-hole passing through the capping layer and the second semiconductor layer and extending to the cavity.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: November 10, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Xianchao Wang
  • Patent number: 10825719
    Abstract: A method for fabricating silicon-on-insulator (SOI) semiconductor devices, wherein the piezoresistive pattern is defined within a blanket doped layer after fusion bonding. This new method of fabricating SOI semiconductor devices is more suitable for simpler large scale fabrication as it provides the flexibility to select the device pattern/type at the latest stages of fabrication.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: November 3, 2020
    Assignee: Kulite Semiconductor Products, Inc.
    Inventors: Alexander A. Ned, Sorin Stefanescu, Joseph R. VanDeWeert
  • Patent number: 10818527
    Abstract: The present invention provides a substrate holding member comprising: a first holding member; a second holding member that cooperates with the first holding member to hold the substrate therebetween; and a transparent portion provided in at least one of the first and second holding members.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: October 27, 2020
    Assignee: EBARA CORPORATION
    Inventor: Ryuya Koizumi
  • Patent number: 10804252
    Abstract: A method of forming a device includes providing a first substrate having a first area and a second area, forming a range compensating material over the first substrate so that the first material is disposed over the first area and not disposed over the second area, implanting ions into the first area and the second area to form first and second cleave planes at first and second depths, respectively, each of the first and second cleave planes being defined by a concentration of the implanted ions, removing the range compensating material, and cleaving the first substrate along a cleave profile including the first and second cleave planes.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: October 13, 2020
    Assignee: Silicon Genesis Corporation
    Inventors: Theodore E. Fong, Michael I. Current
  • Patent number: 10770655
    Abstract: An integrated fan-out package including an integrated circuit, a plurality of memory devices, an insulating encapsulation, and a redistribution circuit structure is provided. The memory devices are electrically connected to the integrated circuit. The integrated circuit and the memory devices are stacked, and the memory devices are embedded in the insulating encapsulation. The redistribution circuit structure is disposed on the insulating encapsulation, and the redistribution circuit structure is electrically connected to the integrated circuit and the memory devices. Furthermore, methods for fabricating the integrated fan-out package are also provided.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: September 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee
  • Patent number: 10770289
    Abstract: A graphene-based layer transfer (GBLT) technique is disclosed. In this approach, a device layer including a III-V semiconductor, Si, Ge, III-N semiconductor, SiC, SiGe, or II-VI semiconductor is fabricated on a graphene layer, which in turn is disposed on a substrate. The graphene layer or the substrate can be lattice-matched with the device layer to reduce defect in the device layer. The fabricated device layer is then removed from the substrate via, for example, a stressor attached to the device layer. In GBLT, the graphene layer serves as a reusable and universal platform for growing device layers and also serves a release layer that allows fast, precise, and repeatable release at the graphene surface.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: September 8, 2020
    Assignee: Massachusetts Institute of Technology
    Inventor: Jeehwan Kim
  • Patent number: 10727299
    Abstract: A lateral bipolar junction transistor (LBJT) device that may include a dielectric stack including a pedestal of a base region passivating dielectric and a nucleation dielectric layer; and a base region composed of a germanium containing material or a type III-V semiconductor material in contact with the pedestal of the base region passivating dielectric. An emitter region and collector region may be present on opposing sides of the base region contacting a sidewall of the pedestal of the base region passivating dielectric and an upper surface of the nucleation dielectric layer.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: July 28, 2020
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Kevin K. Chan, Pouya Hashemi, Tak H. Ning, Alexander Reznicek
  • Patent number: 10727127
    Abstract: A method of processing a substrate, having a first surface with at least one division line formed thereon and a second surface opposite the first surface, includes applying a pulsed laser beam to the substrate from the side of the first surface, at least in a plurality of positions along the at least one division line, so as to form a plurality of modified regions in the substrate, each modified region extending at least from the first surface towards the second surface. Each modified region is formed by melting substrate material by means of the pulsed laser beam and allowing the molten substrate material to resolidify. The method further comprises removing substrate material along the at least one division line where the plurality of modified regions has been formed.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: July 28, 2020
    Assignee: DISCO CORPORATION
    Inventors: Hiroshi Morikazu, Karl Heinz Priewasser, Nao Hattori
  • Patent number: 10700012
    Abstract: A method of dicing a semiconductor wafer may include forming a porous silicon layer along an outline of dies singulated from the semiconductor wafer. The method may include sealing an active surface of the semiconductor wafer, including the porous silicon layer. The method may further include back grinding a rear surface of the semiconductor wafer to expose the porous silicon layer along the outline of the dies. The method also includes etching the semiconductor wafer to release the dies.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: June 30, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Stephen Alan Fanelli, Richard Hammond
  • Patent number: 10676386
    Abstract: The present invention relates to a method for separating solid-body slices (1) from a donor substrate (2). The method comprises the steps of: producing modifications (10) within the donor substrate (2) by means of laser beams (12), wherein a detachment region is predefined by the modifications (10), along which detachment region the solid-body layer (1) is separated from the donor substrate (2), and removing material from the donor substrate (2), starting from a surface (4) extending in the peripheral direction of the donor substrate (2), in the direction of the centre (Z) of the donor substrate (2), in particular in order to produce a peripheral indentation (6).
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: June 9, 2020
    Assignee: Siltectra GmbH
    Inventors: Marko Swoboda, Christian Beyer, Franz Schilling, Jan Richter
  • Patent number: 10658240
    Abstract: In a described example, a method includes: forming stress induced dislocations along scribe lanes between semiconductor dies on a semiconductor wafer using a laser; mounting a first side of the semiconductor wafer on the first side of a first dicing tape; removing a backgrinding tape from the semiconductor wafer; attaching a second dicing tape to a second side of the semiconductor wafer opposite the first side, the second dicing tape adhering to portions of the first dicing tape that are spaced from the semiconductor wafer, forming a dual taped wafer dicing assembly; separating the semiconductor dies by stretching the first dicing tape and stretching the second dicing tape; removing the second dicing tape from the semiconductor dies; and removing the semiconductor dies from the first dicing tape.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: May 19, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Shoichi Iriguchi, Hiroyuki Sada, Genki Yano
  • Patent number: 10658226
    Abstract: A method for preparing an SOI wafer by using rapid thermal processing includes: taking a silicon wafer as a raw material, sequentially performing process steps of oxidation, H+ implantation and bonding to obtain a bonded wafer with an H+ implantation layer; and then splitting the bonded wafer by using rapid thermal processing and microwaves to obtain a required SOI wafer. In the present invention, an SOI film after wafer splitting has better thickness uniformity and lower roughness. The present invention may improve lattice damage after implantation and reduce SOI surface defects after wafer splitting and thus improve the SOI surface quality. The present invention is high in wafer-splitting speed and thus reduces silicon wafer contamination. The present invention has high efficiency and an excellent comprehensive technical effect.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: May 19, 2020
    Assignee: Shenyang Silicon Technology Co., Ltd.
    Inventor: Jie Li
  • Patent number: 10644193
    Abstract: A method of manufacturing a light-emitting element includes: providing a wafer including: a substrate, and a semiconductor structure; forming a plurality of modified regions inside the substrate of the wafer by irradiating the substrate with a laser beam; and separating the wafer into a plurality of light-emitting elements after said irradiating the substrate with the laser beam. Said forming the plurality of modified regions includes: scanning the laser beam along a plurality of first lines, the plurality of first lines extending in a first direction and being arranged in a second direction, the first direction being parallel to the first surface, the second direction intersecting the first direction and being parallel to the first surface, and scanning the laser beam along a plurality of second lines, the plurality of second lines extending in the second direction and being arranged in the first direction.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: May 5, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Kazuki Yamaguchi, Haruki Takeda, Yoshitaka Sumitomo
  • Patent number: 10643836
    Abstract: A method is disclosed that includes operations as follows. With an ion-implanted layer which is disposed between an epitaxial layer and a first semiconductor substrate, the epitaxial layer is bonded directly to a second semiconductor substrate. The ion-implanted layer is split to separate the first semiconductor substrate from the epitaxial layer completely.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: May 5, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jing-Cheng Lin
  • Patent number: 10641962
    Abstract: A mirror and method of fabricating the mirror, the method comprising: providing a silicon-on-insulator substrate, the substrate comprising: a silicon support layer; a buried oxide (BOX) layer on top of the silicon support layer; and a silicon device layer on top of the BOX layer; creating a via in the silicon device layer, the via extending to the BOX layer; etching away a portion of the BOX layer starting at the via and extending laterally away from the via in a first direction to create a channel between the silicon device layer and silicon support layer; applying an anisotropic etch via the channel to regions of the silicon device layer and silicon support layer adjacent to the channel; the anisotropic etch following an orientation plane of the silicon device layer and silicon support layer to create a cavity underneath an overhanging portion of the silicon device layer; the overhanging portion defining a planar underside surface for vertically coupling light into and out of the silicon device layer; and a
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: May 5, 2020
    Assignee: Rockley Photonics Limited
    Inventors: Henri Nykänen, John Paul Drake, Evie Kho, Damiana Lerose, Sanna Leena Mäkelä, Amit Singh Nagra
  • Patent number: 10625257
    Abstract: Techniques for use of wafer bonding techniques for sealing of microfluidic chips are provided. In one aspect, a wafer bonding sealing method includes the steps of: forming a first oxide layer coating surfaces of a first wafer, the first wafer having at least one fluidic chip; forming a second oxide layer on a second wafer; and bonding the first wafer to the second wafer via an oxide-to-oxide bond between the first oxide layer and the second oxide layer to form a bonded wafer pair, wherein the second oxide layer seals the at least one fluidic chip on the first wafer. The second wafer can be at least partially removed after performing the bonding, and fluidic ports may be formed in the second oxide layer. A fluidic chip device is also provided.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: April 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Joshua T. Smith, Cornelia K. Tsang, Chao Wang, Benjamin H. Wunsch
  • Patent number: 10615139
    Abstract: A wafer-to-wafer semiconductor device includes a first wafer substrate having a first bonding layer formed on a first bulk substrate layer. A second wafer substrate includes a second bonding layer formed on a second bulk substrate layer. The second bonding layer is bonded to the first bonding layer to define a bonding interface. At least one of the first wafer substrate and the second wafer substrate includes a crack-arresting film layer configured to increase a bonding energy of the bonding interface.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: April 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wei Lin, Leathen Shi, Spyridon Skordas, Kevin R. Winstel
  • Patent number: 10600677
    Abstract: A method for manufacturing a bonded SOI wafer including a step of performing a heat treatment to each bonded SOI wafer having an oxide film on a back surface thereof in an argon atmosphere to flatten a front surface of an SOI layer, wherein, at the time of performing the heat treatment in the argon atmosphere in a batch processing heat treatment furnace, a silicon wafer is arranged as a dummy wafer between the adjacent bonded SOI wafers housed in the batch processing heat treatment furnace to perform the heat treatment. Consequently, there is the method for manufacturing an SOI wafer which enables suppressing an increase in LPDs at the step of performing the heat treatment to a bonded SOI wafer having an oxide film on a back surface thereof in an argon atmosphere in a batch processing heat treatment furnace to flatten a front surface of an SOI layer.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: March 24, 2020
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Toru Ishizuka, Setsuya Hama
  • Patent number: 10593843
    Abstract: A method of manufacturing an optical component for an optical semiconductor includes: providing a joined body including: a first member having light transmissivity and containing at least one element selected from the group consisting of oxygen, fluorine, and nitrogen, and a second member, wherein the first member and the second member are joined together via a metal joining member made by directly bonding a first metal film formed on the first member and a second metal film formed on the second member; and irradiating the joining member with a laser beam or a microwave.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: March 17, 2020
    Assignee: NICHIA CORPORATION
    Inventor: Masatsugu Ichikawa
  • Patent number: 10586505
    Abstract: A transistor whose channel region includes an oxide semiconductor is used as a pull down transistor. The band gap of the oxide semiconductor is 2.0 eV or more, preferably 2.5 eV or more, more preferably 3.0 eV or more. Thus, hot carrier degradation in the transistor can be suppressed. Accordingly, the circuit size of the semiconductor device including the pull down transistor can be made small. Further, a gate of a pull up transistor is made to be in a floating state by switching of on/off of the transistor whose channel region includes an oxide semiconductor. Note that when the oxide semiconductor is highly purified, the off-state current of the transistor can be 1 aA/?m (1×10?18 A/?m) or less. Therefore, the drive capability of the semiconductor device can be improved.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: March 10, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsushi Umezaki, Hajime Kimura