Abstract: In one embodiment, a method of forming a semiconductor device comprises forming a groove on and/or over a first side of a substrate. A dicing layer is formed from a second side of the substrate using a laser process. The second side is opposite the first side. The dicing layer is disposed under the groove within the substrate. The substrate is singulated through the dicing layer.

Abstract: Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging microelectronic device panels in a panel stack. Each microelectronic device panel includes a plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are formed in the panel stack exposing the plurality of package edge conductors. An electrically-conductive material is deposited into the trenches and contacts the plurality of package edge conductors exposed therethrough. The panel stack is then separated into partially-completed stacked microelectronic packages. For at least one of the partially-completed stacked microelectronic packages, selected portions of the electrically-conductive material are removed to define a plurality of patterned sidewall conductors interconnecting the microelectronic devices included within the stacked microelectronic package.

Abstract: According to a semiconductor substrate (40), a space (A) between a plurality of Si thin film (16), which are provide apart from one another on the insulating substrate (30), is (I) larger than a difference between elongation of part of the insulating substrate which part corresponds to the space (A) and elongation of each of Si wafers (10) when a change is made from room temperature to 600° C. and (II) smaller than 5 mm. This causes an increase in a region of each of a plurality of semiconductor thin films which region has a uniform thickness, and therefore prevents transferred semiconductor layers and the insulating substrate from being fractured or chipped.

Abstract: The present invention has an object to perform a peeling treatment in a short time. Peeling is performed while a peeling layer is exposed to an atmosphere of an etching gas. Alternatively, peeling is performed while an etching gas for a peeling layer is blown to the peeling layer in an atmosphere of an etching gas. Specifically, an etching gas is blown to a part to be peeled while a layer to be peeled is torn off from a substrate. Alternatively, peeling is performed in an etchant for a peeling layer while supplying an etchant to the peeling layer.

Abstract: A patterned adhesive layer including holes is employed to attach a coreless substrate layer to a stiffener. The patterned adhesive layer is confined to kerf regions, which are subsequently removed during singulation. Each hole in the patterned adhesive layer has an area that is greater than the area of a bottomside interconnect footprint of the coreless substrate. The patterned adhesive layer may include a permanent adhesive that is thermally curable or ultraviolet-curable. The composition of the stiffener can be tailored so that the thermal coefficient of expansion of the stiffener provides tensile stress to the coreless substrate layer at room temperature and at the bonding temperature. The tensile stress applied to the coreless substrate layer prevents or reduces warpage of the coreless substrate layer during bonding. Upon dicing, bonded stacks of a semiconductor chip and a coreless substrate can be provided without adhesive thereupon.

Abstract: An integrated circuit assembly includes an insulating layer having a having a first surface and a second surface. A first active layer contacts the first surface of the insulating layer. A metal bond pad is electrically connected to the first active layer and formed on the second surface of the insulating layer. A substrate having a first surface and a second surface, with a second active layer formed in the first surface, is provided such that the first active layer is coupled to the second surface of the substrate.

Abstract: A semiconductor wafer comprises, on a semiconductor crystal layer forming wafer, a first semiconductor crystal layer, a second semiconductor crystal layer, and a third semiconductor crystal layer in this order, wherein both the etching rates of the first semiconductor crystal layer and the third semiconductor crystal layer by a first etching agent are higher than the etching rate of the second semiconductor crystal layer by the first etching agent, and both the etching rates of the first semiconductor crystal layer and the third semiconductor crystal layer by a second etching agent are lower than the etching rate of the second semiconductor crystal layer by the second etching agent.

Abstract: A semiconductor wafer is provided. The semiconductor wafer comprises a sacrificial layer and a semiconductor crystal layer above a semiconductor crystal layer forming wafer, the semiconductor crystal layer forming wafer, the sacrificial layer and the semiconductor crystal layer being arranged in the order of the semiconductor crystal layer forming wafer, the sacrificial layer and the semiconductor crystal layer, wherein the semiconductor wafer comprises a diffusion inhibiting layer that inhibits diffusion of a first atom of one type selected from a plurality of types of atoms constituting the semiconductor crystal layer forming wafer or the sacrificial layer, at any cross-sectional position between (a) the interface of the semiconductor crystal layer forming wafer that faces the sacrificial layer and (b) a middle of the semiconductor crystal layer.

Abstract: Methods are provided for using masking techniques and plasma etching techniques to dice a compound semiconductor wafer into dies. Using these methods allows compound semiconductor die to be obtained that have smooth side walls, a variety of shapes and dimensions, and a variety of side wall profiles. In addition, by using these techniques to perform the dicing operations, the locations of features of the die relative to the side walls are ascertainable with certainty such that one or more of the side walls can be used as a passive alignment feature to precisely align one or more of the die with an external device.

Abstract: Ion-reduced, ion cut-formed three-dimensional (3D) integrated circuits (IC) (3DICs) are disclosed. Related methods and systems are also disclosed. During an ion-cut process for forming a monolithic 3DIC, extra ions are implanted in the donor wafer to effectuate the ion-cut. Excess, residual implanted ions remain implanted in a top layer of the transfer layer of the 3DIC. However, these residual implanted ions can interfere with operation of electronic components in the 3DIC. In this regard, the 3DIC and methods disclosed herein involve reduction or removal of the residual extra ions before further electronic components are created and layered in a 3DIC. In this manner, the extra charge elements introduced by such extra ions are reduced or removed providing for better functionality in the completed device.

Abstract: Disclosed is a semiconductor device having a radio frequency switch. Also disclosed are an antenna switch module and a method of manufacturing the semiconductor device. The semiconductor device includes a metal wiring insulating film bonded to a silicon substrate. In the semiconductor device, a crystal defect layer extends into the silicon substrate from a surface of the silicon substrate. Crystal defects are throughout the crystal defect layer. The semiconductor device and an integrated circuit are in the antenna switch module. The integrated circuit in the antenna switch module is mounted with the radio-frequency switch device and the silicon substrate. The method of manufacturing the semiconductor device includes a step of forming crystal defects throughout a silicon substrate. Radiation or a diffusion is used to form the crystal defects. After the step of forming the crystal defects, the method includes a step of implanting ions into a surface of the silicon substrate to form a crystal defect layer.

Abstract: To provide a resource-saving photoelectric conversion device with excellent photoelectric conversion characteristics. Thin part of a single crystal semiconductor substrate, typically a single crystal silicon substrate, is detached to structure a photoelectric conversion device using a thin single crystal semiconductor layer, which is the detached thin part of the single crystal semiconductor substrate. The thin part of the single crystal semiconductor substrate is detached by a method in which a substrate is irradiated with ions accelerated by voltage, or a method in which a substrate is irradiated with a laser beam which makes multiphoton absorption occur. A so-called tandem-type photoelectric conversion device is obtained by stacking a unit cell including a non-single-crystal semiconductor layer over the detached thin part of the single crystal semiconductor substrate.

Abstract: A semiconductor device with an SRAM memory cell having improved characteristics. Below an active region in which a driver transistor including a SRAM is placed, an n type back gate region surrounded by an element isolation region is provided via an insulating layer. It is coupled to the gate electrode of the driver transistor. A p well region is provided below the n type back gate region and at least partially extends to a position deeper than the element isolation region. It is fixed at a grounding potential. Such a configuration makes it possible to control the threshold potential of the transistor to be high when the transistor is ON and to be low when the transistor is OFF; and control so as not to apply a forward bias to the PN junction between the p well region and the n type back gate region.

Abstract: A method for processing a semiconductor wafer includes applying a release layer to a transparent handler. An adhesive layer, that is distinct from the release layer, is applied between a semiconductor wafer and the transparent handler having the release layer applied thereon. The semiconductor wafer is bonded to the transparent handler using the adhesive layer. The semiconductor wafer is processed while it is bonded to the transparent handler. The release layer is ablated by irradiating the release layer through the transparent handler with a laser. The semiconductor wafer is removed from the transparent handler.

Abstract: The present invention provides a method for manufacturing an SOI wafer, in which an insulator film is formed at least on all surfaces of a base wafer, and while protecting a first part of the insulator film on a back surface on the opposite side from a bonded surface of the base wafer, a bonded wafer before separating a bond wafer along a layer of the implanted ion is brought into contact with a liquid capable of dissolving the insulator film or exposed to a gas capable of dissolving the insulator film, and a second part of the insulator film interposed between the bond wafer and the base wafer is etched from an outer circumferential edge of the bonded wafer and toward the center of the bonded wafer. The method can control the terrace width and inhibit warping of the SOI wafer in a bonding process with a base wafer.

Abstract: A method includes etching a release layer that is coupled between a plurality of semiconductor devices and a substrate with an etch. The etching includes etching the release layer between the semiconductor devices and the substrate until the semiconductor devices are at least substantially released from the substrate. The etching also includes etching a protuberance in the release layer between each of the semiconductor devices and the substrate. The etch is stopped while the protuberances remain between each of the semiconductor devices and the substrate. The method also includes separating the semiconductor devices from the substrate. Other methods and apparatus are also disclosed.

Abstract: A method for processing substrates includes providing a bonding layer between a substrate and a carrier to bond the substrate to the carrier, processing the substrate while the substrate is supported by the carrier, and removing the bonding layer to separate the substrate from the carrier. The bonding layer may include a thermosetting release layer and thermosetting glue layers, wherein at least one of the thermosetting glue layers is provided on each side of the thermosetting release layer.

Abstract: The present invention is a method for manufacturing a bonded wafer, including performing a plasma activation treatment on at least one of the bonded surfaces of the bond wafer and the base wafer before bonding, wherein the plasma activation treatment is performed while a back surface of at least one of the bond wafer and the base wafer is placed on a stage with the back surface being in point contact or line contact with the stage. The method can inhibit increase in attached substances such as particles on the back surface of a wafer during the plasma activation treatment, and prevent re-attachment of the attached substances to the bonded surface of the wafer, particularly when the wafer after the plasma activation treatment is cleaned with a batch cleaning apparatus.

Abstract: A method of processing a device wafer in a wafer stack by chucking the wafer stack device side down and grinding the exposed side of the carrier wafer to parallel with the device wafer, and thereafter flipping the wafer stack and chucking the wafer stack carrier side down and grinding residual silicon from the device wafer.

Abstract: A method of preparing a single crystal semiconductor handle wafer in the manufacture of a silicon-on-insulator device is provided. The method comprises forming a multilayer of passivated semiconductors layers on a dielectric layer of a high resistivity single crystal semiconductor handle wafer. The method additionally comprises forming a semiconductor oxide layer on the multilayer of passivated semiconductor layers. The multilayer of passivated semiconductor layers comprise materials suitable for use as charge trapping layers between a high resistivity substrate and a buried oxide layer in a semiconductor on insulator structure.

Abstract: A method for manufacturing an electronic component includes a first step of preparing a piezoelectric body with a flat surface, a second step of implanting ions into the piezoelectric body such that an ion-implanted layer is formed in the piezoelectric body, a third step of forming sacrificial layers on the flat surface of the piezoelectric body, a fourth step of forming an insulating body over the flat surface of the piezoelectric body and the sacrificial layers to form a piezoelectric structure, a fifth step of dividing the piezoelectric body at the ion-implanted layer to form a piezoelectric laminar structure in which a piezoelectric film separated from the piezoelectric body is bonded to the insulating body, a sixth step of forming electrodes on portions of a division surface of the piezoelectric film, and a seventh step of removing the sacrificial layers from the piezoelectric laminar structure.

Abstract: A heterojunction III-V photovoltaic (PV) cell includes a base layer comprising a III-V substrate, the base layer being less than about 20 microns thick; an intrinsic layer located on the base layer; an amorphous silicon layer located on the intrinsic layer; and a transparent conducting oxide layer located on the amorphous silicon layer.

Abstract: The present invention provides a simplifying method for a peeling process as well as peeling and transcribing to a large-size substrate uniformly. A feature of the present invention is to peel a first adhesive and to cure a second adhesive at the same time in a peeling process, thereby to simplify a manufacturing process. In addition, the present invention is to devise the timing of transcribing a peel-off layer in which up to an electrode of a semiconductor are formed to a predetermined substrate. In particular, a feature is that peeling is performed by using a pressure difference in the case that peeling is performed with a state in which plural semiconductor elements are formed on a large-size substrate.

Abstract: A method of preparing a high resistivity single crystal semiconductor handle wafer comprising implanting He ions through a front surface of the high resistivity single crystal semiconductor handle wafer, which is followed by an anneal sufficient to form a nanocavity layer in the damage region formed by He ion implantation. The anneal may be prior to or concurrent with thermal oxidation to prepare a front oxidized surface layer.

Abstract: A thin sheet (20) disposed on a carrier (10) via a surface modification layer (30) to form an article (2), wherein the article may be subjected to high temperature processing, as in FEOL semiconductor processing, not outgas and have the thin sheet maintained on the carrier without separation therefrom during the processing, yet be separated therefrom upon room temperature peeling force that leaves the thinner one of the thin sheet and carrier intact. Interposers (56) having arrays (50) of vias (60) may be formed on the thin sheet, and devices (66) formed on the interposers. Alternatively, the thin sheet may be a substrate on which semiconductor circuits are formed during FEOL processing.

Abstract: Methods for forming a layer of semiconductor material are provided. A substrate is provided. An amorphous layer is formed over the substrate, where the amorphous layer includes a semiconductor or a semiconductor alloy. A seed wafer is bonded to the amorphous layer, where the seed wafer includes a crystalline semiconductor structure. A solid-phase epitaxial (SPE) growth process is performed to crystallize the amorphous layer, where the SPE growth process uses the crystalline semiconductor structure of the seed wafer as a crystal template. The seed wafer is debonded from the structure.

Abstract: A method of fabricating a semiconductor substrate, includes forming a first semiconductor layer on a substrate, forming a metallic material layer on the first semiconductor layer, forming a second semiconductor layer on the first semiconductor layer and the metallic material layer, etching the substrate using a solution to remove the metallic material layer and a portion of the first semiconductor layer, and forming a cavity in the first semiconductor layer under where the metallic material layer was removed.

Abstract: Methods of manufacturing a plurality of semiconductor chips are provided. The method may include providing a middle layer between a substrate and a carrier to combine the carrier with the substrate, thinning the substrate; after thinning the substrate, separating the carrier from the substrate; and after the carrier is separated from the substrate, cutting the substrate to form the plurality of semiconductor chips, wherein the middle layer is adhered to the carrier with a first bonding force, and the middle layer is adhered to the substrate with a second bonding force, and wherein the second bonding force is greater than the first bonding force.

Abstract: Semiconductor trilayer structures that are doped and strained are provided. Also provided are mechanically flexible transistors, including radiofrequency transistors, incorporating the trilayer structures and methods for fabricating the trilayer structures and transistors. The trilayer structures comprise a first layer of single-crystalline semiconductor material, a second layer of single-crystalline semiconductor material and a third layer of single-crystalline semiconductor material. In the structures, the second layer is in contact with and sandwiched between the first and third layers and the first layer is selectively doped to provide one or more doped regions in the layer.

Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor light emitting device. The method can include forming a nitride semiconductor layer including a light emitting layer on a first substrate having an unevenness, bonding the nitride layer to a second substrate, and separating the first substrate from the nitride layer by irradiating the nitride layer with light. The forming the nitride layer includes leaving a cavity in a space inside a depression of the unevenness while forming a thin film on the depression. The film includes a same material as part of the nitride layer. The separating includes causing the film to absorb part of the light so that intensity of the light applied to a portion of the nitride layer facing the depression is made lower than intensity of the light applied to a portion facing a protrusion of the unevenness.

Abstract: Embodiments of the present description relate to the field of fabricating microelectronic structures. The microelectronic structures may include a glass routing structure formed separately from a trace routing structure, wherein the glass routing structure is incorporated with the trace routing substrate, either in a laminated or embedded configuration. Also disclosed are embodiments of a microelectronic package including at least one microelectronic device disposed proximate to the glass routing structure of the microelectronic substrate and coupled with the microelectronic substrate by a plurality of interconnects. Further, disclosed are embodiments of a microelectronic structure including at least one microelectronic device embedded within a microelectronic encapsulant having a glass routing structure attached to the microelectronic encapsulant and a trace routing structure formed on the glass routing structure.

Abstract: A graphene device may include a channel layer including graphene, a first electrode and second electrode on a first region and second region of the channel layer, respectively, and a capping layer covering the channel layer and the first and second electrodes. A region of the channel layer between the first and second electrodes is exposed by an opening in the capping layer. A gate insulating layer may be on the capping layer to cover the region of the channel layer, and a gate may be on the gate insulating layer.

Abstract: According to an embodiment of the present disclosure, a substrate inverting device for inverting front and rear surfaces of a substrate is provided. The substrate includes a first holding unit configured to hold one surface of the substrate and a second holding unit disposed to face the first holding unit and configured to hold one surface of the substrate. Further, the substrate includes a moving mechanism configured to relatively move at least one of the first holding unit and the second holding unit to approach each other and stay spaced apart from each other, and a transfer mechanism configured to hold the one surface of the substrate. In this case, a support of the substrate in the first holding unit, the second holding unit and the transfer mechanism is performed by a Bernoulli chuck.

Abstract: The invention is directed to a temporary adhesive for production of semiconductor device, containing (A) a polymer compound having an acid group, (B) a diluent, and (C) a solvent, an adhesive support including a substrate and an adhesive layer formed from the temporary adhesive for production of semiconductor device, and a production method of semiconductor device having a member processed including: adhering a first surface of a member to be processed to a substrate through an adhesive layer formed from the temporary adhesive for production of semiconductor device as claimed; conducting a mechanical or chemical processing on a second surface which is different from the first surface of the member to be processed to obtain the member processed; and releasing the first surface of the member processed from the adhesive layer.

Abstract: A thickness of material may be detached from a substrate along a cleave plane, utilizing a cleaving process controlled by a releasable constraint plate. In some embodiments this constraint plate may comprise a plate that can couple side forces (the “P-plate”) and a thin, softer compliant layer (the “S-layer”) situated between the P-plate and the substrate. In certain embodiments a porous surface within the releasable constraint plate and in contact to the substrate, allows the constraint plate to be secured to the substrate via a first pressure differential. Application of a combination of a second pressure differential within a pre-existing cleaved portion, and a linear force to a side of the releasable constraint plate bound to the substrate, generates loading that results in controlled cleaving along the cleave plane.

Abstract: Method for manufacturing a microelectronic device from a first substrate (10), including the production of at least one electronic component in the semi-conductor substrate after transferring the first substrate (10) onto a second substrate (20), characterized in that it comprises: a first phase carried out prior to the transfer, and including forming at least one pattern made of a sacrificial material in a layer of the first substrate (10), a second phase carried out after the transfer and including the substitution of the electronic component for the pattern.

Abstract: In one embodiment, a method includes depositing a photoactive layer onto a first substrate, depositing a contact layer onto the photoactive layer, attaching a second substrate onto the contact layer, and removing the first substrate from the photoactive layer, contact layer, and second substrate.

Abstract: An automatic cutting device is described for cutting an assembly. The assembly includes a material having a weakened zone therein that defines a useful layer and being attached to a source substrate. The cutting device includes a cutting mechanism and a holding and positioning mechanism operatively associated with the cutting mechanism. The holding and positioning mechanism positions the material so that the cutting mechanism detaches the layer from the source substrate along the weakened zone. The cutting device also includes a control mechanism for adjusting at least two different portions of the assembly during detachment of the layer to facilitate a more precise detachment.

Abstract: Laser lift off systems and methods may be used to provide monolithic laser lift off with minimal cracking by reducing the size of one or more beam spots in one or more dimensions to reduce plume pressure while maintaining sufficient energy to provide separation. By irradiating irradiation zones with various shapes and in various patterns, the laser lift off systems and methods use laser energy more efficiently, reduce cracking when separating layers, and improve productivity. Some laser lift off systems and methods described herein separate layers of material by irradiating non-contiguous irradiation zones with laser lift off zones (LOZs) that extend beyond the irradiation zones. Other laser lift off systems and methods described herein separate layers of material by shaping the irradiation zones and by controlling the overlap of the irradiation zones in a way that avoids uneven exposure of the workpiece.

Abstract: System for wafer-level phosphor deposition. In an aspect, a semiconductor wafer is provided that includes a plurality of LED dies wherein at least one die includes an electrical contact, a photo-resist post covering the electrical contact, and a phosphor deposition layer covering the semiconductor wafer and surrounding the photo-resist post. In another aspect, a semiconductor wafer is provided that comprises a plurality of LED dies wherein at least one die comprises an electrical contact, a phosphor deposition layer covering the semiconductor wafer, and a cavity in the phosphor deposition layer exposing the at least one electrical contact.

Abstract: Methods of preparing a thin crystalline silicon film for transfer and devices utilizing a transferred crystalline silicon film are disclosed. The methods include preparing a silicon growth substrate which has an interface defining substance associated with an exterior surface. The methods further include depositing an epitaxial layer of silicon on the silicon growth substrate at the surface and separating the epitaxial layer from the substrate substantially along the plane or other surface defined by the interface defining substance. The epitaxial layer may be utilized as a thin film of crystalline silicon in any type of semiconductor device which requires a crystalline silicon layer. In use, the epitaxial transfer layer may be associated with a secondary substrate.

Abstract: A method for making a solar cell is disclosed. In accordance with the method of the present invention a composite wafer is formed. The composite layer includes a single crystal silicon wafer, a silicon-based device layer and sacrificial porous silicon sandwiched therebetween. The composite wafer is treated to an aqueous etchant maintained below ambient temperatures to selectively etch the sacrificial porous silicon and release or undercut the silicon-based layer from the single crystal silicon wafer. The released silicon device layer is attached to a substrate to make a solar cell and the released single crystal silicon wafer is reused to make additional silicon device layer.

Abstract: The present invention relates to a process for direct bonding two substrates, comprising at least: (a) bringing the surfaces to be bonded of said substrates in close contact; and (b) propagating a bonding wave between said substrates, characterised in that said substrates are kept, during step (b), in an atmosphere of a gas having a negative Joule-Thomson coefficient at the temperature and pressure of said atmosphere.

Abstract: The present invention relates to a method for separating epitaxial layers and growth substrates, and to a semiconductor device using same. According to the present invention, a semiconductor device is provided which comprises a supporting substrate and a plurality of semiconductor layers provided on the supporting substrate, wherein the uppermost layer of the semiconductor layers has a surface of non-uniform roughness.

Abstract: According to one embodiment, a first adhesive layer is formed on one major surface of a first substrate. The first substrate and a second substrate are adhered using a second adhesive layer that has thermosetting properties and covers the first adhesive layer, wherein a bonding strength between the second substrate is greater than a bonding strength between the second substrate and the first adhesive layer. The other major surface of the first substrate is polished, and the first substrate is thinned. A physical force is then applied to peripheral parts of the second adhesive layer, and a circular notched part is formed along the outer perimeter of the second adhesive layer to separate the first substrate and the second substrate at the interface between the first adhesive layer and the second adhesive layer.

Abstract: A method for manufacturing a bonded wafer having a semiconductor film on a handle substrate involving the steps of: implanting ions into a semiconductor substrate to form an ion-implanted layer; subjecting the surface of at least one of the semiconductor substrate and the handle substrate to a surface activation treatment; bonding the surface of the semiconductor substrate to the surface of the handle substrate at a temperature from 50° C. to 350° C.; heating the bonded substrates at a maximum temperature from 200° C. to 350° C. to obtain a bonded body; and transferring a semiconductor film to the handle substrate by subjecting the bonded body to a temperature 30° C. to 100° C. higher than the bonding temperature, and irradiating the bonded body with visible light from a handle or semiconductor substrate side toward the ion-implanted layer of the semiconductor substrate to embrittle the interface of the ion-implanted layer.

Abstract: A transparent board is positioned on a support board provided with a positioning mark, and a release material is provided. A semiconductor element is then positioned so that the electrode element faces upward, and the support board is then removed. An insulating resin is then formed on the release material so as to cover the semiconductor element; and a via, a wiring layer, an insulation layer, an external terminal, and a solder resist are then formed. The transparent board is then peeled from the semiconductor device through the use of the release material. A chip can thereby be mounted with high precision, there is no need to provide a positioning mark during mounting of the chip on the substrate in the manufacturing process, and the substrate can easily be removed. As a result, a semiconductor device having high density and a thin profile can be manufactured at low cost.

Abstract: A method for bonding of a first contact surface of a first substrate to a second contact surface of a second substrate. The method comprises: forming at least one reservoir in at least one reservoir formation layer on the first substrate and/or the second substrate, the reservoir comprised of an amorphous material, at least partial filling of the reservoir/reservoirs with a first educt or a first group of educts, forming or applying a reaction layer which contains a second educt or a second group of educts to the reservoir and/or the reservoir, the first contact surface making contact with the second contact surface for formation of a prebond connection, and forming a permanent bond between the first and second contact surface, at least partially strengthened by the reaction of the first educt or the first group with the second educt or the second group.

Abstract: The present invention provides a method for manufacturing an SOI wafer, in which an insulator film is formed at least on all surfaces of a base wafer, and while protecting a first part of the insulator film on a back surface on the opposite side from a bonded surface of the base wafer, a bonded wafer before separating a bond wafer along a layer of the implanted ion is brought into contact with a liquid capable of dissolving the insulator film or exposed to a gas capable of dissolving the insulator film, and a second part of the insulator film interposed between the bond wafer and the base wafer is etched from an outer circumferential edge of the bonded wafer and toward the center of the bonded wafer. The method can control the terrace width and inhibit warping of the SOI wafer in a bonding process with a base wafer.

Abstract: A method of fabricating an electronic component includes: mounting a device chip on an upper surface of an insulative substrate; forming a sealing portion that seals the device chip; cutting the insulative substrate and the sealing portion; and forming a plated layer covering the sealing portion by barrel plating.