Abstract: A packaging structure and a method of forming a packaging structure are provided. The packaging structure, such as an interposer, is formed by optionally bonding two carrier substrates together and simultaneously processing two carrier substrates. The processing includes forming a sacrificial layer over the carrier substrates. Openings are formed in the sacrificial layers and pillars are formed in the openings. Substrates are attached to the sacrificial layer. Redistribution lines may be formed on an opposing side of the substrates and vias may be formed to provide electrical contacts to the pillars. A debond process may be performed to separate the carrier substrates. Integrated circuit dies may be attached to one side of the redistribution lines and the sacrificial layer is removed.

Abstract: Device and a method of forming a device are disclosed. The method includes providing a crystalline-on-insulator (COI) substrate. The COI substrate includes at least a base substrate over a buried insulator layer. Through via (TV) contacts are formed within the substrate. The TV contact extends from a top surface of the base substrate to within the buried insulator layer. Upper interconnect levels are formed over the top surface of the base substrate. A lower redistribution (RDL) is formed over a bottom surface of the base substrate. The buried insulator layer corresponds to a first RDL dielectric layer of the lower RDL and protects the sidewalls of the TV contacts.

Abstract: A rotational misalignment between semiconductor wafers constituting a bonded wafer is calculated. A light source is arranged at a position which is on a front side of an opening of a notch and which is separated from an outer edge portion of a bonded wafer by a predetermined interval, and outputs light to irradiate the outer edge portion of the bonded wafer including the notch. A camera receives and photoelectrically converts reflected light that is specularly-reflected by the outer edge portion of the bonded wafer including the notch among the light outputted by the light source in order to output a brightness distribution of the reflected light as an image. A computer analyzes positions of notches from the image outputted by the camera to obtain a notch position misalignment, and further calculates a rotational misalignment between semiconductor wafers using a center position misalignment between the semiconductor wafers.

Abstract: This transfer process comprises the following steps: (a) providing a donor substrate and a support substrate; (b) forming an embrittlement region in the donor substrate; (c) forming what is called a bonding layer between the first part of the donor substrate and the support substrate; and (d) assembling the donor substrate to the support substrate, and is noteworthy in that it comprises the following step: (e) exposing, in succession, portions of the embrittlement region to electromagnetic irradiations for an exposure time at a given power density, the exposure time being chosen depending on the thickness of the bonding layer so that the support substrate is thermally decoupled from the first part of the donor substrate, the exposure time being chosen depending on the power density in order to activate kinetics that weaken the embrittlement region.

Abstract: A semiconductor structure includes a III-V monocrystalline layer and a germanium surface layer. An interlayer is formed directly between the III-V monocrystalline layer and the germanium surface layer from a material selected to provide stronger nucleation bonding between the interlayer and the germanium surface layer than nucleation bonding that would be achievable directly between the III-V monocrystalline layer and the germanium surface layer such that a continuous, relatively defect-free germanium surface layer is provided.

Abstract: The invention relates to a process for fabricating a heterostructure comprising at least one thin layer and a carrier substrate made of a semiconductor, the process comprising: bonding a first substrate made of a single-crystal first material, the first substrate comprising a superficial layer made of a polycrystalline second material, to a second substrate so that a bonding interface is created between the polycrystalline layer and the second substrate; removing from the free surface of one of the substrates, called the donor substrate, a thickness thereof so that only a thin layer is preserved; generating a layer of amorphous semiconductor material between the first substrate and the bonding interface by amorphization of the layer of polycrystalline material; and crystallizing the layer of amorphous semiconductor material, the newly crystallized layer having the same orientation as the adjacent first substrate.

Abstract: A method for manufacturing a light-emitting device comprises the steps of: providing a first substrate; forming a semiconductor structure on the first substrate, wherein the semiconductor structure comprises a first type semiconductor layer, a second type semiconductor layer, and an active layer between the first type semiconductor layer and the second type semiconductor layer; forming an isolation region through the second type semiconductor and the active layer to separate the semiconductor structure into a first part and a second part on the first substrate; and injecting an electrical current with a current density to the second part to make the second part to be permanently broken-down; wherein after the second part is permanently broken-down, the first part is capable of generating electromagnetic radiation and the second part is incapable of generating electromagnetic radiation.

Abstract: Methods of creating various laser-defined control structures on pressure relief devices are provided that utilize a laser having a field of view that is smaller than the overall dimensions of the laser-defined structure to be milled into the pressure relief device. The methods generally involve partitioning the working surface of the device into a plurality of tiles within which a particular segment of the control structure will be milled. Upon milling of a control structure segment in one tile, the pressure relief device and/or laser is repositioned so that a control structure segment in another tile may be created.

Abstract: Methods for removing a material layer from a base substrate utilizing spalling in which mode III stress, i.e., the stress that is perpendicular to the fracture front created in the base substrate, during spalling is reduced. The substantial reduction of the mode III stress during spalling results in a spalling process in which the spalled material has less surface roughness at one of its' edges as compared to prior art spalling processes in which the mode III stress is present and competes with spalling.

Abstract: The present disclosure relates to a method of cutting a flexible display device, capable of preventing a generation of a defect at the time of cutting the flexible display device, the method including providing a glass mother substrate having a flexible substrate attached thereon and an insulating layer formed on the flexible substrate; melting the flexible substrate and the insulating layer on the mother substrate by irradiating with a first laser beam; and cutting the mother substrate exposed by the irradiation of the first laser beam using a cutting device.

Abstract: Methods of making optoelectronic devices containing functional elements made from layers liberated from natural and/or fabricated lamellar semiconductor donors. In one embodiment, a donor is provided, a layer is detached from the donor, and the layer is incorporated into an optoelectronic device as a functional element thereof. The thickness of the detached layer is tuned as needed to suit the functionality of the functional element. Examples of functional elements that can be made using detached layers include p-n junctions, Schotkey junctions, PIN junctions, and confinement layers, among others. Examples of optoelectronic devices that can incorporate detached layers include LEDs, laser diodes, MOSFET transistors, and MISFET transistors, among others.

Abstract: A method for processing a semiconductor carrier is provided, the method including: providing a semiconductor carrier including a doped substrate region and a device region disposed over a first side of the doped substrate region, the device region including at least part of one or more electrical devices; and implanting ions into the doped substrate region to form a gettering region in the doped substrate region of the semiconductor carrier.

Abstract: A method for fabricating a semiconductor device is provided. The method includes: providing a first wafer having a first active surface and a first rear surface opposite to the first active surface, the first wafer comprising a first circuit formed therein; providing a second wafer having a second active surface and a second rear surface opposite to the second active surface, the second wafer comprising a second circuit formed therein; bonding the first active surface of the first wafer with the second active surface of the second wafer so as to electrically connecting the first circuit and the second circuit; thinning the second wafer from the second rear surface; and forming at least a conductive through via in the second wafer, wherein the conductive through via is electrically connected to the first circuit through the second circuit.

Abstract: The present disclosure relates to a back-side illuminated CMOS image sensor (BSI CIS). In some embodiments, the BSI CSI has a semiconductor substrate with a front-side and a back-side. A plurality of photodetectors are located within the front-side of the semiconductor substrate. An implantation region is located within the semiconductor substrate at a position separated from the plurality of photodetectors. The implantation region is disposed below the plurality of photodetectors and has a non-uniform doping concentration along a lateral plane parallel to the back-side of the semiconductor substrate. The non-uniform doping concentration allows for the BSI CSI to achieve a small total thickness variation (TTV) between one or more photodetectors and a back-side of a thinned semiconductor substrate that provides for good device performance.

Abstract: A bolometer and a preparation method thereof. The bolometer includes: an infrared detection element (1) and a readout circuit (2), wherein the infrared detection element (1) is formed on one side of a first substrate (100), and an edge of the infrared detection element (1) is provided with an electrode hole (9), and the readout circuit (2) is formed on one side of a second substrate (200) and the readout circuit (2) has an electrode, the first substrate (100) is formed thereon with a silicon via (8) passing through the first substrate (100) and filed with a conductive material, the electrode hole (9) of the infrared detection element (1) is electrically connected to the electrode of the readout circuit (2) via the conductive material filled in the silicon via (8).

Abstract: A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.

Abstract: A method of preventing microcavity formation in a bonding layer of a composite structure resulting from creep and thermal expansion due to high temperature exposure of the composite structure. The method includes the steps of providing a thin film with a thickness of 5 micrometers or less; providing a bonding layer of oxide with a thickness that is equal to or greater than the thickness of the thin film with the bonding layer formed by low pressure chemical vapor deposition. The thin film or support substrate have a mean thermal expansion coefficient of 7×10?6 K?1 or more. The thin film, bonding layer and support substrate combine to reduce stress in and plastic deformation of the bonding layer during exposure to high temperatures of more than approximately 900° C. to thus prevent microcavities from appearing in the bonding layer.

Abstract: A method of forming a Ga2O3-based crystal film includes epitaxially growing a Ga2O3-based crystal film on a (001)-oriented principal surface of a Ga2O3-based substrate at a growth temperature of not less than 750° C. A crystal multilayer structure includes a Ga2O3-based substrate with a (001)-oriented principal surface, and a Ga2O3-based crystal film formed on the principal surface of the Ga2O3-based substrate by epitaxial growth. The principal surface has a flatness of not more than 1 nm in an RMS value.

Abstract: An object is to improve water resistance and reliability of a semiconductor device by reducing the degree of peeling of a film. In a semiconductor device, a first inorganic insulating layer, a semiconductor element layer, a second inorganic insulating layer, an organic insulating layer, and a third inorganic insulating layer are sequentially stacked over a substrate. The second inorganic insulating layer is in contact with the first inorganic insulating layer in an opening portion provided in the semiconductor element layer. The third inorganic insulating layer is in contact with the second inorganic insulating layer in an opening portion provided in the organic insulating layer. In a region where the second inorganic insulating layer and the third inorganic insulating layer are in contact with each other, the second inorganic insulating layer has a plurality of irregularities or openings.

Abstract: An active device substrate includes a flexible substrate, an inorganic de-bonding layer, and at least one active device. The flexible substrate has a first surface and a second surface opposite to the first surface, wherein the first surface is a flat surface. The inorganic de-bonding layer covers the first surface of the flexible substrate, and the material of the inorganic de-bonding layer is metal, metal oxide or combination thereof. The active device is disposed on or above the second surface of the flexible substrate.

Abstract: Provided is a photodiode having a high-concentration layer on its surface, in which the high-concentration layer is formed so that the thickness of a non-depleted region is larger than the roughness of an interface between silicon and an insulator layer, and is smaller than a penetration depth of ultraviolet light.

Abstract: Methods and systems are provided for the split and separation of a layer of desired thickness of crystalline semiconductor material containing optical, photovoltaic, electronic, micro-electro-mechanical system (MEMS), or optoelectronic devices, from a thicker donor wafer using laser irradiation.

Abstract: A method of forming a semiconductor structure includes forming a multilayer lattice matched structure having an unstrained layer, a first strained layer, and a second strained layer formed between the unstrained and the first strained layer. A first opening in the multilayer structure is etched and a second strained fill material having a same material as the second strained layer is deposited. A second opening in the multilayer structure is etched and an unstrained fill material having a same material as the unstrained layer is deposited. A first strained fill material having a same material as the first strained layer is then deposited between the unstrained fill and the second strained fill. A second strained fin is formed from the deposited second strained fill material, a first strained fin is formed from the deposited first strained fill material, and an unstrained fin is formed from the deposited unstrained fill material.

Abstract: A package system includes a first integrated circuit disposed over an interposer. The interposer includes at least one molding compound layer including a plurality of electrical connection structures through the at least one molding compound layer. A first interconnect structure is disposed over a first surface of the at least one molding compound layer and electrically coupled with the plurality of electrical connection structures. The first integrated circuit is electrically coupled with the first interconnect structure.

Abstract: A method for transferring nanostructures includes providing a growth substrate and a number of nanostructures located on the growth substrate. The nanostructures are transferred by an adhesive layer from the growth substrate to a target substrate. The nanostructures are between the target substrate and the adhesive layer, and at least partial of nanostructures is in contact with a surface of the target substrate. The adhesive layer is covered by a metal layer. The adhesive layer together with the metal layer is separated from the plurality of nanostructures and the target substrate in an organic solvent, wherein the organic solvent permeates into an interface between the adhesive layer and the nanostructures.

Abstract: A method relates to separating a component composite into a plurality of component regions, wherein the component composite is provided having a semiconductor layer sequence comprising a region for generating or for receiving electromagnetic radiation. The component composite is mounted on a rigid subcarrier. The component composite is separated into the plurality of component regions, wherein one semiconductor body is produced from the semiconductor layer sequence for each component region. The component regions are removed from the subcarrier.

Abstract: An organic electroluminescent display device includes a first electrode on a substrate, an organic layer including a light-emitting layer on the first electrode, a second electrode including lower and upper conductive layers sequentially stacked on the organic layer, and an insulating pattern extending into the organic layer through the lower conductive layer.

Abstract: In a method for fabricating a field effect transistor, a first source/drain region and a second source/drain region are formed in a substrate. A channel region is formed between the first source/drain region and the second source/drain region. A gate region is formed on the channel region. Micro-cavities are formed in the substrate at least below the channel region, and the micro-cavities are oxidized.

Abstract: Provided is a method of manufacturing a nitride semiconductor device. The method includes forming a plurality of electrodes on a growth substrate on which first and second nitride semiconductor layers are sequentially stacked, forming upper metal layers on the plurality of electrodes respectively, removing the growth substrate to expose a lower surface of the first nitride semiconductor layer, and forming a third nitride semiconductor layer and a lower metal layer sequentially on the exposed lower surface of the first nitride semiconductor layer.

Abstract: An objective of the present invention is to increase production efficiency of high-performance flexible semiconductor devices. A semiconductor device manufacturing method includes: a step of forming an insulating substrate (10) which is configured of glass substrates (11, 13) with a thermal expansion coefficient which approximates the thermal expansion coefficient of a single-crystal silicon substrate (20) and a plastic substrate (12) which is positioned between both of the glass substrates; and a step of, after bonding the insulating substrate (10) with the single-crystal silicon substrate (20), separating a portion of the single-crystal silicon substrate (20) with heat processing, and forming a single-crystal silicon layer (14) upon the glass substrate (11).

Abstract: A method for transferring nanostructures includes providing a growth substrate and a number of nanostructures located on the growth substrate. The nanostructures are transferred by an adhesive layer from the growth substrate to a target substrate. The nanostructures are between the target substrate and the adhesive layer, and at least partial of nanostructures is in contact with a surface of the target substrate. The adhesive layer is covered by a metal layer. The adhesive layer together with the metal layer is separated from the nanostructures and the target substrate in an organic solvent by an external force, wherein the organic solvent permeates into an interface between the adhesive layer and the nanostructures.

Abstract: Spalling is employed to generate a single crystalline semiconductor layer. Complementary metal oxide semiconductor (CMOS) logic and memory devices are formed on a single crystalline semiconductor substrate prior to spalling. Organic light emitting diode (OLED) driving circuitry, solar cells, sensors, batteries and the like can be formed prior to, or after, spalling. The spalled single crystalline semiconductor layer can be transferred to a substrate. OLED displays can be formed into the spalled single crystalline semiconductor layer to achieve a structure including an OLED display with semiconductor driving circuitry and other functions integrated on the single crystalline semiconductor layer.

Abstract: The object of the invention is to provide a method for fabricating a semiconductor device having a peeled layer bonded to a base material with curvature. Particularly, the object is to provide a method for fabricating a display with curvature, more specifically, a light emitting device having an OLED bonded to a base material with curvature. An external force is applied to a support originally having curvature and elasticity, and the support is bonded to a peeled layer formed over a substrate. Then, when the substrate is peeled, the support returns into the original shape by the restoring force, and the peeled layer as well is curved along the shape of the support. Finally, a transfer object originally having curvature is bonded to the peeled layer, and then a device with a desired curvature is completed.

Abstract: Various embodiments of semiconductor manufacturing methods include releasing a transparent carrier from a semiconductor wafer assembly that includes a semiconductor wafer in which a plurality of semiconductor devices are formed, an adhesive layer coupled to the semiconductor wafer, a carrier release layer coupled to the adhesive layer, and the transparent carrier coupled to the carrier release layer. The method further includes controlling a laser system to emit a first beam characterized by first laser parameters toward the adhesive layer, where the first laser parameters are selected so that the first beam will compromise a physical integrity of the adhesive layer. The method further includes, after controlling the laser system to emit the first beam toward the adhesive layer, removing the adhesive layer from the semiconductor wafer.

Abstract: An SOI substrate and a manufacturing method of the SOI substrate, by which enlargement of the substrate is possible and its productivity can be increased, are provided. A step (A) of cutting a first single crystal silicon substrate to form a second single crystal silicon substrate which has a chip size; a step (B) of forming an insulating layer on one surface of the second single crystal silicon substrate, and forming an embrittlement layer in the second single crystal substrate; and a step (C) of bonding a substrate having an insulating surface and the second single crystal silicon substrate with the insulating layer therebetween, and conducting heat treatment to separate the second single crystal silicon substrate along the embrittlement layer, and forming a single crystal silicon thin film on the substrate having an insulating surface, are conducted.

Abstract: A method for forming nanostructures includes bonding a flexible substrate to a crystalline semiconductor layer having a two-dimensional material formed on a side opposite the flexible substrate. The crystalline semiconductor layer is stressed in a first direction to initiate first cracks in the crystalline semiconductor layer. The first cracks are propagated through the crystalline semiconductor layer and through the two-dimensional material. The stress of the crystalline semiconductor layer is released to provide parallel structures including the two-dimensional material on the crystalline semiconductor layer.

Abstract: The present invention is directed to a method for manufacturing an SOI wafer in which the bonded SOI wafer after the delamination by the ion implantation delamination method is subjected to a rapid thermal oxidation process such that an oxide film is formed on a surface of the SOI layer, the oxide film is removed, the bonded SOI wafer is then subjected to a flattening heat treatment to flatten the surface of the SOI layer, the flattening heat treatment causing migration of silicon atoms of the surface of the SOI layer, and the bonded SOI wafer is then subjected to a sacrificial oxidation process to adjust a film thickness of the SOI layer. The method enables efficient manufacture of a high quality SOI wafer having an SOI layer with sufficiently reduced surface roughness of the SOI layer surface and fewer deep pits in the SOI layer surface.

Abstract: A semiconductor structure includes a III-V monocrystalline layer and a germanium surface layer. An interlayer is formed directly between the III-V monocrystalline layer and the germanium surface layer from a material selected to provide stronger nucleation bonding between the interlayer and the germanium surface layer than nucleation bonding that would be achievable directly between the III-V monocrystalline layer and the germanium surface layer such that a continuous, relatively defect-free germanium surface layer is provided.

Abstract: The invention relates to a process for thinning the active silicon layer of a substrate, which comprises an insulator layer between the active layer and a support, this process comprising one step of sacrificial thinning of active layer by formation of a sacrificial oxide layer by sacrificial thermal oxidation and deoxidation of the sacrificial oxide layer. The process is noteworthy in that it comprises: a step of forming a complementary oxide layer on the active layer, using an oxidizing plasma, this layer having a thickness profile complementary to that of oxide layer, so that the sum of the thicknesses of the oxide layer and of the sacrificial silicon oxide layer are constant over the surface of the treated substrate, a step of deoxidation of this oxide layer, so as to thin active layer by a uniform thickness.

Abstract: Transfer of nanoscale elements from a substrate on which they were manufactured or transferred to a flexible sheet may be performed by local and progressive deformation of the flexible sheet over the surface of the substrate to attach and lift the nanoscale elements from the substrate with controlled inter-element registration.

Abstract: A method of processing a device wafer in a wafer stack by chucking the wafer stack device side down and grinding the exposed side of the carrier wafer to parallel with the device wafer, and thereafter flipping the wafer stack and chucking the wafer stack carrier side down and grinding residual silicon from the device wafer.

Abstract: An optoelectronic semiconductor device includes an optoelectronic semiconductor layer sequence on a metal carrier element, which includes as a first component silver and as a second component a material having a lower coefficient of thermal expansion than silver, wherein the first and second components are intermixed in the metal carrier element.

Abstract: Embodiments of the invention are provided for a thin film stack containing a plurality of epitaxial stacks disposed on a substrate and a method for forming such a thin film stack. In one embodiment, the epitaxial stack contains a first sacrificial layer disposed over the substrate, a first epitaxial film disposed over the first sacrificial layer, a second sacrificial layer disposed over the first epitaxial film, and a second epitaxial film disposed over the second sacrificial layer. The thin film stack may further contain additional epitaxial films disposed over sacrificial layers. Generally, the epitaxial films contain gallium arsenide alloys and the sacrificial layers contain aluminum arsenide alloys. Methods provide the removal of the epitaxial films from the substrate by etching away the sacrificial layers during an epitaxial lift off (ELO) process. The epitaxial films are useful as photovoltaic cells, laser diodes, or other devices or materials.

Abstract: To avoid problems of hydrolysis of the silicon oxide formed by PECVD at the surface of at least one wafer, it is proposed to cover, in the vacuum deposition chamber used to deposit the silicon oxide, said oxide with a temporary protective layer containing nitrogen. The protective layer thus protects the silicon oxide against the outer environment and especially against humidity when the wafer provided with the silicon oxide is stored outside of the vacuum deposition chamber. Afterwards, the protective layer is removed, for example, by chemical-mechanical. polishing, just before the two wafers are placed into contact. The protective layer may be formed by a PECVD silicon nitride deposition, by plasma nitriding or nitrogen doping of a superficial portion of the silicon oxide.

Abstract: There is disclosed a method for manufacturing an SOI wafer comprising: a step of implanting at least one of a hydrogen ion and a rare gas ion into a donor wafer to form an ion implanted layer; a step of bonding an ion implanted surface of the donor wafer to a handle wafer; a step of delaminating the donor wafer at the ion implanted layer to reduce a film thickness of the donor wafer, thereby providing an SOI layer; and a step of etching the SOI layer to reduce a thickness of the SOI layer, wherein the etching step includes: a stage of performing rough etching as wet etching; a stage of measuring a film thickness distribution of the SOI layer after the rough etching; and a stage of performing precise etching as dry etching based on the measured film thickness distribution of the SOI layer. There can be provided A method for manufacturing an SOI wafer having high film thickness uniformity of an SOI layer with excellent productivity.

Abstract: A method of transferring graphene includes forming a sacrificial layer and a graphene layer sequentially on a first substrate, bonding the graphene layer to a target layer, and removing the sacrificial layer using a laser and separating the first substrate from the graphene layer.

Abstract: A method for forming nanostructures includes bonding a flexible substrate to a crystalline semiconductor layer having a two-dimensional material formed on a side opposite the flexible substrate. The crystalline semiconductor layer is stressed in a first direction to initiate first cracks in the crystalline semiconductor layer. The first cracks are propagated through the crystalline semiconductor layer and through the two-dimensional material. The stress of the crystalline semiconductor layer is released to provide parallel structures including the two-dimensional material on the crystalline semiconductor layer.

Abstract: Method and Apparatus so configured for the fabrication of three-dimensional integrated devices. A crystalline substrate within an area of a donor semiconductor wafer is etched. The substrate side is located opposite a device layer and has a buried insulating layer and a substrate thickness. The etching removes at least a substantial portion of the crystalline substrate within the area such that the device layer and the buried insulating layer in the area is to conform to a pattern specific topology on an acceptor surface. The donor semiconductor wafer is supported with a supporting structure that allows the donor semiconductor wafer to flexibly conform to the pattern specific topology within at least a portion of the area after the etching to enable conformality and reliable bonding to the device surfaces of an acceptor wafer to form a three dimensional integrated device.

Abstract: Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. A step is performed to selectively etch through the semiconductor active layer and the sacrificial layer in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. A step can be performed to selectively etch through the capping layer and the first portion of the semiconductor active layer to thereby expose the sacrificial layer.

Abstract: A method for the formation of an at least partially relaxed strained material layer, comprises providing a seed substrate; patterning the seed substrate; growing a strained material layer on the patterned seed substrate; transferring the strained material layer from the patterned seed substrate to an intermediate substrate; and at least partially relaxing the strained material layer by a heat treatment.