Abstract: A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form division grooves in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of cooling the polyester sheet in each region of the polyester sheet corresponding to each device chip, pushing up each device chip from the polyester sheet side to pick up each device chip from the polyester sheet.

Abstract: A wafer processing method includes a polyolefin sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyolefin sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyolefin sheet as applying a pressure to the polyolefin sheet to thereby unite the wafer and the ring frame through the polyolefin sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form division grooves in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of applying an ultrasonic wave to the polyolefin sheet in each region of the polyolefin sheet corresponding to each device chip, pushing up each device chip from the polyolefin sheet side to pick up each device chip from the polyolefin sheet.

Abstract: A wafer processing method includes a polyolefin sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyolefin sheet on a back side or a front side of the wafer and on a back side of the ring frame, a uniting step of heating the polyolefin sheet as applying a pressure to the polyolefin sheet to thereby unite the wafer and the ring frame through the polyolefin sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form modified layers in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of picking up each device chip from the polyolefin sheet.

Abstract: A wafer processing method includes a polyolefin sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyolefin sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyolefin sheet as applying a pressure to the polyolefin sheet to thereby unite the wafer and the ring frame through the polyolefin sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form division grooves in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of cooling the polyolefin sheet in each region of the polyolefin sheet corresponding to each device chip, pushing up each device chip from the polyolefin sheet side to pick up each device chip from the polyolefin sheet.

Abstract: A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form division grooves in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of picking up each device chip from the polyester sheet.

Abstract: A wafer processing method includes a polyolefin sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyolefin sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyolefin sheet as applying a pressure to the polyolefin sheet to thereby unite the wafer and the ring frame through the polyolefin sheet by thermocompression bonding, a dividing step of cutting the wafer by using a cutting apparatus to thereby divide the wafer into individual device chips, and a pickup step of applying an ultrasonic wave to the polyolefin sheet, pushing up each device chip through the polyolefin sheet, and then picking up each device chip from the polyolefin sheet.

Abstract: A back surface of a wafer is formed with a ring-shaped projecting portion. The wafer is cut with a blade from a side of a front surface of the wafer in a state where the projecting portion of the wafer with a back surface facing upward is supported.

Abstract: Disclosed herein are techniques for improving performance of micro light emitting diodes. According to certain embodiments, a semi-polar-oriented light emitting diode (LED) (e.g., grown on (2021) plane or (1122) plane) includes a buried p-GaN layer that is grown before the active region and the n-GaN layer of the LED are grown, such that the polarization-induced (including strain-induced piezoelectric polarization and spontaneous polarization) electrical field and the built-in depletion field in the active region are in opposite directions during normal operations, thereby reducing or minimizing the overall internal electric field that can contribute to Quantum-Confined Stark Effect. The buried p-GaN layer is grown on an n-i-n sacrificial etch junction, which can be laterally wet-etched to separate the semi-polar-oriented LED from the underlying substrate and expose the p-GaN layer for planar or vertical (rather than horizontal or lateral) activation.

Abstract: An optical device wafer processing method for transferring an optical device layer of an optical device wafer onto a transfer member includes: a dividing groove forming step of forming dividing grooves in a buffer layer; a transfer member joining step of joining the transfer member to a front surface of the optical device layer; and a laser beam applying step of applying a pulsed laser beam from a back surface side of a crystalline substrate. In the laser beam applying step, the buffer layer, or the buffer layer and part of the optical device layer, left without being divided in the dividing groove forming step, are modified in nature.

Abstract: A semiconductor wafer and a semiconductor wafer fabrication method are provided. The wafer includes a supporting substrate, a semiconductor substrate and a contact layer. The supporting substrate has a first surface and a second surface opposite to the first surface. The semiconductor substrate is disposed on the first surface of the supporting substrate, in which the semiconductor substrate is configured to form plural devices. The contact layer is disposed on the second surface of the supporting substrate to contact the supporting substrate, in which the contact layer is configured to contact an electrostatic chuck and has a resistivity of the contact layer smaller than a resistivity of the supporting substrate. In semiconductor wafer fabrication method, at first, a raw wafer is provided. Then, the contact layer is formed by using an implantation operation or a deposition operation.

Abstract: A method for fabricating a flexible display substrate is provided. The method includes: forming a separation structure on a rigid substrate such that the separation structure includes a first separation layer and a second separation layer; forming a flexible substrate on the separation structure; forming a display element on the flexible substrate; and separating the first separation layer and the second separation layer of the separation structure mechanically to separate the rigid substrate from the flexible substrate.

Abstract: A front-side type image sensor includes a substrate successively comprising a P? type doped semiconducting support substrate, an electrically insulating layer and a semiconducting active layer, and a matrix array of photodiodes in the active layer of the substrate, wherein the substrate comprises, between the support substrate and the electrically insulating layer, a P+ type doped semiconducting epitaxial layer A method of forming such a structure includes epitaxially growing a P+ type doped semiconducting layer on a P? type doped semiconducting support substrate, providing an electrically insulating layer and an active layer over the P+ type doped semiconducting layer, and forming photodiodes in the active layer.

Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor layer on the semiconductor substrate and having an exposed portion of a lower surface, a capping layer on the first semiconductor layer, a second semiconductor layer below the capping layer and having a side surface substantially in full contact with the capping layer, a cavity defined by the first semiconductor layer, the second semiconductor layer, and the capping layer, and a through-hole passing through the capping layer and the second semiconductor layer and extending to the cavity.

Abstract: A method for direct growth of a patterned transition metal dichalcogenide monolayer, the method including the steps of providing a substrate covered by a mask, the mask having a pattern defined by one or more shaped voids; thermally depositing a salt on the substrate through the one or more shaped voids such that a deposited salt is provided on the substrate in the pattern of the mask; and thermally co-depositing a transition metal oxide and a chalcogen onto the deposited salt to form the patterned transition metal dichalcogenide monolayer having the pattern of the mask. Also provided is a patterned transition metal dichalcogenide monolayer prepared according to the method.

Abstract: A method for fabricating silicon-on-insulator (SOI) semiconductor devices, wherein the piezoresistive pattern is defined within a blanket doped layer after fusion bonding. This new method of fabricating SOI semiconductor devices is more suitable for simpler large scale fabrication as it provides the flexibility to select the device pattern/type at the latest stages of fabrication.

Abstract: The present invention provides a substrate holding member comprising: a first holding member; a second holding member that cooperates with the first holding member to hold the substrate therebetween; and a transparent portion provided in at least one of the first and second holding members.

Abstract: A method of forming a device includes providing a first substrate having a first area and a second area, forming a range compensating material over the first substrate so that the first material is disposed over the first area and not disposed over the second area, implanting ions into the first area and the second area to form first and second cleave planes at first and second depths, respectively, each of the first and second cleave planes being defined by a concentration of the implanted ions, removing the range compensating material, and cleaving the first substrate along a cleave profile including the first and second cleave planes.

Abstract: An integrated fan-out package including an integrated circuit, a plurality of memory devices, an insulating encapsulation, and a redistribution circuit structure is provided. The memory devices are electrically connected to the integrated circuit. The integrated circuit and the memory devices are stacked, and the memory devices are embedded in the insulating encapsulation. The redistribution circuit structure is disposed on the insulating encapsulation, and the redistribution circuit structure is electrically connected to the integrated circuit and the memory devices. Furthermore, methods for fabricating the integrated fan-out package are also provided.

Abstract: A graphene-based layer transfer (GBLT) technique is disclosed. In this approach, a device layer including a III-V semiconductor, Si, Ge, III-N semiconductor, SiC, SiGe, or II-VI semiconductor is fabricated on a graphene layer, which in turn is disposed on a substrate. The graphene layer or the substrate can be lattice-matched with the device layer to reduce defect in the device layer. The fabricated device layer is then removed from the substrate via, for example, a stressor attached to the device layer. In GBLT, the graphene layer serves as a reusable and universal platform for growing device layers and also serves a release layer that allows fast, precise, and repeatable release at the graphene surface.

Abstract: A lateral bipolar junction transistor (LBJT) device that may include a dielectric stack including a pedestal of a base region passivating dielectric and a nucleation dielectric layer; and a base region composed of a germanium containing material or a type III-V semiconductor material in contact with the pedestal of the base region passivating dielectric. An emitter region and collector region may be present on opposing sides of the base region contacting a sidewall of the pedestal of the base region passivating dielectric and an upper surface of the nucleation dielectric layer.

Abstract: A method of processing a substrate, having a first surface with at least one division line formed thereon and a second surface opposite the first surface, includes applying a pulsed laser beam to the substrate from the side of the first surface, at least in a plurality of positions along the at least one division line, so as to form a plurality of modified regions in the substrate, each modified region extending at least from the first surface towards the second surface. Each modified region is formed by melting substrate material by means of the pulsed laser beam and allowing the molten substrate material to resolidify. The method further comprises removing substrate material along the at least one division line where the plurality of modified regions has been formed.

Abstract: A method of dicing a semiconductor wafer may include forming a porous silicon layer along an outline of dies singulated from the semiconductor wafer. The method may include sealing an active surface of the semiconductor wafer, including the porous silicon layer. The method may further include back grinding a rear surface of the semiconductor wafer to expose the porous silicon layer along the outline of the dies. The method also includes etching the semiconductor wafer to release the dies.

Abstract: The present invention relates to a method for separating solid-body slices (1) from a donor substrate (2). The method comprises the steps of: producing modifications (10) within the donor substrate (2) by means of laser beams (12), wherein a detachment region is predefined by the modifications (10), along which detachment region the solid-body layer (1) is separated from the donor substrate (2), and removing material from the donor substrate (2), starting from a surface (4) extending in the peripheral direction of the donor substrate (2), in the direction of the centre (Z) of the donor substrate (2), in particular in order to produce a peripheral indentation (6).

Abstract: In a described example, a method includes: forming stress induced dislocations along scribe lanes between semiconductor dies on a semiconductor wafer using a laser; mounting a first side of the semiconductor wafer on the first side of a first dicing tape; removing a backgrinding tape from the semiconductor wafer; attaching a second dicing tape to a second side of the semiconductor wafer opposite the first side, the second dicing tape adhering to portions of the first dicing tape that are spaced from the semiconductor wafer, forming a dual taped wafer dicing assembly; separating the semiconductor dies by stretching the first dicing tape and stretching the second dicing tape; removing the second dicing tape from the semiconductor dies; and removing the semiconductor dies from the first dicing tape.

Abstract: A method for preparing an SOI wafer by using rapid thermal processing includes: taking a silicon wafer as a raw material, sequentially performing process steps of oxidation, H+ implantation and bonding to obtain a bonded wafer with an H+ implantation layer; and then splitting the bonded wafer by using rapid thermal processing and microwaves to obtain a required SOI wafer. In the present invention, an SOI film after wafer splitting has better thickness uniformity and lower roughness. The present invention may improve lattice damage after implantation and reduce SOI surface defects after wafer splitting and thus improve the SOI surface quality. The present invention is high in wafer-splitting speed and thus reduces silicon wafer contamination. The present invention has high efficiency and an excellent comprehensive technical effect.

Abstract: A mirror and method of fabricating the mirror, the method comprising: providing a silicon-on-insulator substrate, the substrate comprising: a silicon support layer; a buried oxide (BOX) layer on top of the silicon support layer; and a silicon device layer on top of the BOX layer; creating a via in the silicon device layer, the via extending to the BOX layer; etching away a portion of the BOX layer starting at the via and extending laterally away from the via in a first direction to create a channel between the silicon device layer and silicon support layer; applying an anisotropic etch via the channel to regions of the silicon device layer and silicon support layer adjacent to the channel; the anisotropic etch following an orientation plane of the silicon device layer and silicon support layer to create a cavity underneath an overhanging portion of the silicon device layer; the overhanging portion defining a planar underside surface for vertically coupling light into and out of the silicon device layer; and a

Abstract: A method is disclosed that includes operations as follows. With an ion-implanted layer which is disposed between an epitaxial layer and a first semiconductor substrate, the epitaxial layer is bonded directly to a second semiconductor substrate. The ion-implanted layer is split to separate the first semiconductor substrate from the epitaxial layer completely.

Abstract: A method of manufacturing a light-emitting element includes: providing a wafer including: a substrate, and a semiconductor structure; forming a plurality of modified regions inside the substrate of the wafer by irradiating the substrate with a laser beam; and separating the wafer into a plurality of light-emitting elements after said irradiating the substrate with the laser beam. Said forming the plurality of modified regions includes: scanning the laser beam along a plurality of first lines, the plurality of first lines extending in a first direction and being arranged in a second direction, the first direction being parallel to the first surface, the second direction intersecting the first direction and being parallel to the first surface, and scanning the laser beam along a plurality of second lines, the plurality of second lines extending in the second direction and being arranged in the first direction.

Abstract: Techniques for use of wafer bonding techniques for sealing of microfluidic chips are provided. In one aspect, a wafer bonding sealing method includes the steps of: forming a first oxide layer coating surfaces of a first wafer, the first wafer having at least one fluidic chip; forming a second oxide layer on a second wafer; and bonding the first wafer to the second wafer via an oxide-to-oxide bond between the first oxide layer and the second oxide layer to form a bonded wafer pair, wherein the second oxide layer seals the at least one fluidic chip on the first wafer. The second wafer can be at least partially removed after performing the bonding, and fluidic ports may be formed in the second oxide layer. A fluidic chip device is also provided.

Abstract: A wafer-to-wafer semiconductor device includes a first wafer substrate having a first bonding layer formed on a first bulk substrate layer. A second wafer substrate includes a second bonding layer formed on a second bulk substrate layer. The second bonding layer is bonded to the first bonding layer to define a bonding interface. At least one of the first wafer substrate and the second wafer substrate includes a crack-arresting film layer configured to increase a bonding energy of the bonding interface.

Abstract: A method for manufacturing a bonded SOI wafer including a step of performing a heat treatment to each bonded SOI wafer having an oxide film on a back surface thereof in an argon atmosphere to flatten a front surface of an SOI layer, wherein, at the time of performing the heat treatment in the argon atmosphere in a batch processing heat treatment furnace, a silicon wafer is arranged as a dummy wafer between the adjacent bonded SOI wafers housed in the batch processing heat treatment furnace to perform the heat treatment. Consequently, there is the method for manufacturing an SOI wafer which enables suppressing an increase in LPDs at the step of performing the heat treatment to a bonded SOI wafer having an oxide film on a back surface thereof in an argon atmosphere in a batch processing heat treatment furnace to flatten a front surface of an SOI layer.

Abstract: A method of manufacturing an optical component for an optical semiconductor includes: providing a joined body including: a first member having light transmissivity and containing at least one element selected from the group consisting of oxygen, fluorine, and nitrogen, and a second member, wherein the first member and the second member are joined together via a metal joining member made by directly bonding a first metal film formed on the first member and a second metal film formed on the second member; and irradiating the joining member with a laser beam or a microwave.

Abstract: Various embodiments process semiconductor devices. In one embodiment, a release layer is applied to a handler. The release layer comprises at least one additive that adjusts a frequency of electro-magnetic radiation absorption property of the release layer. The additive comprises, for example, a 355 nm chemical absorber and/or chemical absorber for one of more wavelengths in a range comprising 600 nm to 740 nm. The at least one singulated semiconductor device is bonded to the handler. The at least one singulated semiconductor device is packaged while it is bonded to the handler. The release layer is ablated by irradiating the release layer through the handler with a laser. The the at least one singulated semiconductor device is removed from the transparent handler after the release layer has been ablated.

Abstract: A transistor whose channel region includes an oxide semiconductor is used as a pull down transistor. The band gap of the oxide semiconductor is 2.0 eV or more, preferably 2.5 eV or more, more preferably 3.0 eV or more. Thus, hot carrier degradation in the transistor can be suppressed. Accordingly, the circuit size of the semiconductor device including the pull down transistor can be made small. Further, a gate of a pull up transistor is made to be in a floating state by switching of on/off of the transistor whose channel region includes an oxide semiconductor. Note that when the oxide semiconductor is highly purified, the off-state current of the transistor can be 1 aA/?m (1×10?18 A/?m) or less. Therefore, the drive capability of the semiconductor device can be improved.

Abstract: A heterogeneous semiconductor structure, including a first integrated circuit and a second integrated circuit, the second integrated circuit being a photonic integrated circuit. The heterogeneous semiconductor structure may be fabricated by bonding a multi-layer source die, in a flip-chip manner, to the first integrated circuit, removing the substrate of the source die, and fabricating one or more components on the source die, using etch and/or deposition processes, to form the second integrated circuit. The second integrated circuit may include components fabricated from cubic phase gallium nitride compounds, and configured to operate at wavelengths shorter than 450 nm.

Abstract: A method includes steps of (a) forming a substrate layer 10 above a support substrate 8 which is transparent, and then a thin-film element above the substrate layer 10; and (b) emitting laser beams La and Lb to a face of the support substrate 8 opposite to another face of the support substrate to which the substrate layer 10 and the thin-film element are formed, and delaminating the substrate layer 10 and the thin-film element from the support substrate 8. In step (b), the laser beams La and Lb are emitted from different directions.

Abstract: According to a flexible OLED device production method of the present disclosure, after an intermediate region (30i) and flexible substrate regions (30d) of a plastic film (30) of a multilayer stack (100) are divided from one another, the interface between the flexible substrate regions (30d) and a glass base (10) is irradiated with laser light. The multilayer stack (100) is separated into a first portion (110) and a second portion (120) while the multilayer stack (100) is in contact with a stage (210). The first portion (110) includes a plurality of OLED devices (1000) which are in contact with the stage (210). The OLED devices (1000) include a plurality of functional layer regions (20) and the flexible substrate regions (30d). The second portion (120) includes the glass base (10) and the intermediate region (30i).

Abstract: Method for manufacturing bonded SOI wafer by bonding bond wafer and base wafer each composed of silicon single crystal with insulator film being interposed therebetween, including steps of: depositing polycrystalline silicon layer on bonding surface side of base wafer; polishing surface of polycrystalline silicon layer to obtain polished surface; forming thermal oxide film on polished surface; forming insulator film on bonding surface of bond wafer; bonding step of bonding bond and base wafers by bringing insulator and oxide films into close contact with each other; and thinning bonded bond wafer to form SOI layer, wherein silicon single crystal wafer having resistivity of 100 ?·cm or more is used as base wafer, thermal oxide film formed on polished surface has thickness of 15 nm or more with RMS of 0.6 nm or less, and any heat treatment after bonding step is performed with maximum treatment temperature of 1150° C. or less.

Abstract: A method for producing a plurality of components and a component are disclosed. In an embodiment the method includes providing a carrier composite comprising a base body and a planar connecting surface, providing a wafer composite comprising a semiconductor body composite and a planar contact surface, connecting the wafer composite to the carrier composite thereby forming a joint composite so that the planar contact surface and the planar connecting surface are joined forming a joint boundary surface. The method further includes reducing inner mechanical stress in the joint composite so that a material of the carrier composite is removed in places, wherein the joint composite is thermally treated in order to form a permanent mechanically-stable connection between the wafer composite and the carrier composite, and wherein reducing inner stress is effected prior to the thermal treatment.

Abstract: A method is provided for preparing a high resistivity silicon handle substrate for use in semiconductor-on-insulator structure. The handle substrate is prepared to comprise thermally stable charge carrier traps in the region of the substrate that will be at or near the buried oxide layer (BOX) of the final semiconductor-on-insulator structure. The handle substrate comprising the stable carrier traps is manufactured by hydrogen ions implantation occurring using at least two different energies, followed by a 2-step thermal treatment. The thermally stable defect structures prepared thereby is stable to anneal at temperatures of at least 1180° C. The defect structure comprises 3-dimensional network of nano-cavities interconnected by dislocations. This wafer can be used as a handle wafer for fabricating silicon-on-insulator (SOI) wafers and further fabricating radio frequency (RF) semiconductor devices.

Abstract: A semiconductor film, a sheet like object, and a semiconductor device are provided that have inhibited semiconductor properties, particularly leakage current, and excellent withstand voltage and heat dissipation. A crystalline semiconductor film or a sheet like object includes a corundum structured oxide semiconductor as a major component, wherein the film has a film thickness of 1 ?m or more. Particularly, the semiconductor film or the object includes a semiconductor component of oxide of one or more selected from gallium, indium, and aluminum as a major component. A semiconductor device has a semiconductor structure including the semiconductor film or the object.

Abstract: A sheet transfer apparatus and a method for transferring a sheet using a sheet transfer apparatus are provided. A sheet transfer apparatus includes: a table on which two or more sheets, which are continuously laminated, are configured to be seated; a sheet adsorbing part on the table to adsorb a first sheet, which is at an uppermost portion, of the two or more laminated sheets at a pressure; and an air discharge part on the table and adjacent to the sheet adsorbing part, and the air discharge part is configured to discharge air to a surface of the first sheet adsorbed to the sheet adsorbing part.

Abstract: In a method in which a workpiece, while being temporarily fixed on a support via a temporary fixing material, is processed and/or transported and thereafter the support and the workpiece are separated from each other by an irradiation separation method, a technique is shown which prevents the photo-degradation of the workpiece. A workpiece treating method includes a step of forming a stack including a support, a temporary fixing material and a workpiece wherein the temporary fixing material includes a layer (I) that contains a polymer (A) including a structural unit (A1); a step of processing the workpiece and/or transporting the stack; a step of applying light to the layer (I) through the support; and a step of separating the support and the workpiece from each other.

Abstract: Embodiments relate to transferring dies or other electronic components from a carrier substrate to a target substrate of a device as part of chip assembly for the device. Bonding material is applied to selected dies on a carrier substrate by direct boning, or to corresponding die transfer locations on a target substrate. The carrier substrate is then brought into contact with the target substrate to transfer each of the selected dies to the carrier substrate. Dies can also be directly bonded to the target substrate even in the presence of other die in situ (e.g., from a previous bonding cycle), hence, enables more than one direct bond cycle to be carried out for a target substrate. As such, multi-color (RGB) display elements can be assembled in stages (e.g., separate bonding cycles) in a flexible manner to provide redundancy or to replace inoperative LED dies.

Abstract: Implementations of a method of singulating a plurality of die may include: providing a semiconductor wafer including a plurality of die located on a first side of the semiconductor wafer where the plurality of die include a desired thickness. The method may include etching a plurality of trenches into the semiconductor wafer only from the first side of the semiconductor wafer where the plurality of trenches is located adjacent to a perimeter of the plurality of die. A depth of the plurality of trenches may be greater than the desired thickness of the plurality of die. The method may also include mounting the first side of the semiconductor wafer to a backgrinding tape. The method may also include thinning a second side of the semiconductor wafer to a predetermined distance to the depth of the plurality of trenches to singulate the plurality of die.

Abstract: An electronic device may have components such as a display, a camera, a button, and other electrical components. A transparent crystalline member such as a layer of aluminum oxide, zirconium oxide, or other crystalline dielectric structure may overlap an electrical component and may serve as a display cover layer, button cover member, or window member. An annealed adhesion layer such as an annealed inorganic layer may be formed on a crystalline dielectric member. The annealed adhesion layer may help adhere an oleophobic coating to the transparent crystalline member.

Abstract: The present disclosure discloses in embodiments a thin film transistor and a manufacturing method thereof, an array substrate. The thin film transistor comprises: a base substrate, an active layer, a source, a gate, and a drain. Two ends of the active layer are connected to the source and the drain, respectively. The gate comprises a top gate and a bottom gate arranged opposite to each other in a direction perpendicular to the base substrate, the top gate comprising a top gate top portion and a top gate side portion connected to the top gate top portion, the top gate side portion extending from the top gate top portion towards the base substrate. The active layer is sandwiched between the top gate top portion and the bottom gate. A sidewall of the active layer is at least partially surrounded by the top gate side portion.

Abstract: It is an object to provide a flexible light-emitting device with long lifetime in a simple way and to provide an inexpensive electronic device with long lifetime using the flexible light-emitting device. A flexible light-emitting device is provided, which includes a substrate having flexibility and a light-transmitting property with respect to visible light; a first adhesive layer over the substrate; an insulating film containing nitrogen and silicon over the first adhesive layer; a light-emitting element including a first electrode, a second electrode facing the first electrode, and an EL layer between the first electrode and the second electrode; a second adhesive layer over the second electrode; and a metal substrate over the second adhesive layer, wherein the thickness of the metal substrate is 10 ?m to 200 ?m inclusive. Further, an electronic device using the flexible light-emitting device is provided.

Abstract: Materials, devices, methods of use and fabrication thereof are disclosed. The materials are particularly well suited for application in superconducting devices and quantum computing, due to ability to avoid undesirable effects from inherent noise and decoherence. The materials are formed from select isotopes having zero nuclear spin into a single crystal-phase film or layer of thickness depending on the desired application of the resulting device. The film/layer may be suspended or disposed on a substrate. The isotopes may be enriched from naturally-occurring sources of isotopically mixed elemental material(s). The single crystal is preferably devoid of structural defects such as grain boundaries, inclusions, impurities and lattice vacancies. Device configurations may be formed from the layer according to a predetermined pattern using lithographic and/or milling techniques.

Abstract: An organic EL display device includes a rectangular first substrate, an organic EL diode unit formed on the first substrate, a rectangular second substrate formed on the organic EL diode unit, a frame-shaped adhesive section configured to attach the first substrate to the second substrate to surround the organic EL diode unit, an extraction interconnection group constituted by a plurality of extraction interconnections extracted from the organic EL diode unit, and a dummy interconnection group formed at an adhesive region at which the adhesive section of the first substrate is attached and constituted by a plurality of dummy interconnections that are separated from each other, wherein the extraction interconnection and the dummy interconnection cross the adhesive section in the same direction.