Thinning Of Semiconductor Substrate Patents (Class 438/459)
  • Patent number: 11456204
    Abstract: A process for making silicon on insulator wafer by bond and etch back—BESOI. Fluorine ion implantation is performed after bonding and after removal of etch stop layers. The ion energy is chosen to have a peak of ion distribution near the wafer bonding interface. The ion dose is chosen to exceed silicon amorphization threshold at maximum ion distribution. The ion dose is chosen low enough to keep silicon surface crystalline. Solid phase epitaxy SPE is performed after the implant. Finalizing of wafer bonding is performed after the SPE by anneal at 800 C. SPE is performed by anneal where temperature is slow ramped up from 450 to 600 C. In further chipmaking process, defect generation as oxidation induced stacking faults—OISFs—during oxidation step is prevented. OISF are not generated even in metal contaminated wafers. As process does not includes high temperature anneal, RF SOI devices—like front chips of smartphones—made on these wafers have advanced RF performance.
    Type: Grant
    Filed: April 4, 2021
    Date of Patent: September 27, 2022
    Inventor: Alexander Yuri Usenko
  • Patent number: 11450582
    Abstract: A wafer-level package structure is provided, including a device wafer integrated with a first chip. The device wafer includes a first front surface integrated with the first chip and a first back surface opposite to the first front surface. A first oxide layer is formed on the first front surface. A second chip is provided to include a bonding surface, on which a second oxide layer is formed. A carrier substrate is provided to be temporarily bonded with the surface of the second chip that faces away from the bonding surface. The second chip is bonded with the device wafer through bonding the first and the second oxide layers using a fusion bonding process. The second chip and the carrier substrate are debonded. An encapsulation layer is formed on the first oxide layer and covers the second chip.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: September 20, 2022
    Assignee: Ningbo Semiconductor International Corporation
    Inventors: Hailong Luo, Clifford Ian Drowley
  • Patent number: 11444062
    Abstract: A semiconductor device is disclosed including a memory module formed from a pair of semiconductor dies mounted face to face to each other at the wafer level. These die pairs are formed using wafer-to-wafer bonding technology, where the wafers may be bonded to each other when they are of full thickness. Once bonded, respective inactive surfaces of the wafers may be thinned and then the die pairs diced from the wafers to form a completed memory module. When the wafers are bonded face to face, they compensate each other, mechanically resulting in the die pair having a minimum warpage.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: September 13, 2022
    Assignee: SanDisk Technologies LLC
    Inventor: Nagesh Vodrahalli
  • Patent number: 11437344
    Abstract: In an embodiment, a device includes: a first wafer including a first substrate and a first interconnect structure, a sidewall of the first interconnect structure forming an obtuse angle with a sidewall of the first substrate; and a second wafer bonded to the first wafer, the second wafer including a second substrate and a second interconnect structure, the sidewall of the first substrate being laterally offset from a sidewall of the second substrate and a sidewall of the second interconnect structure.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: September 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yung-Chi Lin, Tsang-Jiuh Wu, Wen-Chih Chiou, Chen-Hua Yu
  • Patent number: 11430691
    Abstract: A method includes forming a first conductive feature over a semiconductor substrate, forming an ILD layer over the first conductive feature, patterning the ILD layer to form a trench, and forming a conductive layer over the patterned ILD layer to fill the trench. The method further includes polishing the conductive layer to form a via contact configured to interconnect the first conductive feature with a second conductive feature, where polishing the conductive layer exposes a top surface of the ILD layer, polishing the exposed top surface of the ILD layer, such that a top portion of the via contact protrudes from the exposed top surface of the ILD layer, and forming the second conductive feature over the via contact, such that the top portion of the via contact extends into the second conductive feature.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: August 30, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pang-Sheng Chang, Chao-Hsun Wang, Kuo-Yi Chao, Fu-Kai Yang, Mei-Yun Wang, Li-Chieh Wu, Chun-Wei Hsu
  • Patent number: 11398456
    Abstract: A semiconductor device is described that includes an integrated circuit coupled to a first semiconductor substrate with a first set of passive devices (e.g., inductors) on the first substrate. A second semiconductor substrate with a second set of passive devices (e.g., capacitors) may be coupled to the first substrate. Interconnects in the substrates may allow interconnection between the substrates and the integrated circuit. The passive devices may be used to provide voltage regulation for the integrated circuit. The substrates and integrated circuit may be coupled using metallization.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: July 26, 2022
    Assignee: Apple Inc.
    Inventor: Jun Zhai
  • Patent number: 11387133
    Abstract: A wafer processing method includes a modified layer forming step, a protective member disposing step, a reinforcing portion forming step, and an undersurface processing step. The modified layer forming step forms, in a ring shape, a modified layer not reaching a finished thickness of a wafer by irradiating the wafer with a laser beam such that a condensing point of the laser beam is positioned in an inner part of the wafer, the inner part corresponding to a peripheral surplus region. The reinforcing portion forming step makes a cleavage plane reach the top surface from the modified layer formed in a ring shape, removes the modified layer, thins a region corresponding to a device region of the wafer to the finished thickness, and forms a ring-shaped reinforcing portion in a region corresponding to the peripheral surplus region of the wafer by grinding the undersurface of the wafer.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: July 12, 2022
    Assignee: DISCO CORPORATION
    Inventor: Masaru Nakamura
  • Patent number: 11346018
    Abstract: A silicon carbide substrate production method includes: the step of providing covering layers 1b, 1b, each containing silicon oxide, silicon nitride, silicon carbonitride, or silicide, respectively on both surfaces of a base material substrate 1a carbon, silicon or silicon carbide, and turning the surface of each of the covering layers 1b, 1b into a smooth surface to prepare a support substrate 1; a step of forming a polycrystalline silicon carbide film 10 on both surfaces of the support substrate 1 by a gas phase growth method or a liquid phase growth method; and a step of separating the polycrystalline silicon carbide films from the support substrate while preserving, on the surface thereof, the smoothness of the covering layer surfaces 1b, 1b by chemically removing at least the covering layers 1b, 1b, from the support substrate 1. The silicon carbide substrate has a smooth surface and reduced internal stress.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: May 31, 2022
    Assignees: Shin-Etsu Chemical Co., Ltd., CUSIC Inc.
    Inventors: Hiroyuki Nagasawa, Yoshihiro Kubota, Shoji Akiyama
  • Patent number: 11264469
    Abstract: Various embodiments of the present application are directed to a method for forming a thin semiconductor-on-insulator (SOI) substrate without implantation radiation and/or plasma damage. In some embodiments, a device layer is epitaxially formed on a sacrificial substrate and an insulator layer is formed on the device layer. The insulator layer may, for example, be formed with a net charge that is negative or neutral. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates. The sacrificial substrate is removed, and the device layer is cyclically thinned until the device layer has a target thickness. Each thinning cycle comprises oxidizing a portion of the device layer and removing oxide resulting from the oxidizing.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Ta Wu, Chia-Shiung Tsai, Jiech-Fun Lu, Kuo-Hwa Tzeng, Shih-Pei Chou, Yu-Hung Cheng, Yeur-Luen Tu
  • Patent number: 11264264
    Abstract: At least one circuit element may be formed on a front side of a ringed substrate, and the ringed substrate may be mounted on a mounting chuck. The mounting chuck may have an inner raised portion configured to receive the thinned portion of the substrate thereon, and a recessed ring around a perimeter of the mounting chuck configured to receive the outer ring of the ringed substrate therein. At least one solder bump may be formed that is electrically connected to the at least one circuit element, while the ringed wafer is disposed on the mounting chuck.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: March 1, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Takashi Noma, Noboru Okubo, Yusheng Lin
  • Patent number: 11152276
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric protection layer is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Sheng-Chau Chen, Cheng-Yuan Tsai, Kuo-Ming Wu
  • Patent number: 11139210
    Abstract: In some embodiments, a method for bonding semiconductor wafers is provided. The method includes forming a first integrated circuit (IC) over a central region of a first semiconductor wafer. A first ring-shaped bonding support structure is formed over a ring-shaped peripheral region of the first semiconductor wafer, where the ring-shaped peripheral region of the first semiconductor wafer encircles the central region of the first semiconductor wafer. A second semiconductor wafer is bonded to the first semiconductor wafer, such that a second IC arranged on the second semiconductor wafer is electrically coupled to the first IC.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: October 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Cheng-Yuan Tsai, Chih-Hui Huang, Kuo-Ming Wu
  • Patent number: 11127635
    Abstract: The present disclosure relates to a method for forming a multi-dimensional integrated chip structure. In some embodiments, the method may be performed by bonding a second substrate to an upper surface of a first substrate. A first edge trimming cut is performed along a first loop and extends into a first peripheral portion of the second substrate. A second edge trimming cut is performed along a second loop and extends into a second peripheral portion of the second substrate and into the first substrate. A third edge trimming cut is performed along a third loop and extends into a third peripheral portion of the first substrate.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: September 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Lung Lin, Cheng-Hsien Chou, Cheng-Yuan Tsai, Kuo-Ming Wu, Hau-Yi Hsiao
  • Patent number: 11114314
    Abstract: A method of forming a semiconductor structure includes introducing, at selected conditions, hydrogen and helium species (e.g., ions) in a temporary support to form a plane of weakness at a predetermined depth therein, and to define a superficial layer and a residual part of the temporary support; forming on the temporary support an interconnection layer; placing at least one semiconductor chip on the interconnection layer; assembling a stiffener on a back side of the at least one semiconductor chip; and providing thermal energy to the temporary support to detach the residual part and provide the semiconductor structure. The interconnection layer forms an interposer free from any through via.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: September 7, 2021
    Assignee: Soitec
    Inventors: Bich-Yen Nguyen, Ludovic Ecarnot, Nadia Ben Mohamed, Christophe Malville
  • Patent number: 11088010
    Abstract: A method for the temporary bonding of a substrate of interest to a handle substrate, comprising a step of forming an assembly by placing the bonding faces of the substrate of interest and of the handle substrate into contact with one another via a thermoplastic polymer, and a step of treating the assembly at a treatment temperature that exceeds the glass transition temperature of the thermoplastic polymer. Prior to the assembly forming step, this method comprises: a step of producing, at the bonding face of one of either the substrate of interest or the handle substrate, a central cavity surrounded by a peripheral ring made of a material that is rigid at the treatment temperature, and a step of forming a layer of the thermoplastic polymer filling the central cavity.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: August 10, 2021
    Assignee: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES
    Inventors: Pierre Montmeat, Frank Fournel, Marc Zussy
  • Patent number: 11081604
    Abstract: A process of fabricating and a photoconductive antenna are disclosed which include a semi-insulating substrate having a top side and a bottom side; a low-temperature Gallium Arsenide (GaAs) layer deposited on the top side of the semi-insulating substrate; a plurality of metal electrodes having a bowtie dipole, with an excitation gap at the center, deposited directly on the low-temperature Gallium Arsenide layer; and an extended hemispherical lens attached to the bottom side of the semi-insulating substrate; the extended hemispherical lens further comprises an extension layer and a hemispherical layer separated by an extended line whose position is selected so that a beam of light coming from outside of the extended hemispherical lens is collimated to the excitation gap.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: August 3, 2021
    Assignee: Ton Duc Thang University
    Inventor: Truong Khang Nguyen
  • Patent number: 11056388
    Abstract: A surface protective tape, which is used for a method of producing a semiconductor chip including the steps (a) to (d), and contains a substrate film, and a radiation-curable temporary-adhesive layer and a radiation-curable mask material layer provided on the film in this order; wherein, in the step (b), peeling occurs between the temporary-adhesive layer and the mask material layer before irradiation, and between the mask material layer and the patterned surface described below after irradiation: (a) in the state of having laminated the tape on the side of a patterned surface of a semiconductor wafer, grinding the backing-face of the wafer; laminating a wafer fixing tape on the backing-face side of the ground wafer; and supporting and fixing the wafer to a ring flame; (b) after integrally peeling both the film and the temporary-adhesive layer from the tape thereby to expose the mask material layer on top, forming an opening by cutting a portion of the mask material layer corresponding to a street of the
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: July 6, 2021
    Assignee: FURUKAWA ELECTRIC CO., LTD.
    Inventor: Yusuke Goto
  • Patent number: 11024569
    Abstract: A semiconductor package device includes a circuit layer having a top surface, a first electronic component disposed on the top surface of the circuit layer, and a first conductive element disposed on the top surface of the circuit layer, the first conductive element having a top surface. The first electronic component has an active surface and a back surface facing the top surface of the circuit layer. A distance between the active surface of the first electronic component and the top surface of the circuit layer is greater than a distance between the top surface of the first conductive element and the top surface of the circuit layer.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: June 1, 2021
    Assignee: ADVANCED SEMICONDUCOR ENGINEERING, INC.
    Inventors: Jen-Kuang Fang, Wen-Long Lu
  • Patent number: 11018001
    Abstract: A method of growing a two-dimensional transition metal dichalcogenide (TMD) thin film and a method of manufacturing a device including the two-dimensional TMD thin film are provided. The method of growing the two-dimensional TMD thin film may include a precursor supply operation and an evacuation operation, which are periodically and repeatedly performed in a reaction chamber provided with a substrate for thin film growth. The precursor supply operation may include supplying two or more kinds of precursors of a TMD material to the reaction chamber. The evacuation operation may include evacuating the two or more kinds of precursors and by-products generated therefrom from the reaction chamber.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: May 25, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Haeryong Kim, Hyeonjin Shin, Jaeho Lee, Sanghyun Jo
  • Patent number: 11011495
    Abstract: A data processor is implemented as an integrated circuit. The data processor includes a processor die. The processor die is connected to an integrated voltage regulator die using die-to-die bonding. The integrated voltage regulator die provides a regulated voltage to the processor die, and the processor die operates in response to the regulated voltage.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: May 18, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Milind Bhagavat, David Hugh McIntyre, Rahul Agarwal
  • Patent number: 10998217
    Abstract: A bonding material including a phenoxy resin thermoplastic component, and a carbon black filler component. The carbon black filler component is present in an amount greater than 1 wt. %. The carbon black filler converts the phenoxy resin thermoplastic component from a material that transmits infra-red (IR) wavelengths to a material that absorbs a substantial portion of infra-red (IR) wavelengths.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: May 4, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bing Dang, Jeffrey D. Gelorme, John U. Knickerbocker
  • Patent number: 10971420
    Abstract: A monolithic three-dimensional integrated circuit including a first device, a second device on the first device, and a thermal shield stack between the first device and the second device. The thermal shield stack includes a thermal retarder portion having a low thermal conductivity in a vertical direction, and a thermal spreader portion having a high thermal conductivity in a horizontal direction. The thermal shield stack of the monolithic three-dimensional integrated circuit includes only dielectric materials.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: April 6, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wei-E Wang, Mark S. Rodder, Vassilios Gerousis
  • Patent number: 10950504
    Abstract: A wafer processing method is used in processing a wafer including a device area and a peripheral marginal area surrounding the device area. The device area has a plurality of devices and an electrode connected to each device. The wafer processing method includes the steps of cutting a first area of the peripheral marginal area, fixing the front side of the wafer through an adhesive to a carrier substrate, grinding a back side of the wafer, supplying a chemical solution to the back side of the wafer to thereby etch the wafer such that the electrode projects from the back side of the wafer, forming an insulating film on the back side of the wafer, cutting a second area of the peripheral marginal area, the second area being not in contact with the adhesive, thereby removing the second area, and polishing the insulating film.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: March 16, 2021
    Assignee: DISCO CORPORATION
    Inventors: Zach Powers, Xin Lu, Kokichi Minato
  • Patent number: 10903332
    Abstract: Provided are techniques for generating fully depleted silicon on insulator (SOI) transistor with a ferroelectric layer. The techniques include forming a first multi-layer wafer comprising a semiconductor layer and a buried oxide layer, wherein the semiconductor layer is formed over the buried oxide layer. The techniques also including forming a second multi-layer wafer comprising the ferroelectric layer, and bonding the first multi-layer wafer to the second multi-layer wafer, wherein the bonding comprises a coupling between the buried oxide layer and the second multi-layer wafer.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: January 26, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Shawn P. Fetterolf, Terence B. Hook
  • Patent number: 10867836
    Abstract: A semiconductor device includes a first wafer and a second wafer. The first wafer has a top portion. The second wafer is disposed on the top portion of the first wafer, wherein the second wafer has a bottom portion bonded on the top portion of the first wafer, and a non-bonded area of the bottom portion has a width smaller than 0.5 mm. The bottom portion of the second wafer has a size smaller than or equal to that of the top portion of the first wafer. In some embodiments, the top portion of the first wafer has first rounded corners, and the bottom portion of the second wafer has second corners. A cross-sectional view of each of the second rounded corners has a radius smaller than that of each of first rounded corners. In some embodiments, the bottom portion of the second wafer has right angle corners.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuei-Sung Chang, Ching-Ray Chen, Yen-Cheng Liu, Shang-Ying Tsai
  • Patent number: 10861821
    Abstract: A wafer-level system-in-package (WLSiP) packaging method and a WLSiP package structure are provided. The method includes providing a device wafer including a first front surface and a first back surface and providing a plurality of second chips. The method also includes forming an adhesive layer on the first front surface and patterning the adhesive layer to form a plurality of first through-holes. In addition, the method includes bonding the plurality of second chips with a remaining adhesive layer to cover the plurality of first through-holes. Moreover, the method includes forming a plurality of second through-holes, which are connected with the plurality of first through-holes to form a plurality of first conductive through-holes, each first conductive through-hole includes a second through-hole and a first through-hole. Further, the method includes forming a first conductive plug in a first conductive through-hole to electrically connect to one of the plurality of second chips.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: December 8, 2020
    Assignee: Ningbo Semiconductor International Corporation
    Inventors: Mengbin Liu, Hailong Luo
  • Patent number: 10818501
    Abstract: A method for manufacturing a semiconductor device includes bonding a supporting substrate and a first surface of a semiconductor substrate via a bonding layer, processing a second surface of the supporting substrate, opposite to the first surface, to shape the semiconductor substrate into a thin film. After shaping the semiconductor substrate into a thin film, polishing a part of the bonding layer formed at a beveled portion of the supporting substrate or the semiconductor substrate with a first polishing plane to remove the part of the bonding layera A33fter polishing the part of the bonding layer, polishing a remaining part of the bonding layer formed at the beveled portion of the supporting substrate or the semiconductor substrate with a second polishing plane different from the first polishing plane to remove the remaining part of the bonding layer.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: October 27, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takashi Shirono, Eiji Takano, Gen Toyota, Eiichi Shin
  • Patent number: 10818488
    Abstract: A wafer structure and a trimming method thereof are provided. The trimming method includes the following steps. A first wafer having a first surface and a second surface opposite to the first surface is provided. A first pre-trimming mark is formed on the first surface of the first wafer, wherein forming the first pre-trimming mark includes forming a plurality of recesses arranged as a path along a periphery of the first wafer. The first wafer is trimmed on the first pre-trimming mark and along the path of the first pre-trimming mark to remove a portion of the first wafer and form a trimmed edge having first regions thereon.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: October 27, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Ning Chiang, Ming-Te Chuang
  • Patent number: 10790211
    Abstract: A wafer-level packaging method and a package structure are provided. In the packaging method, a device wafer integrated with a first chip is provided. The device wafer includes a first front surface integrated with the first chip and a first back surface opposite to the first front surface. A first oxide layer is formed on the first front surface. A second chip is provided to include a bonding surface, on which a second oxide layer is formed. A carrier substrate is provided to be temporarily bonded with the surface of the second chip that faces away from the bonding surface. The second chip is bonded with the device wafer through bonding the first and the second oxide layers using a fusion bonding process. The second chip and the carrier substrate are debonded. An encapsulation layer is formed on the first oxide layer and covers the second chip.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: September 29, 2020
    Assignee: Ningbo Semiconductor International Corporation
    Inventors: Hailong Luo, Clifford Ian Drowley
  • Patent number: 10763153
    Abstract: There is provided a holding apparatus which is capable of rotatably holding, while cooling to a cryogenic temperature, a to-be-processed object in a vacuum chamber. A holding apparatus for rotatably holding, while cooling, a to-be-processed object in a vacuum chamber Vc, has a stage on which the to-be-processed object is placed, a rotary drive device for rotatably supporting the stage, and a cooling device for cooling the stage. Provided that a stage surface side on which the to-be-processed object is placed is defined as an upside, the rotary drive device has: a tubular rotary shaft body which is mounted on a wall surface of the vacuum chamber, in a penetrating manner, through a first vacuum seal; a connection member for connecting an upper end part of the rotary shaft body and a lower surface of the stage in a manner to define a space below the stage; and a driving motor for driving to rotate the rotary shaft body.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: September 1, 2020
    Assignees: Ulvac, Inc., Ulvac Cryogenics Inc.
    Inventors: Yukihito Tashiro, Junichi Itoh, Hidenori Fukumoto, Kosuke Hidaka, Mitsuki Terashima
  • Patent number: 10763292
    Abstract: A method includes bonding a first semiconductor chip on a second semiconductor chip, applying an etching process to the first semiconductor chip and the second semiconductor chip until a metal surface of the second semiconductor chip is exposed, wherein as a result of applying the etching process, an opening is formed in the first semiconductor chip and the second semiconductor chip and plating a conductive material in the opening to from a conductive plug.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeng-Shyan Lin, Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Shih-Pei Chou, Min-Feng Kao, Szu-Ying Chen
  • Patent number: 10741389
    Abstract: A method of growing a two-dimensional transition metal dichalcogenide (TMD) thin film and a method of manufacturing a device including the two-dimensional TMD thin film are provided. The method of growing the two-dimensional TMD thin film may include a precursor supply operation and an evacuation operation, which are periodically and repeatedly performed in a reaction chamber provided with a substrate for thin film growth. The precursor supply operation may include supplying two or more kinds of precursors of a TMD material to the reaction chamber. The evacuation operation may include evacuating the two or more kinds of precursors and by-products generated therefrom from the reaction chamber.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: August 11, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Haeryong Kim, Hyeonjin Shin, Jaeho Lee, Sanghyun Jo
  • Patent number: 10727053
    Abstract: A method of fabricating a semiconductor structure includes: growing a dielectric layer on a substrate; defining an epitaxial region and a gap region on the dielectric layer; etching a dielectric layer of the epitaxial region to expose the substrate; sequentially growing a gallium nitride buffer layer and an aluminum gallium nitride barrier layer on the exposed substrate. The method of fabricating a semiconductor structure provided by the present application divides the aluminum gallium nitride barrier layer into a plurality of independent portions, thus preventing the microcracks from occurring in the aluminum gallium nitrogen film while increasing the aluminum component, thereby improving the yield rate and reliability of the device.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: July 28, 2020
    Assignee: SUZHOU HAN HUA SEMICONDUCTOR CO., LTD.
    Inventors: Xianfeng Ni, Qian Fan, Wei He
  • Patent number: 10714446
    Abstract: An apparatus is provided which comprises: a substrate; a first active device adjacent to the substrate; a first set of one or more layers to interconnect with the first active device; a second set of one or more layers; a second active and/or passive device coupled to the second set of one or more layers; and a layer adjacent to one of the layers of the first and second sets, wherein the layer is to bond the one of the layers of the first and second sets.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: July 14, 2020
    Assignee: Intel Corporation
    Inventors: Anup Pancholi, Prashant Majhi, Paul Fischer, Patrick Morrow
  • Patent number: 10665539
    Abstract: Semiconductor devices and methods of formation are provided herein. A semiconductor device includes a first inductor, a patterned ground shielding (PGS) proximate the first inductor comprising one or more portions and a first switch configured to couple a first portion of the PGS to a second portion of the PGS. The semiconductor device also has a configuration including a first inductor on a first side of the PGS, a second inductor on a second side of the PGS and a first switch configured to couple a first portion of the PGS to a second portion of the PGS. Selective coupling of portions of the PGS by activating or deactivating switches alters the behavior of the first inductor, or the behavior and interaction between the first inductor and the second inductor. A mechanism is thus provided for selectively configuring a PGS to control inductive or other properties of a circuit.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hsiao-Tsung Yen, Chin-Wei Kuo, Cheng-Wei Luo, Kung-Hao Liang
  • Patent number: 10546916
    Abstract: Disclosed embodiments include in-recess fabricated vertical capacitor cells, that can be assembled as close to the surface of a semiconductor package substrate as the first-level interconnect surface. The in-recess fabricated vertical capacitor cells are semiconductor package-integrated capacitors. Disclosed embodiments include laminated vertical capacitor cells where a plated through-hole is twice breached to form opposing capacitor plates. The breached, plated through-hole capacitors are semiconductor package-integrated capacitors.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: January 28, 2020
    Assignee: Intel Corporation
    Inventors: Brandon C Marin, Praneeth Akkinepally, Whitney Bryks, Dilan Seneviratne, Frank Truong
  • Patent number: 10508365
    Abstract: A method for producing a semiconductor layer (3), including the following method steps: A creating a release layer (2) on a carrier substrate (1); B applying a semiconductor layer (3) to the release layer (2); C detaching the semiconductor layer (3) from the carrier substrate. The invention is characterized in that, in method step A, the release layer (2) is created so as to fully cover at least a processing side of the carrier substrate, in that, in method step B, the semiconductor layer (3) is applied so as to fully cover the release layer (2) at least on the processing side and partially overlap one or more peripheral sides (5a, 5b) of the carrier substrate and in that, between method steps B and C, in a method step C0, regions of the semiconductor layer (3) that overlap a peripheral side are removed. The invention also relates to a semiconductor wafer, to a device for edge correction, to a detaching unit and to a device for producing a semiconductor layer.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: December 17, 2019
    Assignee: NexWafe GmbH
    Inventors: Stefan Reber, Kai Schillinger, Frank Siebke
  • Patent number: 10453731
    Abstract: A method of transferring an integrated circuit (IC) onto an alternative substrate is provided at a wafer level to enable coefficient of thermal expansion (CTE) matching for a circuit layer to a different material. The method is executable relative to a wafer with a circuit layer, a first major surface, a second major surface opposite the first major surface, and a substrate affixed to the first major surface. The method includes temporarily bonding a handle to the second major surface, removing a majority of the substrate to expose the first major surface and bonding a second substrate to the first major surface with deposited bonding material.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: October 22, 2019
    Assignee: RAYTHEON COMPANY
    Inventor: John J. Drab
  • Patent number: 10411062
    Abstract: Disclosed are a substrate bonding apparatus and a method of manufacturing a semiconductor device. The substrate bonding apparatus comprises vacuum pumps, a first chuck engaged with the vacuum pumps and adsorbing a first substrate at vacuum pressure of the vacuum pumps, and a pushing unit penetrating a center of the first chuck and pushing the first substrate away from the first chuck. The first chuck comprises adsorption sectors providing different vacuum pressures in an azimuth direction to the first substrate.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: September 10, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun Hyung Kim, Seokho Kim, SungHyup Kim, Jaegeun Kim, Taeyeong Kim
  • Patent number: 10395974
    Abstract: Various embodiments of the present application are directed to a method for forming a thin semiconductor-on-insulator (SOI) substrate at low cost and with low total thickness variation (TTV). In some embodiments, an etch stop layer is epitaxially formed on a sacrificial substrate. A device layer is epitaxially formed on the etch stop layer and has a different crystalline lattice than the etch stop layer. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the etch stop layer are between the sacrificial and handle substrates. The sacrificial substrate is removed. An etch is performed into the etch stop layer to remove the etch stop layer. The etch is performed using an etchant comprising hydrofluoric acid, hydrogen peroxide, and acetic acid.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: August 27, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Pei Chou, Hung-Wen Hsu, Jiech-Fun Lu, Yu-Hung Cheng, Yung-Lung Lin, Min-Ying Tsai
  • Patent number: 10384934
    Abstract: A method for manufacturing a MEMS device is disclosed. Moreover a MEMS device and a module including a MEMS device are disclosed. An embodiment includes a method for manufacturing MEMS devices includes forming a MEMS stack over a first main surface of a substrate, forming a polymer layer over a second main surface of the substrate and forming a first opening in the polymer layer and the substrate such that the first opening abuts the MEMS stack.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: August 20, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Alfons Dehe, Stephan Pindl, Bernhard Knott, Carsten Ahrens
  • Patent number: 10326044
    Abstract: A method of processing a device wafer comprising applying a sacrificial material to a surface of a carrier wafer, adhering a surface of the device wafer to an opposing surface of the carrier wafer, planarizing an exposed surface of the sacrificial material by removing only a portion of a thickness thereof, and planarizing an opposing surface of the device wafer. A wafer assembly is also disclosed.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: June 18, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Andrew M. Bayless
  • Patent number: 10312134
    Abstract: A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm; a Group IVA nitride layer in contact with the semiconductor handle substrate, the Group IVA nitride layer selected from the group consisting of carbon nitride, silicon carbon nitride, and a combination thereof; a dielectric layer in contact with the Group IVA nitride layer; and a semiconductor device layer in contact with the dielectric layer.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: June 4, 2019
    Assignee: GlobalWafers Co., Ltd.
    Inventor: Qingmin Liu
  • Patent number: 10293435
    Abstract: The pressure-sensitive adhesive film according to the present invention comprises a resin film as a substrate and a pressure-sensitive adhesive layer provided at least on a face of the resin film. The resin film has a multi-layer constitution consisting of at least two layers. The resin film has a laser beam reflectance of 5% or higher, but 40% or lower in a wavelength range of 1000 nm to 1100 nm, and has a laser beam transmittance of 5% or lower in the said wavelength range.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: May 21, 2019
    Assignees: NITTO DENKO CORPORATION, NITTO EUROPE N.V.
    Inventors: Kenta Yamashita, Mitsushi Yamamoto, Donald Pinxten, Bert Cryns
  • Patent number: 10253222
    Abstract: There is provided a pressure sensitive adhesive sheet for wafer protection (1a) comprising a base material (11), an intermediate layer (12), and a pressure sensitive adhesive layer (13) in this order, wherein the intermediate layer is a layer formed from an intermediate layer-forming composition containing 100 parts by mass of a non-energy ray-curable acrylic polymer (A) and 25 parts by mass or more of an energy ray-curable acrylic polymer (B) having a mass average molecular weight of 50,000 to 250,000; and the pressure sensitive adhesive layer is a layer formed from a pressure sensitive adhesive composition containing an energy ray-curable acrylic polymer (C). The inventive pressure sensitive adhesive sheet for wafer protection is excellent in interfacial adhesion between an intermediate layer and a pressure sensitive adhesive layer after energy ray irradiation.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: April 9, 2019
    Assignee: LINTEC CORPORATION
    Inventors: Sayaka Enoki, Yuki Morita
  • Patent number: 10204824
    Abstract: A method for producing a SOI wafer that includes implanting at least one type of gas ion selected from a hydrogen ion and a rare gas ion from a surface of a bond wafer formed of a silicon single crystal to form an ion implanted layer, bonding the ion-implanted surface of the bond wafer to a surface of a base wafer formed of a silicon single crystal through a silicon oxide film formed on the base wafer surface, delaminating the bond wafer at the ion implanted layer by performing delamination heat treatment to fabricate a SOI wafer having a buried oxide film layer and a SOI layer on the base wafer, and performing flattening heat treatment on the SOI wafer in an atmosphere containing argon gas.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: February 12, 2019
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Isao Yokokawa, Hiroji Aga, Norihiro Kobayashi
  • Patent number: 10199470
    Abstract: A Field Effect Transistor (FET) having a substrate; a plurality of active regions disposed on the substrate; and a laterally extending finger-like control electrode disposed on a portion of a surface of the substrate. The active regions are laterally spaced one from the other successively along the laterally extending finger-like control electrode. The laterally extending finger-like control electrode controls a flow of carriers through each one of the plurality of active regions between a source electrode and a drain electrode.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: February 5, 2019
    Assignee: Raytheon Company
    Inventors: Alan J. Bielunis, Istvan Rodriguez, Christopher M. Laighton
  • Patent number: 10170357
    Abstract: Provided is an SOI wafer manufacturing method that allows production of an SOI wafer having a high gettering ability and a small resistance variance in a thickness direction of an active layer, at high productivity. The SOI wafer manufacturing method includes a first step of implanting light element ions to a surface of at least one of a first substrate and a second substrate to form, on the at least one of the first substrate and the second substrate, a modified layer in which the light element ions are present in solid solution, a second step of forming an oxide film on a surface of at least one of the first substrate and the second substrate, a third step of bonding the first substrate and the second substrate according to a normal-temperature vacuum bonding method, and a fourth step of obtaining an active layer by thinning the first substrate.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: January 1, 2019
    Assignee: SUMCO CORPORATION
    Inventor: Yoshihiro Koga
  • Patent number: 10131541
    Abstract: The present disclosure relates to a method for fabricating a micro-electromechanical system (MEMS) device. In the method, a carrier wafer is received. A MEMS wafer, which includes a plurality of die, is bonded to the carrier wafer. A cavity is formed to separate an upper surface of the carrier wafer from a lower surface of a die of the MEMS wafer. A separation trench is formed to laterally surround the die, wherein formation of the cavity and the separation trench leaves a tethering structure suspending the die over the upper surface of the carrier wafer. The die and carrier wafer are translated with respect to one another to break the tethering structure and separate the die from the carrier wafer.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chia-Hua Chu
  • Patent number: 10128120
    Abstract: The inventive concepts provide a method of completely removing a damage region of a surface of an etch target layer after plasma-etching the etch target layer. The method includes performing a first post-etch plasma treatment process using a first post-treatment gas on the plasma-etched etch target layer. A polarity of ions of the first post-treatment gas may be the same as a polarity of bias power applied to a stage in a plasma apparatus.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: November 13, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwangsu Kim, Byoung Jae Park, Yongsun Ko, Kyunghyun Kim, ChangSup Mun, Kijong Park