Thinning Of Semiconductor Substrate Patents (Class 438/459)
  • Patent number: 11887893
    Abstract: A semiconductor substrate and a method of manufacturing the same are provided. The method includes epitaxially growing a buffer layer and a silicon carbide layer on a silicon surface of an N-type silicon carbide substrate, and the silicon carbide layer is high-resistivity silicon carbide or N-type silicon carbide (N—SiC). Next, a gallium nitride epitaxial layer is epitaxially grown on the silicon carbide layer to obtain a semiconductor structure composed of the buffer layer, the silicon carbide layer, and the gallium nitride epitaxial layer. After the epitaxial growth of the gallium nitride epitaxial layer, a laser is used to form a damaged layer in the semiconductor structure, and a chip carrier is bonded to the surface of the gallium nitride epitaxial layer, and then the N-type silicon carbide and the semiconductor structure are separated at the location of the damaged layer.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: January 30, 2024
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Chih-Yuan Chuang, Walter Tony Wohlmuth
  • Patent number: 11881455
    Abstract: Provided is a semiconductor architecture including a wafer, a first semiconductor device provided on a first surface of the wafer, the first semiconductor device being configured to route signals, a second semiconductor device provided on a second surface of the wafer opposite to the first surface of the wafer, the second semiconductor device being configured to supply power, and a buried power rail (BPR) included inside of the wafer and extending from the first surface of the wafer to the second surface of the wafer, the BPR being configured to deliver the power from the second semiconductor device to the first semiconductor device.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: January 23, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Saehan Park, Hoonseok Seo, Gil Hwan Son, Byounghak Hong, Kang Ill Seo
  • Patent number: 11869859
    Abstract: A die stack includes: a first die including a first semiconductor substrate; a second die including a second semiconductor substrate; a bonding dielectric structure including a bonding polymer and that bonds the first die and the second die; a bonding interconnect structure that extends through the bonding dielectric structure to bond and electrically connect the first die and the second die; and a bonding dummy pattern that extends through the bonding dielectric structure to bond the first die and the second die. The bonding dummy pattern is electrically conductive and is electrically floated.
    Type: Grant
    Filed: August 28, 2021
    Date of Patent: January 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Jen-Yuan Chang
  • Patent number: 11867994
    Abstract: A display module includes: a heating circuit, a gating circuit and a plurality of heating lines. The heating circuit includes a first type of heating signal output terminal and a second type of heating signal output terminal, and the gating circuit includes a gating unit. The first type of heating signal output terminal is electrically connected to a first type of signal input terminal of the gating unit, and a first type of signal output terminal of the gating unit is electrically connected to a first terminal of a heating line; and/or the second type of heating signal output terminal is electrically connected to a second type of signal input terminal of the gating unit, and a second type of signal output terminal of the gating unit is electrically connected to a second terminal of the heating line.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: January 9, 2024
    Assignee: Shanghai AVIC OPTO Electronics Co., Ltd.
    Inventors: Xiangchun Wang, Xiaoyuan Ding, Guanzhong Xiong, Jian Zhao
  • Patent number: 11855159
    Abstract: Various embodiments of the present application are directed to a method for forming a thin semiconductor-on-insulator (SOI) substrate without implantation radiation and/or plasma damage. In some embodiments, a device layer is epitaxially formed on a sacrificial substrate and an insulator layer is formed on the device layer. The insulator layer may, for example, be formed with a net charge that is negative or neutral. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates. The sacrificial substrate is removed, and the device layer is cyclically thinned until the device layer has a target thickness. Each thinning cycle comprises oxidizing a portion of the device layer and removing oxide resulting from the oxidizing.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Ta Wu, Chia-Shiung Tsai, Jiech-Fun Lu, Kuo-Hwa Tzeng, Shih-Pei Chou, Yu-Hung Cheng, Yeur-Luen Tu
  • Patent number: 11854928
    Abstract: A semiconductor package includes an integrated circuit (IC) structure, an insulating encapsulation laterally covering the IC structure, and a redistribution structure disposed on the insulating encapsulation and the IC structure. The redistribution structure is electrically connected to the IC structure. The IC structure includes a first die, a capacitor structure, a dielectric layer laterally covering the first die and the capacitor structure, and a second die disposed on the dielectric layer, the first die, and the capacitor structure. The second die interacts with the capacitor structure, where a bonding interface between the second die and the first die is substantially coplanar with a bonding interface between the second die and the dielectric layer. A manufacturing method of a semiconductor package is also provided.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Tzu-Chun Tang, Wei-Ting Chen, Chung-Hao Tsai
  • Patent number: 11854856
    Abstract: An object is to provide a technique capable of suppressing defectives in semiconductor elements. A manufacturing method of a semiconductor device includes a step of forming a laminated body in which an adhesive protective layer, an adhesive layer, a peeling layer, and a support substrate are disposed in this order on a first main surface of the semiconductor substrate, a step of removing the semiconductor substrate other than a portion where a plurality of circuit elements are formed, a step of bonding the portion where the circuit elements are formed to a transfer substrate, a step of removing the peeling layer, the support substrate and the adhesive layer, a step of removing the adhesive protective layer by chemical treatment, and a step of dividing the plurality of circuit elements.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: December 26, 2023
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Masahiro Fujikawa, Kunihiko Nishimura, Shuichi Hiza, Eiji Yagyu
  • Patent number: 11824047
    Abstract: The present application provides a method for fabricating a semiconductor device including providing a first semiconductor die including a first substrate including a first substrate including a first region and a second region, a plurality of first through substrate vias in the first region, a first circuit layer on the first substrate, and a control circuit on the first region and in the first circuit layer; forming a plurality of through die vias vertically along the first circuit layer and the second region; providing a second semiconductor die including a plurality of second conductive pads substantially coplanar with a top surface of the second semiconductor die; providing a third semiconductor die including a plurality of third conductive pads substantially coplanar with a top surface of the third semiconductor die; flipping the second semiconductor die and bonding the second semiconductor die onto the first circuit layer.
    Type: Grant
    Filed: November 23, 2022
    Date of Patent: November 21, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tse-Yao Huang
  • Patent number: 11817352
    Abstract: A method of fabricating a redistribution circuit structure including the following steps is provided. A conductive via is formed. A photosensitive dielectric layer is formed to cover the conductive via. The photosensitive dielectric layer is partially removed to reveal the conductive via at least through an exposure and development process. A redistribution wiring is formed on the photosensitive dielectric layer and the revealed conductive via.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: November 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Han Wang, Yu-Hsiang Hu, Hung-Jui Kuo
  • Patent number: 11793439
    Abstract: Epidermal electronics are non-invasive and non-obstructive skin mounted sensors with mechanical properties matching human epidermis. Their manufacturing process includes photolithography and dry and wet etching within cleanroom facilities. The high cost of manpower, materials, photo masks, and facilities greatly hinders the commercialization potential of disposable epidermal electronics. In contrast, an embodiment of the invention includes a low cost, high throughput, bench top “cut-and-paste” method to complete the freeform manufacture of epidermal sensor system (ESS) in minutes. This versatile method works for many types of thin metal and polymeric sheets and is compatible with many tattoo adhesives or medical tapes. The resultant ESS is highly multimaterial and multifunctional and may measure ECG, EMG, skin temperature, skin hydration, as well as respiratory rate.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: October 24, 2023
    Assignee: BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM
    Inventors: Nanshu Lu, Shixuan Yang, Pulin Wang
  • Patent number: 11800725
    Abstract: A 3D device including: a first level including first transistors and a first interconnect; a second level including second transistors and overlaying the first level; and at least eight electronic circuit units (ECUs), where each of the at least eight ECUs includes a first circuit, the first circuit including a portion of the first transistors, where each of the at least eight ECUs includes a second circuit including a portion of the second transistors, where each of the at least eight ECUs includes a first vertical bus, where the first vertical bus provides electrical connections between the first circuit and the second circuit, where each of the at least eight ECUs includes at least one processor and at least one memory array, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonding regions and metal to metal bonding regions.
    Type: Grant
    Filed: February 1, 2023
    Date of Patent: October 24, 2023
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han, Brian Cronquist
  • Patent number: 11793005
    Abstract: A semiconductor device, the device comprising: a plurality of transistors, wherein at least one of said plurality of transistors comprises a first single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a second single crystal source, channel, and drain, wherein said second single crystal source, channel, and drain is disposed above said first single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a third single crystal source, channel, and drain, wherein said third single crystal source, channel, and drain is disposed above said second single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a fourth single crystal source, channel, and drain, and wherein said third single crystal channel is self-aligned to said fourth single crystal channel being processed following the same lithography step.
    Type: Grant
    Filed: February 2, 2023
    Date of Patent: October 17, 2023
    Assignee: Monolithic 3D Inc.
    Inventors: Deepak C. Sekar, Zvi Or-Bach
  • Patent number: 11715684
    Abstract: A semiconductor device includes lower circuit patterns on a lower substrate; lower bonding patterns on the lower circuit patterns, the lower bonding patterns including a conductive material and being electrically connected to the lower circuit patterns; upper bonding patterns on and contacting the lower bonding patterns, and including a conductive material; a passive device on the upper bonding patterns, and including a conductive material and contacting one of the upper bonding patterns; a gate electrode structure on the passive device, and including gate electrodes spaced apart from each other in a first direction, each of which extends in a second direction, and extension lengths in the second direction of the gate electrodes increasing from a lowermost level toward an uppermost level in a stepwise manner; a channel extending through at least a portion of the gate electrode structure; and an upper substrate on the channel.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: August 1, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sungmin Hwang, Jiwon Kim, Jaeho Ahn, Joonsung Lim, Sukkang Sung
  • Patent number: 11707219
    Abstract: An electrode sheet is capable of suppressing an influence of noise that is applied on a wire, and a biological signal measuring device uses the electrode sheet. The electrode sheet is provided with a sheet, a biological signal receiving electrode formed at the sheet and exposed from the sheet, a biological signal amplifier formed at the sheet, an interface part for connection to an external biological signal processing unit, a first wire that connects the biological signal receiving electrode and an input part of the biological signal amplifier to each other, and a second wire that connects the interface part and an output part of the biological signal amplifier to each other.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: July 25, 2023
    Assignee: Osaka University
    Inventors: Tsuyoshi Sekitani, Takafumi Uemura, Teppei Araki, Shusuke Yoshimoto
  • Patent number: 11711913
    Abstract: First semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes a programmable logic device, an array of static random-access memory (SRAM) cells, and a first bonding layer including first bonding contacts. Second semiconductor structures are formed on a second wafer. At least one of the second semiconductor structures includes an array of NAND memory cells and a second bonding layer including second bonding contacts. The first wafer and the second wafer are bonded in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. The bonded first and second wafers are diced into dies. At least one of the dies includes the bonded first and second semiconductor structures.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: July 25, 2023
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Weihua Cheng, Jun Liu
  • Patent number: 11707200
    Abstract: A connector (140) is provided with a holding component (141), a support component (148), a terminal (144) electrically connected to a contact of a guide wire (130) held by the holding component (141), and a guide component (147) rotatable around an axial line (130A) of the guide wire (130) with respect to the support component (148). The holding component (141) is provided with a body (150) having an insertion hole (150a) for the guide wire (130) and a holding piece (151) extending along an axial line of the insertion hole (150a) from the body (150) and capable of being elastically deformed inward in a radial direction with respect to the axial line. The guide component (147) has a guide surface (165a) guiding the holding piece (151) inward in the radial direction. The holding component (141) is slid along the axis line of the insertion hole (150a) with respect to the guide component (147), whereby the holding piece abuts on the guide surface (165a) to be elastically deformed inward in the radial direction.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: July 25, 2023
    Inventors: Katsuya Miyagawa, Natsumi Shimazaki, Tomoe Morita
  • Patent number: 11705323
    Abstract: The wafer trimming device includes a chuck table configured to hold a target wafer via suction, thereby fixing the target wafer, a notch trimmer configured to trim a notch of the target wafer, and an edge trimmer configured to trim an edge of the target wafer. The notch trimmer includes a notch trimming blade configured to rotate about a rotation axis perpendicular to a circumferential surface of the target wafer. The edge trimmer includes an edge trimming blade configured to rotate about a rotation axis parallel to the circumferential surface of the target wafer.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: July 18, 2023
    Inventors: Jungseok Ahn, Unbyoung Kang, Chungsun Lee, Teakhoon Lee
  • Patent number: 11688763
    Abstract: A semiconductor device structure may include a substrate having a substrate base comprising a first dopant type; a semiconductor layer disposed on a surface of the substrate base, the semiconductor layer comprising a second dopant type and having an upper surface; and a semiconductor plug assembly comprising a semiconductor plug disposed within the semiconductor layer, the semiconductor plug extending from an upper surface of the semiconductor layer and having a depth at least equal to a thickness of the semiconductor layer, the semiconductor plug having a first boundary, the first boundary formed within the semiconductor layer, and having a second boundary, the second boundary formed within the semiconductor layer and disposed opposite the first boundary, wherein the first boundary and second boundary extend perpendicularly to the surface of the substrate base.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: June 27, 2023
    Assignee: Littelfuse, Inc.
    Inventors: Ader Shen, Ting-Fung Chang, James Lu, Wayne Lin
  • Patent number: 11676863
    Abstract: Implementations of a method for aligning a semiconductor wafer for singulation may include: providing a semiconductor wafer having a first side and a second side. The first side of the wafer may include a plurality of die and the plurality of die may be separated by streets. The semiconductor wafer may include an edge ring around a perimeter of the wafer on the second side of the wafer. The wafer may also include a metal layer on the second side of the wafer. The metal layer may substantially cover the edge ring. The method may include grinding the edge ring to create an edge exclusion area and aligning the semiconductor wafer with a saw using a camera positioned in the edge exclusion area on the second side of the wafer. Aligning the wafer may include using three or more alignment features included in the edge exclusion area.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: June 13, 2023
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Takashi Noma
  • Patent number: 11646309
    Abstract: A semiconductor device including: a first silicon level including a first single crystal silicon layer and a plurality of first transistors; a first metal layer disposed over the first silicon level; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 40 nm alignment error; a via disposed through the second level, where each of the second transistors includes a metal gate, where a typical thickness of the second metal layer is greater than a typical thickness of the third metal layer by at least 50%.
    Type: Grant
    Filed: May 28, 2022
    Date of Patent: May 9, 2023
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Patent number: 11626550
    Abstract: A micro light emitting diode (LED) having a high light extraction efficiency includes a bottom conductive layer, a light emitting layer on the bottom conductive layer, and a top conductive structure on the light emitting layer. The micro LED additionally includes a conductive side arm electrically connecting the sidewall of the light emitting layer with the bottom conductive layer, and a reflective bottom dielectric layer arranged under the light emitting layer and above the bottom conductive layer. In some embodiments, the micro LED further includes an ohmic contact between the top conductive structure and the light emitting layer that has a small area and is transparent, thereby increasing the light emergent area and improving the light extraction efficiency.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: April 11, 2023
    Assignee: Jade Bird Display (Shanghai) Limited
    Inventor: Qiming Li
  • Patent number: 11600706
    Abstract: A composite substrate is provided in some embodiments of the present disclosure, which includes a substrate, an insulation layer, a first silicon-containing layer and a first epitaxial layer. The insulation layer is disposed on the substrate. The first silicon-containing layer is disposed on the insulation layer, in which the first silicon-containing layer includes a plurality of group V atoms. The first epitaxial layer is disposed on the first silicon-containing layer, in which the first epitaxial layer includes a plurality of group III atoms. A distribution concentration of the group V atoms in the first silicon-containing layer increases as getting closer to the first epitaxial layer, and a distribution concentration of the group III atoms in the first epitaxial layer increases as getting closer to the first silicon-containing layer. A method of manufacturing a composite substrate is also provided in some embodiments of the present disclosure.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: March 7, 2023
    Assignee: WAFER WORKS CORPORATION
    Inventor: Wen-Chung Li
  • Patent number: 11569115
    Abstract: A method of temporary bonding of an object having first and second opposite surfaces successively including bonding the object to a handle on the side of the first surface, bonding the object to a first adhesive film on the side of the second surface, bonding the first adhesive film to a second adhesive film on the side opposite to the object, and removing the handle from the object.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: January 31, 2023
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Pierre Montmeat, Frank Fournel, Laurent Bally, Thierry Enot
  • Patent number: 11557572
    Abstract: The present application discloses a semiconductor device with stacked dies and the method for fabricating the semiconductor device with the stacked dies. The semiconductor device includes a first semiconductor die including a first substrate including a first and a second region, a first circuit layer on the first substrate, a control circuit on the first region and in the first circuit layer; and through die vias along the first circuit layer and the second region; a second semiconductor die stacked on the first semiconductor die and including second conductive pads connected to the through die vias and the control circuit; and a third semiconductor die stacked under the first semiconductor die and including third conductive pads connected to the through die vias and the control circuit. The through die vias, the second conductive pads, and the third conductive pads configure transmission channels through which the control circuit is capable to access the second and the third semiconductor die.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: January 17, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tse-Yao Huang
  • Patent number: 11502190
    Abstract: A vertical power semiconductor device is described. The vertical power semiconductor device includes a semiconductor body having a first main surface and a second main surface opposite to the first main surface. A thickness of the semiconductor body between the first main surface and the second main surface ranges from 40 ?m to 200 ?m. Active device elements are formed in the semiconductor body at the first main surface. Edge termination elements at least partly surround the active device elements at the first main surface. A diffusion region extends into the semiconductor body from the second main surface. A doping concentration profile of the diffusion region decreases from a peak concentration Ns at the second main surface to a concentration Ns/e, e being Euler's number, over a vertical distance ranging from 1 ?m to 5 ?m.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: November 15, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Andre Brockmeier, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze
  • Patent number: 11494277
    Abstract: Implementations of encoding techniques are disclosed. The encoding technique, such as a Data bus Inversion (DBI) technique, is implementable in a vertically-stacked memory module, but is riot limited thereto. The module can be a plurality of memory integrated circuits which are vertically stacked, and which communicate via a bus formed in one embodiment of channels comprising Through-Wafer Interconnects (TWIs), but again is not limited thereto. One such module includes spare channels that are normally used to reroute a data signal on the bus away from faulty data channels. In one disclosed technique, the status of a spare channel or channels is queried, and if one or more are unused, they can be used to carry a DBI bit, thus allowing at least a portion of the bus to be assessed in accordance with a DBI algorithm. Depending on the location and number of spare channels needed for rerouting, DBI can be apportioned across the bus in various manners.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: November 8, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Timothy Mowry Hollis
  • Patent number: 11495489
    Abstract: Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate with a thick device layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer covering a handle substrate, and epitaxially forming a device layer on a sacrificial substrate. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates, and the sacrificial substrate is removed. The removal includes performing an etch into the sacrificial substrate until the device layer is reached. Because the device layer is formed by epitaxy and transferred to the handle substrate, the device layer may be formed with a large thickness. Further, because the epitaxy is not affected by the thickness of the insulator layer, the insulator layer may be formed with a large thickness.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: November 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Ta Wu, Chia-Shiung Tsai, Jiech-Fun Lu, Kuan-Liang Liu, Shih-Pei Chou, Yu-Hung Cheng, Yeur-Luen Tu
  • Patent number: 11482407
    Abstract: There is provided a wafer grinding method of grinding a wafer having an orientation flat for indicating a crystal orientation in the condition where the wafer is held on a holding surface of a chuck table. The chuck table includes a suction holding portion for holding the wafer under suction and a frame portion surrounding the suction holding portion. The suction holding portion has a first cutout portion corresponding to the orientation flat, and the frame portion has a second cutout portion formed along the first cutout portion. The wafer grinding method includes a holding surface grinding step of grinding the holding surface by using abrasive members of a grinding wheel, and a wafer grinding step of grinding the wafer by using the abrasive members in the condition where the wafer is held on the holding surface ground by the abrasive members.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: October 25, 2022
    Assignee: DISCO CORPORATION
    Inventor: Yohei Gokita
  • Patent number: 11462495
    Abstract: A method includes forming integrated circuits on a front side of a first chip, performing a backside grinding on the first chip to reveal a plurality of through-vias in the first chip, and forming a first bridge structure on a backside of the first chip using a damascene process. The bridge structure has a first bond pad, a second bond pad, and a conductive trace electrically connecting the first bond pad to the second bond pad. The method further includes bonding a second chip and a third chip to the first chip through face-to-back bonding. A third bond pad of the second chip is bonded to the first bond pad of the first chip. A fourth bond pad of the third chip is bonded to the second bond pad of the first chip.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: October 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee
  • Patent number: 11456204
    Abstract: A process for making silicon on insulator wafer by bond and etch back—BESOI. Fluorine ion implantation is performed after bonding and after removal of etch stop layers. The ion energy is chosen to have a peak of ion distribution near the wafer bonding interface. The ion dose is chosen to exceed silicon amorphization threshold at maximum ion distribution. The ion dose is chosen low enough to keep silicon surface crystalline. Solid phase epitaxy SPE is performed after the implant. Finalizing of wafer bonding is performed after the SPE by anneal at 800 C. SPE is performed by anneal where temperature is slow ramped up from 450 to 600 C. In further chipmaking process, defect generation as oxidation induced stacking faults—OISFs—during oxidation step is prevented. OISF are not generated even in metal contaminated wafers. As process does not includes high temperature anneal, RF SOI devices—like front chips of smartphones—made on these wafers have advanced RF performance.
    Type: Grant
    Filed: April 4, 2021
    Date of Patent: September 27, 2022
    Inventor: Alexander Yuri Usenko
  • Patent number: 11450582
    Abstract: A wafer-level package structure is provided, including a device wafer integrated with a first chip. The device wafer includes a first front surface integrated with the first chip and a first back surface opposite to the first front surface. A first oxide layer is formed on the first front surface. A second chip is provided to include a bonding surface, on which a second oxide layer is formed. A carrier substrate is provided to be temporarily bonded with the surface of the second chip that faces away from the bonding surface. The second chip is bonded with the device wafer through bonding the first and the second oxide layers using a fusion bonding process. The second chip and the carrier substrate are debonded. An encapsulation layer is formed on the first oxide layer and covers the second chip.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: September 20, 2022
    Assignee: Ningbo Semiconductor International Corporation
    Inventors: Hailong Luo, Clifford Ian Drowley
  • Patent number: 11444062
    Abstract: A semiconductor device is disclosed including a memory module formed from a pair of semiconductor dies mounted face to face to each other at the wafer level. These die pairs are formed using wafer-to-wafer bonding technology, where the wafers may be bonded to each other when they are of full thickness. Once bonded, respective inactive surfaces of the wafers may be thinned and then the die pairs diced from the wafers to form a completed memory module. When the wafers are bonded face to face, they compensate each other, mechanically resulting in the die pair having a minimum warpage.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: September 13, 2022
    Assignee: SanDisk Technologies LLC
    Inventor: Nagesh Vodrahalli
  • Patent number: 11437344
    Abstract: In an embodiment, a device includes: a first wafer including a first substrate and a first interconnect structure, a sidewall of the first interconnect structure forming an obtuse angle with a sidewall of the first substrate; and a second wafer bonded to the first wafer, the second wafer including a second substrate and a second interconnect structure, the sidewall of the first substrate being laterally offset from a sidewall of the second substrate and a sidewall of the second interconnect structure.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: September 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yung-Chi Lin, Tsang-Jiuh Wu, Wen-Chih Chiou, Chen-Hua Yu
  • Patent number: 11430691
    Abstract: A method includes forming a first conductive feature over a semiconductor substrate, forming an ILD layer over the first conductive feature, patterning the ILD layer to form a trench, and forming a conductive layer over the patterned ILD layer to fill the trench. The method further includes polishing the conductive layer to form a via contact configured to interconnect the first conductive feature with a second conductive feature, where polishing the conductive layer exposes a top surface of the ILD layer, polishing the exposed top surface of the ILD layer, such that a top portion of the via contact protrudes from the exposed top surface of the ILD layer, and forming the second conductive feature over the via contact, such that the top portion of the via contact extends into the second conductive feature.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: August 30, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pang-Sheng Chang, Chao-Hsun Wang, Kuo-Yi Chao, Fu-Kai Yang, Mei-Yun Wang, Li-Chieh Wu, Chun-Wei Hsu
  • Patent number: 11398456
    Abstract: A semiconductor device is described that includes an integrated circuit coupled to a first semiconductor substrate with a first set of passive devices (e.g., inductors) on the first substrate. A second semiconductor substrate with a second set of passive devices (e.g., capacitors) may be coupled to the first substrate. Interconnects in the substrates may allow interconnection between the substrates and the integrated circuit. The passive devices may be used to provide voltage regulation for the integrated circuit. The substrates and integrated circuit may be coupled using metallization.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: July 26, 2022
    Assignee: Apple Inc.
    Inventor: Jun Zhai
  • Patent number: 11387133
    Abstract: A wafer processing method includes a modified layer forming step, a protective member disposing step, a reinforcing portion forming step, and an undersurface processing step. The modified layer forming step forms, in a ring shape, a modified layer not reaching a finished thickness of a wafer by irradiating the wafer with a laser beam such that a condensing point of the laser beam is positioned in an inner part of the wafer, the inner part corresponding to a peripheral surplus region. The reinforcing portion forming step makes a cleavage plane reach the top surface from the modified layer formed in a ring shape, removes the modified layer, thins a region corresponding to a device region of the wafer to the finished thickness, and forms a ring-shaped reinforcing portion in a region corresponding to the peripheral surplus region of the wafer by grinding the undersurface of the wafer.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: July 12, 2022
    Assignee: DISCO CORPORATION
    Inventor: Masaru Nakamura
  • Patent number: 11346018
    Abstract: A silicon carbide substrate production method includes: the step of providing covering layers 1b, 1b, each containing silicon oxide, silicon nitride, silicon carbonitride, or silicide, respectively on both surfaces of a base material substrate 1a carbon, silicon or silicon carbide, and turning the surface of each of the covering layers 1b, 1b into a smooth surface to prepare a support substrate 1; a step of forming a polycrystalline silicon carbide film 10 on both surfaces of the support substrate 1 by a gas phase growth method or a liquid phase growth method; and a step of separating the polycrystalline silicon carbide films from the support substrate while preserving, on the surface thereof, the smoothness of the covering layer surfaces 1b, 1b by chemically removing at least the covering layers 1b, 1b, from the support substrate 1. The silicon carbide substrate has a smooth surface and reduced internal stress.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: May 31, 2022
    Assignees: Shin-Etsu Chemical Co., Ltd., CUSIC Inc.
    Inventors: Hiroyuki Nagasawa, Yoshihiro Kubota, Shoji Akiyama
  • Patent number: 11264264
    Abstract: At least one circuit element may be formed on a front side of a ringed substrate, and the ringed substrate may be mounted on a mounting chuck. The mounting chuck may have an inner raised portion configured to receive the thinned portion of the substrate thereon, and a recessed ring around a perimeter of the mounting chuck configured to receive the outer ring of the ringed substrate therein. At least one solder bump may be formed that is electrically connected to the at least one circuit element, while the ringed wafer is disposed on the mounting chuck.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: March 1, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Takashi Noma, Noboru Okubo, Yusheng Lin
  • Patent number: 11264469
    Abstract: Various embodiments of the present application are directed to a method for forming a thin semiconductor-on-insulator (SOI) substrate without implantation radiation and/or plasma damage. In some embodiments, a device layer is epitaxially formed on a sacrificial substrate and an insulator layer is formed on the device layer. The insulator layer may, for example, be formed with a net charge that is negative or neutral. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates. The sacrificial substrate is removed, and the device layer is cyclically thinned until the device layer has a target thickness. Each thinning cycle comprises oxidizing a portion of the device layer and removing oxide resulting from the oxidizing.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Ta Wu, Chia-Shiung Tsai, Jiech-Fun Lu, Kuo-Hwa Tzeng, Shih-Pei Chou, Yu-Hung Cheng, Yeur-Luen Tu
  • Patent number: 11152276
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric protection layer is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Sheng-Chau Chen, Cheng-Yuan Tsai, Kuo-Ming Wu
  • Patent number: 11139210
    Abstract: In some embodiments, a method for bonding semiconductor wafers is provided. The method includes forming a first integrated circuit (IC) over a central region of a first semiconductor wafer. A first ring-shaped bonding support structure is formed over a ring-shaped peripheral region of the first semiconductor wafer, where the ring-shaped peripheral region of the first semiconductor wafer encircles the central region of the first semiconductor wafer. A second semiconductor wafer is bonded to the first semiconductor wafer, such that a second IC arranged on the second semiconductor wafer is electrically coupled to the first IC.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: October 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Cheng-Yuan Tsai, Chih-Hui Huang, Kuo-Ming Wu
  • Patent number: 11127635
    Abstract: The present disclosure relates to a method for forming a multi-dimensional integrated chip structure. In some embodiments, the method may be performed by bonding a second substrate to an upper surface of a first substrate. A first edge trimming cut is performed along a first loop and extends into a first peripheral portion of the second substrate. A second edge trimming cut is performed along a second loop and extends into a second peripheral portion of the second substrate and into the first substrate. A third edge trimming cut is performed along a third loop and extends into a third peripheral portion of the first substrate.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: September 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Lung Lin, Cheng-Hsien Chou, Cheng-Yuan Tsai, Kuo-Ming Wu, Hau-Yi Hsiao
  • Patent number: 11114314
    Abstract: A method of forming a semiconductor structure includes introducing, at selected conditions, hydrogen and helium species (e.g., ions) in a temporary support to form a plane of weakness at a predetermined depth therein, and to define a superficial layer and a residual part of the temporary support; forming on the temporary support an interconnection layer; placing at least one semiconductor chip on the interconnection layer; assembling a stiffener on a back side of the at least one semiconductor chip; and providing thermal energy to the temporary support to detach the residual part and provide the semiconductor structure. The interconnection layer forms an interposer free from any through via.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: September 7, 2021
    Assignee: Soitec
    Inventors: Bich-Yen Nguyen, Ludovic Ecarnot, Nadia Ben Mohamed, Christophe Malville
  • Patent number: 11088010
    Abstract: A method for the temporary bonding of a substrate of interest to a handle substrate, comprising a step of forming an assembly by placing the bonding faces of the substrate of interest and of the handle substrate into contact with one another via a thermoplastic polymer, and a step of treating the assembly at a treatment temperature that exceeds the glass transition temperature of the thermoplastic polymer. Prior to the assembly forming step, this method comprises: a step of producing, at the bonding face of one of either the substrate of interest or the handle substrate, a central cavity surrounded by a peripheral ring made of a material that is rigid at the treatment temperature, and a step of forming a layer of the thermoplastic polymer filling the central cavity.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: August 10, 2021
    Assignee: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES
    Inventors: Pierre Montmeat, Frank Fournel, Marc Zussy
  • Patent number: 11081604
    Abstract: A process of fabricating and a photoconductive antenna are disclosed which include a semi-insulating substrate having a top side and a bottom side; a low-temperature Gallium Arsenide (GaAs) layer deposited on the top side of the semi-insulating substrate; a plurality of metal electrodes having a bowtie dipole, with an excitation gap at the center, deposited directly on the low-temperature Gallium Arsenide layer; and an extended hemispherical lens attached to the bottom side of the semi-insulating substrate; the extended hemispherical lens further comprises an extension layer and a hemispherical layer separated by an extended line whose position is selected so that a beam of light coming from outside of the extended hemispherical lens is collimated to the excitation gap.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: August 3, 2021
    Assignee: Ton Duc Thang University
    Inventor: Truong Khang Nguyen
  • Patent number: 11056388
    Abstract: A surface protective tape, which is used for a method of producing a semiconductor chip including the steps (a) to (d), and contains a substrate film, and a radiation-curable temporary-adhesive layer and a radiation-curable mask material layer provided on the film in this order; wherein, in the step (b), peeling occurs between the temporary-adhesive layer and the mask material layer before irradiation, and between the mask material layer and the patterned surface described below after irradiation: (a) in the state of having laminated the tape on the side of a patterned surface of a semiconductor wafer, grinding the backing-face of the wafer; laminating a wafer fixing tape on the backing-face side of the ground wafer; and supporting and fixing the wafer to a ring flame; (b) after integrally peeling both the film and the temporary-adhesive layer from the tape thereby to expose the mask material layer on top, forming an opening by cutting a portion of the mask material layer corresponding to a street of the
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: July 6, 2021
    Assignee: FURUKAWA ELECTRIC CO., LTD.
    Inventor: Yusuke Goto
  • Patent number: 11024569
    Abstract: A semiconductor package device includes a circuit layer having a top surface, a first electronic component disposed on the top surface of the circuit layer, and a first conductive element disposed on the top surface of the circuit layer, the first conductive element having a top surface. The first electronic component has an active surface and a back surface facing the top surface of the circuit layer. A distance between the active surface of the first electronic component and the top surface of the circuit layer is greater than a distance between the top surface of the first conductive element and the top surface of the circuit layer.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: June 1, 2021
    Assignee: ADVANCED SEMICONDUCOR ENGINEERING, INC.
    Inventors: Jen-Kuang Fang, Wen-Long Lu
  • Patent number: 11018001
    Abstract: A method of growing a two-dimensional transition metal dichalcogenide (TMD) thin film and a method of manufacturing a device including the two-dimensional TMD thin film are provided. The method of growing the two-dimensional TMD thin film may include a precursor supply operation and an evacuation operation, which are periodically and repeatedly performed in a reaction chamber provided with a substrate for thin film growth. The precursor supply operation may include supplying two or more kinds of precursors of a TMD material to the reaction chamber. The evacuation operation may include evacuating the two or more kinds of precursors and by-products generated therefrom from the reaction chamber.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: May 25, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Haeryong Kim, Hyeonjin Shin, Jaeho Lee, Sanghyun Jo
  • Patent number: 11011495
    Abstract: A data processor is implemented as an integrated circuit. The data processor includes a processor die. The processor die is connected to an integrated voltage regulator die using die-to-die bonding. The integrated voltage regulator die provides a regulated voltage to the processor die, and the processor die operates in response to the regulated voltage.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: May 18, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Milind Bhagavat, David Hugh McIntyre, Rahul Agarwal
  • Patent number: 10998217
    Abstract: A bonding material including a phenoxy resin thermoplastic component, and a carbon black filler component. The carbon black filler component is present in an amount greater than 1 wt. %. The carbon black filler converts the phenoxy resin thermoplastic component from a material that transmits infra-red (IR) wavelengths to a material that absorbs a substantial portion of infra-red (IR) wavelengths.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: May 4, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bing Dang, Jeffrey D. Gelorme, John U. Knickerbocker