Thinning Of Semiconductor Substrate Patents (Class 438/459)
  • Patent number: 10384934
    Abstract: A method for manufacturing a MEMS device is disclosed. Moreover a MEMS device and a module including a MEMS device are disclosed. An embodiment includes a method for manufacturing MEMS devices includes forming a MEMS stack over a first main surface of a substrate, forming a polymer layer over a second main surface of the substrate and forming a first opening in the polymer layer and the substrate such that the first opening abuts the MEMS stack.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: August 20, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Alfons Dehe, Stephan Pindl, Bernhard Knott, Carsten Ahrens
  • Patent number: 10326044
    Abstract: A method of processing a device wafer comprising applying a sacrificial material to a surface of a carrier wafer, adhering a surface of the device wafer to an opposing surface of the carrier wafer, planarizing an exposed surface of the sacrificial material by removing only a portion of a thickness thereof, and planarizing an opposing surface of the device wafer. A wafer assembly is also disclosed.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: June 18, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Andrew M. Bayless
  • Patent number: 10312134
    Abstract: A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm; a Group IVA nitride layer in contact with the semiconductor handle substrate, the Group IVA nitride layer selected from the group consisting of carbon nitride, silicon carbon nitride, and a combination thereof; a dielectric layer in contact with the Group IVA nitride layer; and a semiconductor device layer in contact with the dielectric layer.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: June 4, 2019
    Assignee: GlobalWafers Co., Ltd.
    Inventor: Qingmin Liu
  • Patent number: 10293435
    Abstract: The pressure-sensitive adhesive film according to the present invention comprises a resin film as a substrate and a pressure-sensitive adhesive layer provided at least on a face of the resin film. The resin film has a multi-layer constitution consisting of at least two layers. The resin film has a laser beam reflectance of 5% or higher, but 40% or lower in a wavelength range of 1000 nm to 1100 nm, and has a laser beam transmittance of 5% or lower in the said wavelength range.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: May 21, 2019
    Assignees: NITTO DENKO CORPORATION, NITTO EUROPE N.V.
    Inventors: Kenta Yamashita, Mitsushi Yamamoto, Donald Pinxten, Bert Cryns
  • Patent number: 10253222
    Abstract: There is provided a pressure sensitive adhesive sheet for wafer protection (1a) comprising a base material (11), an intermediate layer (12), and a pressure sensitive adhesive layer (13) in this order, wherein the intermediate layer is a layer formed from an intermediate layer-forming composition containing 100 parts by mass of a non-energy ray-curable acrylic polymer (A) and 25 parts by mass or more of an energy ray-curable acrylic polymer (B) having a mass average molecular weight of 50,000 to 250,000; and the pressure sensitive adhesive layer is a layer formed from a pressure sensitive adhesive composition containing an energy ray-curable acrylic polymer (C). The inventive pressure sensitive adhesive sheet for wafer protection is excellent in interfacial adhesion between an intermediate layer and a pressure sensitive adhesive layer after energy ray irradiation.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: April 9, 2019
    Assignee: LINTEC CORPORATION
    Inventors: Sayaka Enoki, Yuki Morita
  • Patent number: 10204824
    Abstract: A method for producing a SOI wafer that includes implanting at least one type of gas ion selected from a hydrogen ion and a rare gas ion from a surface of a bond wafer formed of a silicon single crystal to form an ion implanted layer, bonding the ion-implanted surface of the bond wafer to a surface of a base wafer formed of a silicon single crystal through a silicon oxide film formed on the base wafer surface, delaminating the bond wafer at the ion implanted layer by performing delamination heat treatment to fabricate a SOI wafer having a buried oxide film layer and a SOI layer on the base wafer, and performing flattening heat treatment on the SOI wafer in an atmosphere containing argon gas.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: February 12, 2019
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Isao Yokokawa, Hiroji Aga, Norihiro Kobayashi
  • Patent number: 10199470
    Abstract: A Field Effect Transistor (FET) having a substrate; a plurality of active regions disposed on the substrate; and a laterally extending finger-like control electrode disposed on a portion of a surface of the substrate. The active regions are laterally spaced one from the other successively along the laterally extending finger-like control electrode. The laterally extending finger-like control electrode controls a flow of carriers through each one of the plurality of active regions between a source electrode and a drain electrode.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: February 5, 2019
    Assignee: Raytheon Company
    Inventors: Alan J. Bielunis, Istvan Rodriguez, Christopher M. Laighton
  • Patent number: 10170357
    Abstract: Provided is an SOI wafer manufacturing method that allows production of an SOI wafer having a high gettering ability and a small resistance variance in a thickness direction of an active layer, at high productivity. The SOI wafer manufacturing method includes a first step of implanting light element ions to a surface of at least one of a first substrate and a second substrate to form, on the at least one of the first substrate and the second substrate, a modified layer in which the light element ions are present in solid solution, a second step of forming an oxide film on a surface of at least one of the first substrate and the second substrate, a third step of bonding the first substrate and the second substrate according to a normal-temperature vacuum bonding method, and a fourth step of obtaining an active layer by thinning the first substrate.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: January 1, 2019
    Assignee: SUMCO CORPORATION
    Inventor: Yoshihiro Koga
  • Patent number: 10131541
    Abstract: The present disclosure relates to a method for fabricating a micro-electromechanical system (MEMS) device. In the method, a carrier wafer is received. A MEMS wafer, which includes a plurality of die, is bonded to the carrier wafer. A cavity is formed to separate an upper surface of the carrier wafer from a lower surface of a die of the MEMS wafer. A separation trench is formed to laterally surround the die, wherein formation of the cavity and the separation trench leaves a tethering structure suspending the die over the upper surface of the carrier wafer. The die and carrier wafer are translated with respect to one another to break the tethering structure and separate the die from the carrier wafer.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chia-Hua Chu
  • Patent number: 10128120
    Abstract: The inventive concepts provide a method of completely removing a damage region of a surface of an etch target layer after plasma-etching the etch target layer. The method includes performing a first post-etch plasma treatment process using a first post-treatment gas on the plasma-etched etch target layer. A polarity of ions of the first post-treatment gas may be the same as a polarity of bias power applied to a stage in a plasma apparatus.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: November 13, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwangsu Kim, Byoung Jae Park, Yongsun Ko, Kyunghyun Kim, ChangSup Mun, Kijong Park
  • Patent number: 10128143
    Abstract: Temporary adhesive material for wafer processing, the temporary adhesive material being used for temporarily bonding support to wafer having circuit-forming front surface and back surface to be processed, including complex temporary adhesive material layer that has first temporary adhesive layer composed of thermosetting siloxane polymer layer (A), second temporary adhesive layer composed of thermosetting polymer layer (B), and third temporary adhesive layer composed of thermoplastic resin layer (C), wherein the polymer layer (A) is cured layer of composition containing (A-1) an organopolysiloxane having alkenyl group within its molecule, (A-2) an organopolysiloxane having R103SiO0.5 unit and SiO2 unit, (A-3) organohydrogenpolysiloxane having two or more Si—H groups per molecule, and (A-4) platinum-based catalyst.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: November 13, 2018
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Masahito Tanabe, Michihiro Sugo, Hiroyuki Yasuda, Shohei Tagami, Hideto Kato
  • Patent number: 10115622
    Abstract: A wafer processing laminate including support, temporary adhesive material layer laminated on the support, and wafer stacked on temporary adhesive material layer, wafer having front surface on which circuit is formed and back surface to be processed, temporary adhesive material layer including first temporary adhesive layer composed of thermoplastic resin layer (A) laminated on front surface of wafer and second temporary adhesive layer composed of thermosetting resin layer (B) laminated on first temporary adhesive layer, thermoplastic resin layer (A) being soluble in cleaning liquid (D) after processing wafer, thermosetting resin layer (B) being insoluble in cleaning liquid (D) after heat curing and capable of absorbing cleaning liquid (D) such that cleaning liquid (D) permeates into layer (B). This wafer processing laminate allows a wide selection of materials, facilitates separation and collection of processed wafer, meets requirements on various processes, and can increase productivity of thin wafers.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: October 30, 2018
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Shohei Tagami, Michihiro Sugo, Hideto Kato
  • Patent number: 10115580
    Abstract: A method for manufacturing an SOI wafer having SOI layer includes a thinning step to adjust SOI film thickness of the SOI wafer, including the steps of: (A1) measuring the SOI film thickness of the SOI wafer having the SOI layer before the thinning step; (A2) determining rotational position of the SOI wafer in the thinning step on the basis of a radial SOI film thickness distribution obtained in the measuring of the film thickness and previously determined radial stock removal distribution in the thinning step, and rotating the SOI wafer around the central axis thereof so as to bring the SOI wafer to the determined rotational position; and (A3) thinning the SOI layer of the rotated SOI wafer. The method for manufacturing the SOI wafer can produce an SOI wafer with an excellent radial film thickness uniformity of the SOI layer after the thinning step.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: October 30, 2018
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Hiroji Aga, Susumu Kuwabara
  • Patent number: 10081172
    Abstract: A method of preparing a laminate, in which the laminate has a substrate and a support plate, and is provided with a release layer capable of being altered by irradiation with infrared ray, the method including forming the release layer on only a periphery of one of the substrate and the support plate; and laminating the substrate and the support plate through the release layer and a first adhesive layer.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: September 25, 2018
    Assignee: TOKYO OHKA KOGYO CO., LTD.
    Inventors: Shingo Ishida, Takahiro Yoshioka
  • Patent number: 10014217
    Abstract: De are singulated from a wafer having a back layer by placing the wafer onto a first carrier substrate with the back layer adjacent the carrier substrate, forming singulation lines through the wafer to expose the back layer within the singulation lines, and using a plate structure to apply a pressure to the wafer to separate the back layer in the singulation lines. The pressure can be applied through the first carrier substrate proximate to the back layer, or can be applied through a second carrier substrate attached to a front side of the wafer opposite to the back layer.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: July 3, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Gordon M. Grivna
  • Patent number: 9984888
    Abstract: A semiconductor wafer having a plurality of through substrate vias (TSVs) is disclosed. The semiconductor wafer includes a stepped support ring on an outer edge of the semiconductor wafer, a usable back side region of the semiconductor wafer substantially enclosed by the stepped support ring, and the plurality of TSVs extending from a front side of the semiconductor wafer to the usable back side region of the semiconductor wafer. The stepped support ring includes a step between an outer ring and an inner ring of the stepped support ring. The semiconductor wafer further includes a back side metal on the usable back side region of the semiconductor wafer, a plurality of semiconductor devices on the front side of the semiconductor wafer, where at least one of the plurality of semiconductor devices is coupled to the back side metal through at least one of the plurality of TSVs.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: May 29, 2018
    Assignee: Newport Fab, LLC
    Inventors: David J. Howard, Hadi Jebory
  • Patent number: 9962915
    Abstract: A bonding method including an adhesive layer forming process in which a thermoplastic adhesive is applied to a substrate or a support plate and an adhesive layer is formed; a heating process in which the adhesive layer that is formed on the substrate or the support plate is heated; and a bonding process in which the substrate and the support plate are pressed against each other via the heated adhesive layer, thereby bonding the substrate and the support plate.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: May 8, 2018
    Assignee: TOKYO OHKA KOGYO CO., LTD.
    Inventors: Atsushi Miyanari, Yoshihiro Inao, Shigeru Kato, Takahiro Setaka, Shingo Ishida
  • Patent number: 9953859
    Abstract: Provided is an SOI wafer manufacturing method that allows production of an SOI wafer having a high gettering ability and a small resistance variance in a thickness direction of an active layer, at high productivity. The SOI wafer manufacturing method includes a first step of implanting light element ions to a surface of at least one of a first substrate and a second substrate to form, on the at least one of the first substrate and the second substrate, a modified layer in which the light element ions are present in solid solution, a second step of forming an oxide film on a surface of at least one of the first substrate and the second substrate, a third step of bonding the first substrate and the second substrate according to a bonding thermal processing, and a fourth step of obtaining an active layer by thinning the first substrate.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: April 24, 2018
    Assignee: SUMCO CORPORATION
    Inventor: Yoshihiro Koga
  • Patent number: 9953855
    Abstract: The invention relates to a process for transferring an active layer to a final substrate using a temporary substrate, the active layer comprises a first side having a three-dimensional surface topology, the process comprising: a first step of bonding the first side of the active layer to one side of the temporary substrate; a second step of bonding a second side of the active layer to the final substrate; and a third step of separating the active layer and the temporary substrate; the process being characterized in that the side of the temporary substrate possesses a surface topology complementary to the surface topology of the first side of the active layer, so that the surface topology of the temporary substrate encapsulates the surface topology of the first side of the active layer in the bonding first step.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: April 24, 2018
    Assignee: Soitec
    Inventor: Marcel Broekaart
  • Patent number: 9953860
    Abstract: A method of manufacturing an SOI wafer, including (a) forming a thermal oxide film on an SOI layer of an SOI wafer by a heat treatment under an oxidizing gas atmosphere, (b) measuring thickness of the SOI layer after forming the thermal oxide film, (c) performing a batch cleaning, wherein an etching amount of SOI layer is adjusted depending on thickness of the SOI layer measured in step (b) such that thickness of the SOI layer is adjusted to be thicker than a target value after etching, (d) measuring thickness of the SOI layer after batch cleaning, (e) performing a single-wafer cleaning, wherein an etching amount of the SOI layer is adjusted depending on thickness of the SOI layer measured in step (d) such that thickness of the SOI layer is adjusted to be the target value after etching, and removing the thermal oxide film formed in step (a) before or after step (b).
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: April 24, 2018
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Hiroji Aga
  • Patent number: 9938140
    Abstract: A method for manufacturing a MEMS device is disclosed. Moreover a MEMS device and a module including a MEMS device are disclosed. An embodiment includes a method for manufacturing MEMS devices includes forming a MEMS stack on a first main surface of a substrate, forming a polymer layer on a second main surface of the substrate and forming a first opening in the polymer layer and the substrate such that the first opening abuts the MEMS stack.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: April 10, 2018
    Assignee: Infineon Technologies AG
    Inventors: Alfons Dehe, Stephan Pindl, Bernhard Knott, Carsten Ahrens
  • Patent number: 9934996
    Abstract: A bonding arrangement comprising a silicone-base adhesive composition is suited for temporarily bonding a wafer to a support for wafer processing. The bonding arrangement includes a first temporary bond layer of non-silicone thermoplastic resin, and a second temporary bond layer of thermosetting silicone polymer and/or a third temporary bond layer of thermosetting siloxane-modified polymer. The second and/or third bond layer contains an antistatic agent.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: April 3, 2018
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Michihiro Sugo, Hiroyuki Yasuda, Shohei Tagami, Masahito Tanabe
  • Patent number: 9905411
    Abstract: Method for processing a semiconductor-wafer having a front surface, back surface, and chamfered-portion composed of a chamfered surface on the front surface side, a chamfered surface on the back surface side, and an end face at a peripheral end, including: mirror-polishing of each portion of the chamfered surface on the front surface side, the chamfered surface on the back surface side, the end face, and an outermost peripheral-portion on the front or back surface adjacent to the chamfered surface; wherein the end face mirror-polishing and mirror-polishing of the outermost peripheral-portion on the front or back surface are performed in one step, after step of mirror-polishing the chamfered surface on the front surface side and step of mirror-polishing the chamfered surface on the back surface side; roll-off amount of the outermost peripheral-portion on the front or back surface is adjusted by one step-performed mirror-polishing of the end face and outermost peripheral-portion.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: February 27, 2018
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Yuki Miyazawa, Takahiro Kida, Tomofumi Takano
  • Patent number: 9884979
    Abstract: The present invention is a temporary adhesion method for temporarily bonding a support and a wafer via a temporary adhesive material, including attaching the wafer to the support via the temporary adhesive material including a complex temporary adhesive material layer that consists of a thermoplastic resin layer (A) exhibiting a storage modulus E? of 1 to 500 MPa and a tensile rupture strength of 5 to 50 MPa at 25° C. and a thermosetting polymer layer (B) exhibiting a storage modulus E? of 1 to 1000 MPa and a tensile rupture strength of 1 to 50 MPa at 25° C.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: February 6, 2018
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Hiroyuki Yasuda, Michihiro Sugo, Masahito Tanabe
  • Patent number: 9855734
    Abstract: Provided is a method of treating a wafer in the state where the wafer is fixed on a support plate with an adhesive composition. Although the wafer is treated by a chemical, heating, or exothermic treatment, the method achieves sufficient adhesiveness during the step of treating a surface of the wafer and allows detachment of the support plate from the wafer without damaging the wafer or leaving the adhesive on the wafer after the wafer treating step. The method of treating a wafer of the present invention includes the steps of: fixing a wafer on a support plate via an adhesive composition containing a curable adhesive component to be crosslinked and cured by light irradiation or heating; crosslinking and curing the curable adhesive component by light irradiation or heating of the adhesive composition; treating a surface of the wafer fixed on the support plate by a chemical, heating, or exothermic treatment; and detaching the support plate from the treated wafer.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: January 2, 2018
    Assignee: SEKISUI CHEMICAL CO., LTD.
    Inventors: Takahiro Asao, Toru Tonegawa, Kozo Ueda, Hirohide Yabuguchi
  • Patent number: 9842900
    Abstract: A lattice matched epitaxial oxide interlayer is disposed between each semiconductor layer of a graded buffer layer material stack. Each lattice matched epitaxial oxide interlayer inhibits propagation of threading dislocations from one semiconductor layer of the graded buffer layer material stack into an overlying semiconductor layer of the graded buffer layer material stack. This allows for decreasing the thickness of each semiconductor layer within the graded buffer layer material stack. The topmost semiconductor layer of the graded buffer layer material stack, which is a relaxed layer, contains a lower defect density than the other semiconductor layers of the graded buffer layer material stack.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: December 12, 2017
    Assignee: International Business Machines Corporation
    Inventor: Alexander Reznicek
  • Patent number: 9831097
    Abstract: The present disclosure provides methods for etching a silicon material in a device structure in semiconductor applications. In one example, a method for etching features in a silicon material includes performing a remote plasma process formed from an etching gas mixture including HF gas without nitrogen etchants to remove a silicon material disposed on a substrate.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: November 28, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Nitin K. Ingle, Anchuan Wang, Zihui Li, Mikhail Korolik
  • Patent number: 9786592
    Abstract: An integrated circuit structure with a back side through silicon via (B/S TSV) therein and a method of forming the same is disclosed. The method includes the steps of: receiving a wafer comprising a substrate having a front side that has a conductor thereon and a back side; forming a back side through silicon via (B/S TSV) from the back side of the substrate to penetrate the substrate; and filling the back side through silicon via (B/S TSV) with a conductive material to form an electrical connection with the conductor. Thus a back side through silicon via penetrates the back side of the substrate and electrically connects to the conductor on the front side of the substrate is formed.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: October 10, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jeng-Shyan Lin, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Min-Feng Kao, Hsun-Ying Huang
  • Patent number: 9748140
    Abstract: A method for use in manufacturing semiconductor devices includes providing a wafer on a support, covering a central wafer portion of the wafer, and cutting a marginal wafer portion of the wafer from the wafer. According to an embodiment of an apparatus, the apparatus includes a support configured to support a wafer, a masking device configured to cover a central wafer portion of the wafer, and a cutting device configured to cut a marginal wafer portion of the wafer from the wafer.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: August 29, 2017
    Assignee: Infineon Technologies AG
    Inventors: Ursula Hedenig, Markus Ottowitz, Thomas Grille, Carsten von Koblinski
  • Patent number: 9748735
    Abstract: Example photoconductive devices and example methods for using photoconductive devices are described. An example method may include providing a photoconductive device having a metal-semiconductor-metal structure. The method may also include controlling, based on a first input state, illumination of the photoconductive device by a first optical beam during a time period, and controlling, based on a second input state, illumination of the photoconductive device by a second optical beam during the time period. Further, the method may include detecting an amount of current produced by the photoconductive device during the time period, and based on the detected amount of current, providing an output indicative of the first input state and the second input state. The example devices can be used individually as discrete components or in integrated circuits for memory or logic applications.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: August 29, 2017
    Assignee: The University of North Carolina at Charlotte
    Inventors: Yong Zhang, Jason Kendrick Marmon
  • Patent number: 9728457
    Abstract: A method of manufacturing a semiconductor substrate structure for use in a semiconductor substrate stack system is presented. The method includes a semiconductor substrate which includes a front-face, a backside, a bulk layer, an interconnect layer that includes a plurality of inter-metal dielectric layers sandwiched between conductive layers, a contact layer that is between the bulk layer and the interconnect layer, and a TSV structure commencing between the bulk layer and the contact layer and terminating at the backside of the substrate. The TSV structure is electrically coupled to the interconnect layer and the TSV structure is electrically coupled to a bonding pad on the backside.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: August 8, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Pin Chang, Weng-Jin Wu, Wen-Chih Chiou, Chen-Hua Yu
  • Patent number: 9682541
    Abstract: A bonding method which includes a pressing step of bonding a substrate and a support plate for supporting the substrate to each other through an adhesive layer and pressing the bonded substrate and support plate using a plate member; and, after the pressing step, a pressure adjusting step of placing the substrate and the support plate bonded to each other through the adhesive layer in an environment having higher pressure than pressure of an environment in which the pressing step is performed.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: June 20, 2017
    Assignee: TOKOY OHKA KOGYO CO., LTD.
    Inventors: Hirofumi Imai, Atsushi Kubo, Takahiro Yoshioka, Kimihiro Nakada, Shigeru Kato, Yasumasa Iwata
  • Patent number: 9685377
    Abstract: A wafer is divided into individual device chips along a plurality of scheduled division lines. A protective film is formed by coating liquid-state resin, which is hardened by irradiation of ultraviolet rays thereon, on the front face of the wafer. The protective film is hardened by irradiating ultraviolet rays upon the protective film. A protective tape is adhered on a front face of the hardened protective film. A modified layer is formed by irradiating a laser beam of a wavelength having a transparency to the wafer along the scheduled division lines with a focal point thereof positioned in the inside of the wafer. A back face of the wafer is ground while grinding water is supplied to thin the wafer to a given thickness and divide the wafer into the individual device chips along the scheduled division lines using the modified layer as a start point of the break.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: June 20, 2017
    Assignee: DISCO CORPORATION
    Inventors: Masaru Nakamura, Yuya Matsuoka
  • Patent number: 9570419
    Abstract: A semiconductor wafer and a plurality of semiconductor dies are provided. The wafer and the dies each include first electrically conductive terminals arranged on a main surface. The wafer is permanently attached to each of the semiconductor dies such that the first terminals are electrically connected to one another. At least one of the wafer and the semiconductor dies is thinned. The wafer is diced so as to form a plurality of chip-stacks, each of the chip-stacks comprising one of the semiconductor dies permanently attached to a diced wafer chip. At least one of the first terminals in the chip-stack is accessible by a second electrically conductive terminal arranged on a rear surface and electrically connected to the first terminal by an electrical connector that is internal to a semiconductor body of either the semiconductor die or the diced wafer chip of the chip-stack.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: February 14, 2017
    Assignee: Infineon Technologies AG
    Inventor: Aik Teong Tan
  • Patent number: 9530763
    Abstract: A method includes attaching a partially processed CMOS wafer to a second wafer to produce a combined wafer. The second wafer comprises a first region including a material different from silicon. The method also includes forming devices in the first region or in a second region of the combined wafer having a material different from silicon.
    Type: Grant
    Filed: April 4, 2013
    Date of Patent: December 27, 2016
    Assignee: Massachusetts Institute of Technology
    Inventor: Eugene A. Fitzgerald
  • Patent number: 9525030
    Abstract: A semiconductor device according to the embodiment comprises a base substrate; patterns on the base substrate; and an epitaxial layer on the base substrate, wherein the epitaxial layer is formed on a surface of the substrate exposed among the patterns. A method for growing a semiconductor crystal comprises the steps of cleaning a silicon carbide substrate; forming patterns on the silicon carbide substrate; and forming an epitaxial layer on the silicon carbide substrate.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: December 20, 2016
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Min Young Hwang, Seok Min Kang, Moo Seong Kim, Yeong Deuk Jo
  • Patent number: 9496130
    Abstract: The invention provides a reclaiming processing method for a delaminated wafer, by which the delaminated wafer obtained as a by-produce at the time of producing a bonded wafer is subjected to reclaiming polishing and is again available as a bond wafer or a base wafer, wherein, in the reclaiming polishing, the delaminate wafer is polished with use of a double-side polisher in a state that oxide film is not formed on a delaminated surface of the delaminated wafer and oxide film is formed on a back side which is the opposite side of the delaminated surface. As a result, the reclaiming processing method for a delaminated wafer, by which the delaminated wafer obtained as a by-product at the time of manufacturing a bonded wafer based on an ion implantation delamination method is subjected to the reclaiming polishing, which enables sufficiently improving quality.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: November 15, 2016
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Toru Ishizuka, Yuji Okubo, Takuya Sasaki, Akira Araki, Nobuhiko Noto
  • Patent number: 9496139
    Abstract: The present invention provides a method of more efficiently producing a semiconductor epitaxial wafer, which can suppress metal contamination by achieving higher gettering capability. A method of producing a semiconductor epitaxial wafer 100 according to the present invention includes a first step of irradiating a semiconductor wafer 10 with cluster ions 16 to form a modifying layer 18 formed from a constituent element of the cluster ions 16 in a surface portion 10A of the semiconductor wafer; and a second step of forming an epitaxial layer 20 on the modifying layer 18 of the semiconductor wafer 10.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: November 15, 2016
    Assignee: SUMCO Corporation
    Inventors: Takeshi Kadono, Kazunari Kurita
  • Patent number: 9481160
    Abstract: The present disclosure generally describes techniques suitable for use in the construction or recycling of composite materials. An article may comprise a thermoplastic coupled to a bonding interface layer, with a coating layer applied to the surface of the bonding interface layer. A bonding interface layer may comprise catalytic nanoparticles embedded within and/or encapsulated by one or more radiatively unstable polymers. Application of ionizing radiation to the article may release a catalyst at the bonding interface. Application of heat and/or stress to the article may enhance catalytic degradation of the remaining bonding interface and uncoupling of the thermoplastic from the coating layer. Embodiments of methods, compositions, articles and/or systems may be disclosed and claimed.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: November 1, 2016
    Assignee: Empire Technology Development LLC
    Inventor: Angele Sjong
  • Patent number: 9466532
    Abstract: The present disclosure includes micro-electro mechanical system (MEMS) structures and methods of forming the same. Substrates of the MEMS structures are bonded together by fusion bonding at high processing temperatures, which enables more complete removal of chemical species from the dielectric materials in the substrates prior to sealing cavities of the MEMS structures. Fusion bonding of MEMS structures reduces outgassing of chemical species and is compatible with the cavity formation process. The MEMS structures bonded by fusion bonding are mechanically stronger compared to eutectic bonding due to a higher bonding ratio. In addition, fusion bonding enables the formation of through substrate vias (TSVs) in the MEMS structures.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: October 11, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Hua Chu, Kuei-Sung Chang, Te-Hao Lee
  • Patent number: 9460924
    Abstract: A method for forming a semiconductor device is provided including processing a wafer having a spacer layer and a structure layer, the spacer layer is over the structure layer. The method continues including forming a first sidewall spacer from the spacer layer, forming a structure strip from the structure layer below the first sidewall spacer, forming a masking structure over and intersecting the structure strip, and forming a vertical post from the structure strip below the masking structure.
    Type: Grant
    Filed: March 26, 2007
    Date of Patent: October 4, 2016
    Assignee: Globalfoundries, Inc.
    Inventors: Witold P. Maszara, Qi Xiang
  • Patent number: 9443961
    Abstract: An integrated circuit device includes a semiconductor substrate, and a semiconductor strip extending into the semiconductor substrate. A first and a second dielectric region are on opposite sides of, and in contact with, the semiconductor strip. Each of the first dielectric region and the second dielectric region includes a first portion level with the semiconductor strip, and a second portion lower than the semiconductor strip. The second portion further includes a portion overlapped by the semiconductor strip.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: September 13, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tai-Chun Huang, Chih-Tang Peng, Chia-Wei Chang, Ming-Hua Yu, Hao-Ming Lien, Chao-Cheng Chen, Tze-Liang Lee
  • Patent number: 9419160
    Abstract: A nitride semiconductor structure is provided. The nitride semiconductor structure includes a substrate, a SiC nucleation layer, a composite buffer layer and a nitride semiconductor layer. The SiC nucleation layer is located on the substrate. The composite buffer layer is located on the SiC nucleation layer. The nitride semiconductor layer is located on the composite buffer layer. Besides, the nitride semiconductor structure is an AlN free semiconductor structure.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: August 16, 2016
    Assignee: Episil-Precision Inc.
    Inventors: Jung Hsuan, Chih-Wei Hu, Yi-Jen Chan
  • Patent number: 9412831
    Abstract: In a method of manufacturing a silicon carbide semiconductor device having a JFET, after forming a second concave portion configuring a second mesa portion, a thickness of a source region is detected by observing a pn junction between the source region and a first gate region exposed by the second concave portion. Selective etching is conducted on the basis of the detection result to form a first concave portion deeper than the thickness of the source region and configuring a first mesa portion inside of an outer peripheral region in an outer periphery of a cell region, and to make the second concave portion deeper than the second gate region.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: August 9, 2016
    Assignee: DENSO CORPORATION
    Inventors: Yuichi Takeuchi, Naohiro Sugiyama
  • Patent number: 9406818
    Abstract: A method of manufacturing chip package includes providing a semiconductor wafer having a plurality of semiconductor chips. An outer spacer and a plurality of inner spacers are formed on the semiconductor wafer. A protection lid is formed and disposed on the outer spacer and the inner spacers. A plurality of cavities is formed on each of the semiconductor chips from a lower surface thereof to expose the conductive pad disposed on the upper surface of the semiconductor chip. A plurality of conductive portions is formed and fills each of the cavities and electrically connected to each of the conductive pads. A plurality of solder balls is disposed on the lower surface and electrically connected to each of the conductive portions. The semiconductor chips are separated by cutting along a plurality of cutting lines between each of the semiconductor chips.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: August 2, 2016
    Assignee: XINTEC INC.
    Inventors: Tsang-Yu Liu, Shu-Ming Chang, Po-Han Lee
  • Patent number: 9368390
    Abstract: A method for fabricating a semiconductor apparatus including providing a first silicon substrate having a first contact, wherein providing the first silicon substrate comprises forming a silicide layer between the first silicon substrate and a first metal layer. The method further includes providing a second silicon substrate having a second contact comprising a second metal layer and placing the first contact in contact with the second contact. The method further includes heating the first and second metal layers to form a metallic alloy, whereby the metallic alloy bonds the first contact to the second contact.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: June 14, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chyi-Tsong Ni, I-Shi Wang, Hsin-Kuei Lee, Ching-Hou Su
  • Patent number: 9364862
    Abstract: A sensor assembly including one or more capacitive micromachined ultrasonic transducer (CMUT) microarray modules which are provided with a number of individual transducers. The microarray modules are arranged to simulate or orient individual transducers in a hyperbolic paraboloid geometry. The transducers/sensor are arranged in a rectangular or square matrix and are activatable individually, selectively or collectively to emit and received reflected beam signals at a frequency of between about 100 to 170 kHz.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: June 14, 2016
    Assignee: UNIVERSITY OF WINDSOR
    Inventor: Sazzadur Chowdhury
  • Patent number: 9337037
    Abstract: A method for obtaining a heterogeneous substrate intended for use in the production of a semiconductor comprises the following steps: (a) obtaining a first substrate (2) made from a type II-VI or type III-V material and a second substrate (1), each substrate being substantially planar and each substrate having a pre-determined surface area; (b) grinding a non-through recess (10) into the second substrate (1), the surface area of said recess being greater than the surface area of the first substrate, such that the first substrate can be housed in the recess; (c) depositing a bonding material (15) in the recess (10); (d) depositing the first substrate (2) in the recess (10) of the second substrate and securing the first substrate in the second substrate at a temperature below 300° C.; and (e) leveling the first and second substrates in order to obtain a heterogeneous substrate having a substantially planar face (30).
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: May 10, 2016
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Abdenacer Ait-Mani, Stephanie Huet
  • Patent number: 9330957
    Abstract: A process for assembling a first wafer and a second wafer each bevelled on their peripheries includes excavating the bevelled peripheral part of at least one first side of the first wafer to create a deposit bordering the region excavated in the material of the first wafer. The first side and a second side of the second wafer are then bonded together.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: May 3, 2016
    Assignees: STMICROELECTRONICS (CROLLES 2) SAS, COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Aomar Halimaoui, Marc Zussy
  • Patent number: 9306116
    Abstract: Methods for bonding semiconductor wafers requiring the transfer of electrical and optical signals between the bonded wafers and across the bonding interface by interfusing optical interconnects on one wafer with optical interconnects on a second wafer, interfusing electrical interconnects on one wafer with electrical interconnects on the second wafer, and interfusing a dielectric intermediary bonding layer on one wafer with the dielectric intermediary bonding layer on the second wafer to bond the wafers together with electrical interconnections and optical interconnections between the wafers. The methods are also applicable to the bonding of semiconductor wafers to provide a high density of electrical interconnects between wafers.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: April 5, 2016
    Assignee: Ostendo Technologies, Inc.
    Inventors: Hussein S. El-Ghoroury, Chih-Li Chuang, Kameshwar Yadavalli, Qian Fan