Thinning Of Semiconductor Substrate Patents (Class 438/459)
  • Patent number: 8871611
    Abstract: A method for bonding first and second wafers by molecular adhesion. The method includes placing the wafers in an environment having a first pressure (P1) greater than a predetermined threshold pressure above which initiation of bonding wave propagation is prevented, bringing the first wafer and the second wafer into alignment and contact, and spontaneously initiating the propagation of a bonding wave between the wafers after they are in contact solely by reducing the pressure within the environment to a second pressure (P2) below the threshold pressure.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: October 28, 2014
    Assignee: Soitec
    Inventor: Marcel Broekaart
  • Patent number: 8865489
    Abstract: Described herein are printable structures and methods for making, assembling and arranging electronic devices. A number of the methods described herein are useful for assembling electronic devices where one or more device components are embedded in a polymer which is patterned during the embedding process with trenches for electrical interconnects between device components. Some methods described herein are useful for assembling electronic devices by printing methods, such as by dry transfer contact printing methods. Also described herein are GaN light emitting diodes and methods for making and arranging GaN light emitting diodes, for example for display or lighting systems.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: October 21, 2014
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: John A. Rogers, Ralph Nuzzo, Hoon-sik Kim, Eric Brueckner, Sang Il Park, Rak Hwan Kim
  • Patent number: 8865520
    Abstract: The present invention provides a temporary carrier bonding and detaching process. A first surface of a semiconductor wafer is mounted on a first carrier by a first adhesive layer, and a first isolation coating disposed between the first adhesive layer and the first carrier. Then, a second carrier is mounted on the second surface of the semiconductor wafer. The first carrier is detached. Then, the first surface of the semiconductor wafer is mounted on a film frame. The second carrier is detached. The method of the present invention utilizes the second carrier to support and protect the semiconductor wafer, after which the first carrier is detached. Therefore, the semiconductor wafer will not be damaged or broken, thereby improving the yield rate of the semiconductor process. Furthermore, the simplicity of the detaching method for the first carrier allows for improvement in efficiency of the semiconductor process.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: October 21, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuo-Pin Yang, Wei-Min Hsiao, Cheng-Hui Hung
  • Publication number: 20140308801
    Abstract: Bonding of one or more semiconductor layers to a glass substrate is facilitated by depositing spin-on-glass (SOG) on the top of the semiconductor layers. The SOG is then bonded to the glass substrate, and after that, the original substrate of the semiconductor layers is removed. The resulting structure has the semiconductor layers disposed on the glass substrate with a layer of SOG sandwiched between. Bonding is always between glass and glass, and is independent of the composition of the target layers. Thus, it can provide “anything on glass”. For example, X-on-insulator (XOI), where X can be silicon, germanium, GaAs, GaN, SiC, graphene, etc. The spin-on-glass also helps with the surface roughness requirement.
    Type: Application
    Filed: April 11, 2014
    Publication date: October 16, 2014
    Applicant: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Jae Hyung Lee, Woo Shik Jung, Krishna C. Saraswat
  • Publication number: 20140306268
    Abstract: A method for obtaining a heterogeneous substrate intended for use in the production of a semiconductor comprises the following steps: (a) obtaining a first substrate (2) made from a type II-VI or type III-V material and a second substrate (1), each substrate being substantially planar and each substrate having a pre-determined surface area; (b) grinding a non-through recess (10) into the second substrate (1), the surface area of said recess being greater than the surface area of the first substrate, such that the first substrate can be housed in the recess; (c) depositing a bonding material (15) in the recess (10); (d) depositing the first substrate (2) in the recess (10) of the second substrate and securing the first substrate in the second substrate at a temperature below 300° C.; and (e) leveling the first and second substrates in order to obtain a heterogeneous substrate having a substantially planar face (30).
    Type: Application
    Filed: October 31, 2012
    Publication date: October 16, 2014
    Inventors: Abdenacer Ait-Mani, Stephanie Huet
  • Patent number: 8859390
    Abstract: A structure to prevent propagation of a crack into the active region of a 3D integrated circuit, such as a crack initiated by a flaw at the periphery of a thinned substrate layer or a bonding layer, and methods of forming the same is disclosed.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: October 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mukta G Farooq, John A Griesemer, William F Landers, Ian D Melville, Thomas M Shaw, Huilong Zhu
  • Patent number: 8859392
    Abstract: A manufacturing method of a power semiconductor includes steps of providing a first semiconductor substrate and a second semiconductor substrate, forming a metal oxide semiconductor layer on a first surface of the first semiconductor substrate, grinding a second surface of the first semiconductor substrate, forming a N-type buffer layer and a P-type injection layer on a third surface of the second semiconductor substrate through ion implanting, grinding a fourth surface of the second semiconductor substrate, and combining the second surface of the first semiconductor substrate with the third surface of the second semiconductor substrate for forming a third semiconductor substrate. As a result, the present invention achieves the advantages of enhancing the process flexibility and un-limiting the characteristics of the power semiconductor.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: October 14, 2014
    Assignee: Mosel Vitelic Inc.
    Inventor: Chien-Ping Chang
  • Patent number: 8859395
    Abstract: Techniques for processing power transistor devices are provided. In one aspect, the curvature of a power transistor device comprising a device film formed on a substrate is controlled by thinning the substrate, the device having an overall residual stress attributable at least in part to the thinning step, and applying a stress compensation layer to a surface of the device film, the stress compensation layer having a tensile stress sufficient to counterbalance at least a portion of the overall residual stress of the device. The resultant power transistor device may be part of an integrated circuit.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: October 14, 2014
    Assignee: Agere Systems LLC
    Inventors: Roger A. Fratti, Warren K. Waskiewicz
  • Patent number: 8859394
    Abstract: A method of fabricating a composite semiconductor structure includes providing an SOI substrate including a plurality of silicon-based devices, providing a compound semiconductor substrate including a plurality of photonic devices, and dicing the compound semiconductor substrate to provide a plurality of photonic dies. Each die includes one or more of the plurality of photonics devices. The method also includes providing an assembly substrate having a base layer and a device layer including a plurality of CMOS devices, mounting the plurality of photonic dies on predetermined portions of the assembly substrate, and aligning the SOI substrate and the assembly substrate. The method further includes joining the SOI substrate and the assembly substrate to form a composite substrate structure and removing at least the base layer of the assembly substrate from the composite substrate structure.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: October 14, 2014
    Assignee: Skorpios Technologies, Inc.
    Inventors: John Dallesasse, Stephen B. Krasulick, Timothy Creazzo, Elton Marchena
  • Patent number: 8853054
    Abstract: A method is provided for preparing multilayer semiconductor structures, such as silicon-on-insulator wafers, having reduced warp and bow. Reduced warp multilayer semiconductor structures are prepared by forming a dielectric structure on the exterior surfaces of a bonded pair of a semiconductor device substrate and a semiconductor handle substrate having an intervening dielectric layer therein. Forming a dielectric layer on the exterior surfaces of the bonded pair offsets stresses that may occur within the bulk of the semiconductor handle substrate due to thermal mismatch between the semiconductor material and the intervening dielectric layer as the structure cools from process temperatures to room temperatures.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: October 7, 2014
    Assignee: SunEdison Semiconductor Limited
    Inventors: Guoqiang Zhang, Jeffrey L. Libbert
  • Patent number: 8853005
    Abstract: When forming a conductive film by a method comprising sputtering after grinding the back surface of a semiconductor substrate, in order to avoid discharge from a part of an adhesive flown out at the outer periphery of the substrate, wherein the adhesive is used to fix the substrate to a support during grinding, at least the substrate end or the adhesive is removed after grinding the semiconductor substrate and before forming the conductive film, so that a gap between the substrate end and the adhesive may have a predetermined size.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: October 7, 2014
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Seiya Fujii
  • Patent number: 8853544
    Abstract: Various aspects of the present invention provide a transfer method for peeling off an MIM structure (comprising lower electrode/dielectric layer/upper electrodes) film formed on a supporting substrate and then transferring onto a transfer substrate with sufficiently uniform and low damage. Various aspects of the present invention also provide a thin film element provided with one or more thin film components which are transferred onto a substrate by using said method.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: October 7, 2014
    Assignee: Taiyo Yuden Co., Ltd.
    Inventors: Ryuichi Kondou, Kenichi Ota
  • Publication number: 20140287567
    Abstract: According to one embodiment, a first adhesive layer is formed on one major surface of a first substrate. The first substrate and a second substrate are adhered using a second adhesive layer that has thermosetting properties and covers the first adhesive layer, wherein a bonding strength between the second substrate is greater than a bonding strength between the second substrate and the first adhesive layer. The other major surface of the first substrate is polished, and the first substrate is thinned. A physical force is then applied to peripheral parts of the second adhesive layer, and a circular notched part is formed along the outer perimeter of the second adhesive layer to separate the first substrate and the second substrate at the interface between the first adhesive layer and the second adhesive layer.
    Type: Application
    Filed: August 30, 2013
    Publication date: September 25, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Eiji TAKANO
  • Patent number: 8841201
    Abstract: A method for fabricating a semiconductor device is disclosed. A first substrate is arranged over a second substrate. A wafer bonding process is performed on the semiconductor device. First regions of the device are enclosed by the bonding process. Second regions of the device remain exposed. One or more processes are performed on the exposed second regions, after performing the wafer bonding process. The one or more processes include a fill process that forms a fill material within the exposed second regions. An edge seal material is applied on the first and second substrates after performing the one or more processes.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: September 23, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Chuan Teng, Jung-Huei Peng, Shang-Ying Tsai, Hsin-Ting Huang, Lin-Min Hung, Yao-Te Huang, Chin-Yi Cho
  • Patent number: 8841742
    Abstract: Methods of transferring a layer of semiconductor material from a first donor structure to a second structure include forming recesses in the donor structure, implanting ions into the donor structure to form a generally planar, inhomogeneous weakened zone therein, and providing material within the recesses. The first donor structure may be bonded to a second structure, and the first donor structure may be fractured along the generally planar weakened zone, leaving the layer of semiconductor material bonded to the second structure. Semiconductor devices may be fabricated by forming active device structures on the transferred layer of semiconductor material. Semiconductor structures are fabricated using the described methods.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: September 23, 2014
    Assignee: Soitec
    Inventors: Mariam Sadaka, Ionut Radu
  • Patent number: 8835221
    Abstract: An integrated chip package structure and method of manufacturing the same is by adhering dies on a ceramic substrate and forming a thin-film circuit layer on top of the dies and the ceramic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: September 16, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Jin-Yaun Lee, Mou-Shiung Lin, Ching-Cheng Huang
  • Patent number: 8836033
    Abstract: Embodiments of a method and apparatus for removing metallic nanotubes without transferring CNTs from one substrate to another substrate provide two methods of transferring a thin layer of crystalline ST-cut quartz wafer to the surface of a carrier silicon wafer for subsequent CNT growth, without resorting to CNT transfer. In other words, embodiments of a method and apparatus allow CNTs to be grown on the same substrate that metallic nanotube removal is performed, therefore eliminating the costly and messy step of transferring CNTs from one substrate to another. This is achieved through a residual thin layer of crystalline ST-cut quartz layer on a silicon wafer. The ST-cut quartz wafer promotes aligned growth of CNTs, while the underlying silicon wafer allows backgate burnout.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: September 16, 2014
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Silai Krishnaswamy, Joseph Payne, Jeffrey Hartman
  • Patent number: 8835222
    Abstract: A method for producing a two-chip assembly includes: providing a wafer having a first thickness, which wafer has a front side and a back side, a first plurality of first chips being provided on the front side of the wafer; attaching a second plurality of second chips on the front side of the wafer, so that every first chip is joined in each instance to a second chip and forms a corresponding two-chip pair; forming a cohesive mold package on the front side of the wafer, so that the second chips are packaged; thinning the wafer from the back side to a second thickness which is less than the first thickness; forming vias from the back side to the second chips; and separating the two-chip pairs into corresponding two-chip assemblies.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: September 16, 2014
    Assignee: Robert Bosch GmbH
    Inventors: Mathias Bruendel, Frieder Haag, Jens Frey, Rolf Speicher, Juergen Fritz, Lutz Rauscher
  • Publication number: 20140252555
    Abstract: According to one embodiment, a substrate for forming elements includes a substrate; an insulating film provided on the substrate; and a Ge layer or an SiGe layer bonded to the substrate via the insulating film. The insulating film is a laminated structure comprising a plurality of films including an oxide film, a high-dielectric constant insulating film, and a compound insulating film including a metal element and Ge.
    Type: Application
    Filed: May 16, 2014
    Publication date: September 11, 2014
    Inventor: Keiji IKEDA
  • Patent number: 8828785
    Abstract: Techniques for producing a single-crystal phase change material and the incorporation of those techniques in an electronic device fabrication process flow are provided. In one aspect, a method of fabricating an electronic device is provided which includes the following steps. A single-crystal phase change material is formed on a first substrate. At least one first electrode in contact with a first side of the single-crystal phase change material is formed. The single-crystal phase change material and the at least one first electrode in contact with the first side of the single-crystal phase change material form a transfer structure on the first substrate. The transfer structure is transferred to a second substrate. At least one second electrode in contact with a second side of the single-crystal phase change material is formed. A single-crystal phase change material-containing structure and electronic device are also provided.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Guy Cohen, Simone Raoux
  • Patent number: 8830413
    Abstract: The present invention provides a simplifying method for a peeling process as well as peeling and transcribing to a large-size substrate uniformly. A feature of the present invention is to peel a first adhesive and to cure a second adhesive at the same time in a peeling process, thereby to simplify a manufacturing process. In addition, the present invention is to devise the timing of transcribing a peel-off layer in which up to an electrode of a semiconductor are formed to a predetermined substrate. In particular, a feature is that peeling is performed by using a pressure difference in the case that peeling is performed with a state in which plural semiconductor elements are formed on a large-size substrate.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: September 9, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Takayama, Junya Maruyama, Yuugo Goto, Yumiko Ohno
  • Patent number: 8822306
    Abstract: According to an embodiment, a composite wafer includes a carrier substrate having a graphite layer and a monocrystalline semiconductor layer attached to the carrier substrate.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: September 2, 2014
    Assignee: Infineon Technologies AG
    Inventors: Rudolf Berger, Hermann Gruber, Wolfgang Lehnert, Guenther Ruhl, Raimund Foerg, Anton Mauder, Hans-Joachim Schulze, Karsten Kellermann, Michael Sommer, Christian Rottmair, Roland Rupp
  • Publication number: 20140242779
    Abstract: According to one embodiment, a semiconductor device manufacturing method includes: bonding a first wafer and a second wafer to each other, to form a stack; rubbing a film attached with a fill material in a thin-film shape into a gap located between a bevel of the first wafer and a bevel of the second wafer, to fill the gap with the fill material; and thinning the first wafer.
    Type: Application
    Filed: July 30, 2013
    Publication date: August 28, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenro NAKAMURA, Mitsuyoshi ENDO, Kazuyuki HIGASHI, Takashi SHIRONO
  • Patent number: 8815651
    Abstract: A method for manufacturing an electronic interconnect device is described, the method comprising: providing an electronic members each having one or more electrical contacts on a first member side thereof; providing a carrier having a carrier base and having sets of one or more electrically conductive projections on a surface of the carrier base; attaching the electronic members with the corresponding contacts thereof to the respective set of projections to thereby electrically connect the one or more electrical contacts of the respective chip with the corresponding one or more electrically conductive projections of the respective set; encapsulating exposed portions of the electronic member with an encapsulating material to form an encapsulation.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: August 26, 2014
    Assignee: Infineon Technologies AG
    Inventors: Edward Fuergut, Joachim Mahler
  • Patent number: 8815641
    Abstract: A method and structure for a semiconductor device including a thin nitride layer formed between a diamond SOI layer and device silicon layer to block diffusion of ions and improve lifetime of the device silicon.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: August 26, 2014
    Assignee: Soitec
    Inventors: Rick C. Jerome, Francois Hebert, Craig McLachlan, Kevin Hoopingarner
  • Patent number: 8809164
    Abstract: Methods for detecting the physical layout of an integrated circuit are provided. The methods of the present disclosure allow large area imaging of the circuit layout without requiring tedious sample preparation techniques. The imaging can be performed utilizing low-energy beam techniques such as scanning electron microscopy; however, more sophisticated imaging techniques can also be employed. In the methods of the present disclosure, spalling is used to remove a portion of a semiconductor layer including at least one semiconductor device formed thereon or therein from a base substrate. In some cases, a buried insulator layer that is located beneath a semiconductor layer including the at least one semiconductor device can be completely or partially removed. In some cases, the semiconductor layer including the at least one semiconductor device can be thinned. The methods improve the detection quality that the buried insulator layer and a thick semiconductor layer can reduce.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: August 19, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Bahman Hekmatshoartabari, Ali Khakifirooz, John A. Ott, Ghavam G. Shahidi, Davood Shahrjerdi
  • Publication number: 20140225229
    Abstract: A group III nitride composite substrate includes a group III nitride film and a support substrate formed from a material different in chemical composition from the group III nitride film. The group III nitride film has a thickness of 10 ?m or more. A sheet resistance of a-group III-nitride-film-side main surface of the group III nitride composite substrate is 200 ?/sq or less. A method for manufacturing a group III nitride composite substrate includes the steps of bonding the group III nitride film and the support substrate to each other; and reducing the thickness of at least one of the group III nitride film and the support substrate bonded to each other. Accordingly, a group III nitride composite substrate of a low sheet resistance that is obtained with a high yield as well as a method for manufacturing the same are provided.
    Type: Application
    Filed: December 5, 2013
    Publication date: August 14, 2014
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Akihiro HACHIGO, Keiji ISHIBASHI, Naoki MATSUMOTO
  • Patent number: 8802542
    Abstract: The invention pertains to a combination of a substrate and a wafer, wherein the substrate and the wafer are arranged parallel to one another and bonded together with the aid of an adhesive layer situated between the substrate and the wafer, and wherein the adhesive is chosen such that its adhesive properties are neutralized or at least diminished when a predetermined temperature is exceeded. According to the invention, the adhesive layer is only applied annularly between the substrate and the wafer in the edge region of the wafer.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: August 12, 2014
    Inventor: Erich Thallner
  • Patent number: 8802457
    Abstract: A method includes performing a grinding to a backside of a semiconductor substrate, wherein a remaining portion of the semiconductor substrate has a back surface. A treatment is then performed on the back surface using a method selected from the group consisting essentially of a dry treatment and a plasma treatment. Process gases that are used in the treatment include oxygen (O2). The plasma treatment is performed without vertical bias in a direction perpendicular to the back surface.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: August 12, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yu Lai, Cheng-Ta Wu, Kai-Chun Hsu, Yeur-Luen Tu, Ching-Chun Wang, Chia-Shiung Tsai
  • Patent number: 8802541
    Abstract: A low temperature wafer bonding method and a bonded structure are provided. The method includes: providing a first substrate having a plurality of metal pads and a first dielectric layer close to the metal pads, where the metal pads and the first dielectric layer are on a top surface of the first substrate; providing a second substrate having a plurality of semiconductor pads and a second dielectric layer close to the semiconductor pads, where the semiconductor pads and the second dielectric layer are on a top surface of the second substrate; disposing at least one of the metal pads in direct contact with at least one of the semiconductor pads, and disposing the first dielectric layer in direct contact with the second dielectric layer; and bonding the metal pads with the semiconductor pads, and bonding the first dielectric layer with the second dielectric layer.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: August 12, 2014
    Assignee: Lexvu Opto Microelectronics Technology (Shanghai) Ltd.
    Inventors: Zhiwei Wang, Jianhong Mao, Lei Zhang, Deming Tang
  • Patent number: 8802540
    Abstract: The present invention provides a method of manufacturing a bonded wafer. The method includes ozone washing two silicon wafers to form an oxide film equal to or less than 2.2 nm in thickness on each surface of the two silicon wafers, and bonding the two silicon wafers through the oxide films formed to obtain a bonded wafer.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: August 12, 2014
    Assignee: Sumco Corporation
    Inventors: Nobuyuki Morimoto, Akihiko Endo
  • Publication number: 20140217478
    Abstract: CMOS Ultrasonic Transducers and processes for making such devices are described. The processes may include forming cavities on a first wafer and bonding the first wafer to a second wafer. The second wafer may be processed to form a membrane for the cavities. Electrical access to the cavities may be provided.
    Type: Application
    Filed: February 4, 2014
    Publication date: August 7, 2014
    Applicant: Butterfly Network, Inc.
    Inventors: Jonathan M. Rothberg, Kieth G. Fife, Tyler S. Ralston, Gregory L. Charvat, Nevada J. Sanchez
  • Patent number: 8796076
    Abstract: After formation of an opening by exposing and development of the photosensitive surface protection film and adhesive layer which is formed on the circuit side of the semiconductor wafer, the semiconductor chips having a photosensitive surface protection film and adhesive layer thereon is fabricated by cutting individual chips from the semiconductor wafer. After the second semiconductor chip is placed over the first semiconductor chip up by the suction collet, the second semiconductor chip is bonded with the first semiconductor chip by the first surface protection film and adhesive layer. The suction side of the suction collet has lower adhesion to the second semiconductor chip than that between the now bonded semiconductor chips.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: August 5, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Yoshimura, Shoko Omizo
  • Publication number: 20140213039
    Abstract: Methods processing substrates are provided. The method may include providing a bonding layer between a substrate and a carrier to bond the substrate to the carrier, processing the substrate while the substrate is supported by the carrier, and removing the bonding layer to separate the substrate from the carrier. The bonding layer may include a thermosetting glue layer and thermosetting release layers provided on opposing sides of the thermosetting glue layer.
    Type: Application
    Filed: January 9, 2014
    Publication date: July 31, 2014
    Inventors: Chungsun LEE, Jung-Hwan KIM, Kwang-chul CHOI, Un-Byoung KANG, Jeon Il LEE
  • Patent number: 8790996
    Abstract: Methods of processing a device substrate are disclosed herein. In one embodiment, a method of processing a device substrate can include bonding a first surface of a device substrate to a carrier with a polymeric material. The device substrate may have a plurality of first openings extending from the first surface towards a second surface of the device substrate opposite from the first surface. Then, material can be removed at the second surface of the device substrate, wherein at least some of the first openings communicate with the second surface at least one of before or after performing the removal of the material. Then, at least a portion of the polymeric material disposed between the first surface and the carrier substrate can be exposed to a substance through at least some first openings to debond the device substrate from the carrier substrate.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: July 29, 2014
    Assignee: Invensas Corporation
    Inventor: Pezhman Monadgemi
  • Patent number: 8785249
    Abstract: Aspects and examples include electrical components and methods of forming electrical components. In one example, a method includes selecting a substrate, forming a pattern of a first conductive material on a top surface of the substrate, forming a pattern of a second conductive material on a bottom surface of the substrate, dicing the substrate into one or more die having a first diced surface and a second diced surface, securing the first diced surface of each of the one or more die to a retaining material, encapsulating the one or more die in an encapsulent to form a reconstituted wafer, and forming a pattern of a third conductive material on the second diced surface by metalizing a surface of the reconstituted wafer.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: July 22, 2014
    Assignee: The Charles Stark Draper Laboratory, Inc.
    Inventor: Maurice Karpman
  • Patent number: 8785229
    Abstract: Methods of forming micromechanical resonators include forming first and second substrates having first and second semiconductor layers of first and second conductivity type therein, respectively. The first semiconductor layer of first conductivity type is bonded to the second semiconductor layer of second conductivity type to thereby define a first rectifying junction at an interface of the bonded semiconductor layers. A piezoelectric layer is formed on the first rectifying junction and at least a first electrode is formed on the piezoelectric layer.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: July 22, 2014
    Assignee: Integrated Device Technology, inc.
    Inventor: Wanling Pan
  • Patent number: 8785293
    Abstract: The invention relates to a method of adapting the lattice parameter of a seed layer of a strained material, comprising the following successive steps: a) a structure is provided that has a seed layer of strained material, of lattice parameter A1, of nominal lattice parameter An and of thermal expansion coefficient CTE3, a low-viscosity layer and an intermediate substrate of thermal expansion coefficient CTE1; b) a heat treatment is applied so as to relax the seed layer of strained material; and c) the seed layer is transferred onto a support substrate of thermal expansion coefficient CTE5, the intermediate substrate and the support substrate being chosen so that A1<An and CTE1?CTE3 and CTE5>CTE1 or A1>An and CTE1?CTE3 and CTE5<CTE1.
    Type: Grant
    Filed: February 15, 2010
    Date of Patent: July 22, 2014
    Assignee: SOITEC
    Inventors: Pascal Guenard, Frederic Dupont
  • Patent number: 8785297
    Abstract: A method for encapsulating electronic components, including the steps of: forming, in a first surface of a semiconductor wafer, electronic components; forming, on the first surface, an interconnection stack including conductive tracks and vias separated by an insulating material; forming first and second bonding pads on the interconnection stack; thinning down the wafer, except at least on its contour; filling the thinned-down region with a first resin layer; arranging at least one first chip on the first bonding pads and forming solder bumps on the second bonding pads; depositing a second resin layer covering the first chips and partially covering the solder bumps; bonding an adhesive strip on the first resin layer; and scribing the structure into individual chips.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: July 22, 2014
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Marc Feron, Vincent Jarry, Laurent Barreau
  • Patent number: 8785296
    Abstract: A packaging method with backside wafer dicing includes the steps of forming a support structure at the front surface of the wafer then depositing a metal layer on a center area of the backside of the wafer after grinding the wafer backside to reduce the wafer thickness; detecting from the backside of the wafer sections of scribe lines formed in the front surface in the region between the edge of the metal layer and the edge of the wafer and cutting the wafer and the metal layer from the wafer backside along a straight line formed by extending a scribe line section detected from the wafer backside.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: July 22, 2014
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Yan Xun Xue, Ping Huang, Yueh-Se Ho
  • Patent number: 8778771
    Abstract: A method of manufacturing a semiconductor device includes steps of providing a substrate including a semiconductor portion, a non-porous semiconductor layer, and a porous semiconductor layer arranged between the semiconductor portion and the non-porous semiconductor layer, forming a porous oxide layer by oxidizing the porous semiconductor layer, forming a bonded substrate by bonding a supporting substrate to a surface, on a side of the non-porous semiconductor layer, of the substrate on which the porous oxide layer is formed, and separating the semiconductor portion from the bonded substrate by utilizing the porous oxide layer.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: July 15, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kazuo Kokumai
  • Patent number: 8778778
    Abstract: According to an embodiment, an active layer is formed on a first surface of a semiconductor substrate, a wiring layer is formed on the active layer, and an insulating layer is formed covering the wiring layer. The first surface of the semiconductor substrate is bonded to a support substrate via the insulating layer, and the semiconductor substrate bonded to the support substrate is thinned leaving the semiconductor substrate having a predetermined thickness which covers the active layer from a second surface. At least a part of area of the thinned semiconductor substrate is removed to expose the active layer.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: July 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumasa Tanida, Masahiro Sekiguchi, Masayuki Dohi, Tsuyoshi Matsumura, Hideo Numata, Mari Otsuka, Naoko Yamaguchi, Takashi Shirono, Satoshi Hongo
  • Patent number: 8778735
    Abstract: A WLCSP method comprises: depositing a metal bump on bonding pads of chips; forming a first packaging layer at front surface of wafer to cover metal bumps while forming an un-covered ring at the edge of wafer to expose the ends of each scribe line located between two adjacent chips; thinning first packaging layer to expose metal bumps; forming a groove on front surface of first packaging layer along each scribe line by cutting along a straight line extended by two ends of scribe line exposed on front surface of un-covered ring; grinding back surface of wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal layer at bottom surface of wafer in recessed space; cutting off the edge portion of wafer; and separating individual chips from wafer by cutting through first packaging layer, the wafer and metal layer along groove.
    Type: Grant
    Filed: June 29, 2013
    Date of Patent: July 15, 2014
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Yan Xun Xue, Hamza Yilmaz, Yueh-Se Ho, Jun Lu, Ping Huang, Lei Shi, Lei Duan, Yuping Gong
  • Publication number: 20140191373
    Abstract: A composite wafer 10 includes a supporting substrate 12 and a semiconductor substrate 14 which are bonded to each other by direct bonding. The supporting substrate 12 is a translucent alumina substrate with an alumina purity of 99% or more. The linear transmittance of the supporting substrate 12 at the visible light range is 40% or less. Furthermore, the total light transmittance from the front at a wavelength of 200 to 250 nm of the supporting substrate 12 is 60% or more. The average crystal grain size of the supporting substrate 12 is 10 to ?m. The semiconductor substrate 14 is a single crystal silicon substrate. Such a composite wafer 10 has insulation performance and thermal conduction comparable to those of a SOS wafer, can be manufactured at low cost, and can be easily made to have a large diameter.
    Type: Application
    Filed: January 27, 2014
    Publication date: July 10, 2014
    Applicant: NGK INSULATORS, LTD.
    Inventors: Yasunori Iwasaki, Akiyoshi Ide, Yuji Hori, Tomoyoshi Tai, Sugio Miyazawa
  • Patent number: 8772132
    Abstract: A method of manufacturing a laminated wafer is provided by forming a silicon film layer on a surface of an insulating substrate comprising the steps in the following order of: applying a surface activation treatment to both a surface of a silicon wafer or a silicon wafer to which an oxide film is layered and a surface of the insulating substrate followed by laminating in an atmosphere of temperature exceeding 50° C. and lower than 300° C., applying a heat treatment to a laminated wafer at a temperature of 200° C. to 350° C., and thinning the silicon wafer by a combination of grinding, etching and polishing to form a silicon film layer.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: July 8, 2014
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Shoji Akiyama, Yoshihiro Kubota, Atsuo Ito, Makoto Kawai, Kouichi Tanaka, Yuji Tobisaka, Yoshihiro Nojima
  • Patent number: 8765576
    Abstract: A method of manufacturing a laminated substrate is provided. The method includes: forming an oxide film on at least a surface of a first substrate having a hardness of equal to or more than 150 GPa in Young's modulus, and then smoothing the oxide film; implanting hydrogen ions or rare gas ions, or mixed gas ions thereof from a surface of a second substrate to form an ion-implanted layer inside the substrate, laminating the first substrate and the second substrate through at least the oxide film, and then detaching the second substrate in the ion-implanted layer to form a laminated substrate; heat-treating the laminated substrate and diffusing outwardly the oxide film.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: July 1, 2014
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Shoji Akiyama, Atsuo Ito, Yoshihiro Kubota, Koichi Tanaka, Makoto Kawai, Yuuji Tobisaka
  • Patent number: 8765578
    Abstract: A method of edge protecting bonded semiconductor wafers. A second semiconductor wafer and a first semiconductor wafer are attached by a bonding layer/interface and the second semiconductor wafer undergoes a thinning process. As a part of the thinning process, a first protective layer is applied to the edges of the second and first semiconductor wafers. A third semiconductor wafer is attached to the second semiconductor wafer by a bonding layer/interface and the third semiconductor wafer undergoes a thinning process. As a part of the thinning process, a second protective layer is applied to the edges of the third semiconductor wafer and over the first protective layer. The first, second and third semiconductor wafers form a wafer stack. The wafer stack is diced into a plurality of 3D chips while maintaining the first and second protective layers.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Douglas C. La Tulipe, Jr., Spyridon Skordas, Tuan A. Vo, Kevin R. Winstel
  • Patent number: 8765579
    Abstract: A semiconductor wafer has a device area where a plurality of semiconductor devices are respectively formed in a plurality of regions partitioned by a plurality of crossing division lines formed on the front side of the semiconductor wafer and a peripheral area surrounding the device area. The back side of the semiconductor wafer corresponding to the device area is ground to thereby form a circular recess and an annular projection surrounding the circular recess. In a chip stacked wafer forming step, a plurality of semiconductor device chips are provided on the bottom surface of the circular recess of the semiconductor wafer at the positions respectively corresponding to the semiconductor devices of the semiconductor wafer. The chip stacked wafer is ground to reduce the thickness of each semiconductor device chip to a finished thickness, and a through electrode is formed in each semiconductor device of the semiconductor wafer.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: July 1, 2014
    Assignee: Disco Corporation
    Inventors: Youngsuk Kim, Shigenori Harada
  • Patent number: 8759229
    Abstract: A method for manufacturing an epitaxial wafer that can reduce occurrence of a surface defect or a slip formed on an epitaxial layer is provided. The manufacturing method is characterized by comprising: a smoothing step of controlling application of an etchant to a wafer surface in accordance with a surface shape of a silicon wafer to smooth the wafer surface; and an epitaxial layer forming step of forming an epitaxial layer formed of a silicon single crystal on the surface of the wafer based on epitaxial growth.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: June 24, 2014
    Assignee: Sumco Corporation
    Inventors: Sakae Koyata, Kazushige Takaishi, Tomohiro Hashii, Katsuhiko Murayama, Takeo Katoh
  • Patent number: 8753913
    Abstract: A method for fabricating an integrated device, the method including, overlying a first crystalline layer onto a second crystalline layer to form a combined layer, wherein one of the first and second crystalline layers is an image sensor layer and at least one of the first and second crystalline layers has been transferred by performing an atomic species implantation, and wherein at least one of the first and second crystalline layers includes single crystal transistors.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: June 17, 2014
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar