Abstract: The present disclosure provides methods for etching a silicon material in a device structure in semiconductor applications. In one example, a method for etching features in a silicon material includes performing a remote plasma process formed from an etching gas mixture including HF gas without nitrogen etchants to remove a silicon material disposed on a substrate.

Abstract: An integrated circuit structure with a back side through silicon via (B/S TSV) therein and a method of forming the same is disclosed. The method includes the steps of: receiving a wafer comprising a substrate having a front side that has a conductor thereon and a back side; forming a back side through silicon via (B/S TSV) from the back side of the substrate to penetrate the substrate; and filling the back side through silicon via (B/S TSV) with a conductive material to form an electrical connection with the conductor. Thus a back side through silicon via penetrates the back side of the substrate and electrically connects to the conductor on the front side of the substrate is formed.

Abstract: A method for use in manufacturing semiconductor devices includes providing a wafer on a support, covering a central wafer portion of the wafer, and cutting a marginal wafer portion of the wafer from the wafer. According to an embodiment of an apparatus, the apparatus includes a support configured to support a wafer, a masking device configured to cover a central wafer portion of the wafer, and a cutting device configured to cut a marginal wafer portion of the wafer from the wafer.

Abstract: Example photoconductive devices and example methods for using photoconductive devices are described. An example method may include providing a photoconductive device having a metal-semiconductor-metal structure. The method may also include controlling, based on a first input state, illumination of the photoconductive device by a first optical beam during a time period, and controlling, based on a second input state, illumination of the photoconductive device by a second optical beam during the time period. Further, the method may include detecting an amount of current produced by the photoconductive device during the time period, and based on the detected amount of current, providing an output indicative of the first input state and the second input state. The example devices can be used individually as discrete components or in integrated circuits for memory or logic applications.

Abstract: A method of manufacturing a semiconductor substrate structure for use in a semiconductor substrate stack system is presented. The method includes a semiconductor substrate which includes a front-face, a backside, a bulk layer, an interconnect layer that includes a plurality of inter-metal dielectric layers sandwiched between conductive layers, a contact layer that is between the bulk layer and the interconnect layer, and a TSV structure commencing between the bulk layer and the contact layer and terminating at the backside of the substrate. The TSV structure is electrically coupled to the interconnect layer and the TSV structure is electrically coupled to a bonding pad on the backside.

Abstract: A wafer is divided into individual device chips along a plurality of scheduled division lines. A protective film is formed by coating liquid-state resin, which is hardened by irradiation of ultraviolet rays thereon, on the front face of the wafer. The protective film is hardened by irradiating ultraviolet rays upon the protective film. A protective tape is adhered on a front face of the hardened protective film. A modified layer is formed by irradiating a laser beam of a wavelength having a transparency to the wafer along the scheduled division lines with a focal point thereof positioned in the inside of the wafer. A back face of the wafer is ground while grinding water is supplied to thin the wafer to a given thickness and divide the wafer into the individual device chips along the scheduled division lines using the modified layer as a start point of the break.

Abstract: A bonding method which includes a pressing step of bonding a substrate and a support plate for supporting the substrate to each other through an adhesive layer and pressing the bonded substrate and support plate using a plate member; and, after the pressing step, a pressure adjusting step of placing the substrate and the support plate bonded to each other through the adhesive layer in an environment having higher pressure than pressure of an environment in which the pressing step is performed.

Abstract: A semiconductor wafer and a plurality of semiconductor dies are provided. The wafer and the dies each include first electrically conductive terminals arranged on a main surface. The wafer is permanently attached to each of the semiconductor dies such that the first terminals are electrically connected to one another. At least one of the wafer and the semiconductor dies is thinned. The wafer is diced so as to form a plurality of chip-stacks, each of the chip-stacks comprising one of the semiconductor dies permanently attached to a diced wafer chip. At least one of the first terminals in the chip-stack is accessible by a second electrically conductive terminal arranged on a rear surface and electrically connected to the first terminal by an electrical connector that is internal to a semiconductor body of either the semiconductor die or the diced wafer chip of the chip-stack.

Abstract: A method includes attaching a partially processed CMOS wafer to a second wafer to produce a combined wafer. The second wafer comprises a first region including a material different from silicon. The method also includes forming devices in the first region or in a second region of the combined wafer having a material different from silicon.

Abstract: A semiconductor device according to the embodiment comprises a base substrate; patterns on the base substrate; and an epitaxial layer on the base substrate, wherein the epitaxial layer is formed on a surface of the substrate exposed among the patterns. A method for growing a semiconductor crystal comprises the steps of cleaning a silicon carbide substrate; forming patterns on the silicon carbide substrate; and forming an epitaxial layer on the silicon carbide substrate.

Abstract: The present invention provides a method of more efficiently producing a semiconductor epitaxial wafer, which can suppress metal contamination by achieving higher gettering capability. A method of producing a semiconductor epitaxial wafer 100 according to the present invention includes a first step of irradiating a semiconductor wafer 10 with cluster ions 16 to form a modifying layer 18 formed from a constituent element of the cluster ions 16 in a surface portion 10A of the semiconductor wafer; and a second step of forming an epitaxial layer 20 on the modifying layer 18 of the semiconductor wafer 10.

Abstract: The invention provides a reclaiming processing method for a delaminated wafer, by which the delaminated wafer obtained as a by-produce at the time of producing a bonded wafer is subjected to reclaiming polishing and is again available as a bond wafer or a base wafer, wherein, in the reclaiming polishing, the delaminate wafer is polished with use of a double-side polisher in a state that oxide film is not formed on a delaminated surface of the delaminated wafer and oxide film is formed on a back side which is the opposite side of the delaminated surface. As a result, the reclaiming processing method for a delaminated wafer, by which the delaminated wafer obtained as a by-product at the time of manufacturing a bonded wafer based on an ion implantation delamination method is subjected to the reclaiming polishing, which enables sufficiently improving quality.

Abstract: The present disclosure generally describes techniques suitable for use in the construction or recycling of composite materials. An article may comprise a thermoplastic coupled to a bonding interface layer, with a coating layer applied to the surface of the bonding interface layer. A bonding interface layer may comprise catalytic nanoparticles embedded within and/or encapsulated by one or more radiatively unstable polymers. Application of ionizing radiation to the article may release a catalyst at the bonding interface. Application of heat and/or stress to the article may enhance catalytic degradation of the remaining bonding interface and uncoupling of the thermoplastic from the coating layer. Embodiments of methods, compositions, articles and/or systems may be disclosed and claimed.

Abstract: The present disclosure includes micro-electro mechanical system (MEMS) structures and methods of forming the same. Substrates of the MEMS structures are bonded together by fusion bonding at high processing temperatures, which enables more complete removal of chemical species from the dielectric materials in the substrates prior to sealing cavities of the MEMS structures. Fusion bonding of MEMS structures reduces outgassing of chemical species and is compatible with the cavity formation process. The MEMS structures bonded by fusion bonding are mechanically stronger compared to eutectic bonding due to a higher bonding ratio. In addition, fusion bonding enables the formation of through substrate vias (TSVs) in the MEMS structures.

Abstract: A method for forming a semiconductor device is provided including processing a wafer having a spacer layer and a structure layer, the spacer layer is over the structure layer. The method continues including forming a first sidewall spacer from the spacer layer, forming a structure strip from the structure layer below the first sidewall spacer, forming a masking structure over and intersecting the structure strip, and forming a vertical post from the structure strip below the masking structure.

Abstract: An integrated circuit device includes a semiconductor substrate, and a semiconductor strip extending into the semiconductor substrate. A first and a second dielectric region are on opposite sides of, and in contact with, the semiconductor strip. Each of the first dielectric region and the second dielectric region includes a first portion level with the semiconductor strip, and a second portion lower than the semiconductor strip. The second portion further includes a portion overlapped by the semiconductor strip.

Abstract: A nitride semiconductor structure is provided. The nitride semiconductor structure includes a substrate, a SiC nucleation layer, a composite buffer layer and a nitride semiconductor layer. The SiC nucleation layer is located on the substrate. The composite buffer layer is located on the SiC nucleation layer. The nitride semiconductor layer is located on the composite buffer layer. Besides, the nitride semiconductor structure is an AlN free semiconductor structure.

Abstract: In a method of manufacturing a silicon carbide semiconductor device having a JFET, after forming a second concave portion configuring a second mesa portion, a thickness of a source region is detected by observing a pn junction between the source region and a first gate region exposed by the second concave portion. Selective etching is conducted on the basis of the detection result to form a first concave portion deeper than the thickness of the source region and configuring a first mesa portion inside of an outer peripheral region in an outer periphery of a cell region, and to make the second concave portion deeper than the second gate region.

Abstract: A method of manufacturing chip package includes providing a semiconductor wafer having a plurality of semiconductor chips. An outer spacer and a plurality of inner spacers are formed on the semiconductor wafer. A protection lid is formed and disposed on the outer spacer and the inner spacers. A plurality of cavities is formed on each of the semiconductor chips from a lower surface thereof to expose the conductive pad disposed on the upper surface of the semiconductor chip. A plurality of conductive portions is formed and fills each of the cavities and electrically connected to each of the conductive pads. A plurality of solder balls is disposed on the lower surface and electrically connected to each of the conductive portions. The semiconductor chips are separated by cutting along a plurality of cutting lines between each of the semiconductor chips.

Abstract: A sensor assembly including one or more capacitive micromachined ultrasonic transducer (CMUT) microarray modules which are provided with a number of individual transducers. The microarray modules are arranged to simulate or orient individual transducers in a hyperbolic paraboloid geometry. The transducers/sensor are arranged in a rectangular or square matrix and are activatable individually, selectively or collectively to emit and received reflected beam signals at a frequency of between about 100 to 170 kHz.

Abstract: A method for fabricating a semiconductor apparatus including providing a first silicon substrate having a first contact, wherein providing the first silicon substrate comprises forming a silicide layer between the first silicon substrate and a first metal layer. The method further includes providing a second silicon substrate having a second contact comprising a second metal layer and placing the first contact in contact with the second contact. The method further includes heating the first and second metal layers to form a metallic alloy, whereby the metallic alloy bonds the first contact to the second contact.

Abstract: A method for obtaining a heterogeneous substrate intended for use in the production of a semiconductor comprises the following steps: (a) obtaining a first substrate (2) made from a type II-VI or type III-V material and a second substrate (1), each substrate being substantially planar and each substrate having a pre-determined surface area; (b) grinding a non-through recess (10) into the second substrate (1), the surface area of said recess being greater than the surface area of the first substrate, such that the first substrate can be housed in the recess; (c) depositing a bonding material (15) in the recess (10); (d) depositing the first substrate (2) in the recess (10) of the second substrate and securing the first substrate in the second substrate at a temperature below 300° C.; and (e) leveling the first and second substrates in order to obtain a heterogeneous substrate having a substantially planar face (30).

Abstract: A process for assembling a first wafer and a second wafer each bevelled on their peripheries includes excavating the bevelled peripheral part of at least one first side of the first wafer to create a deposit bordering the region excavated in the material of the first wafer. The first side and a second side of the second wafer are then bonded together.

Abstract: Methods for bonding semiconductor wafers requiring the transfer of electrical and optical signals between the bonded wafers and across the bonding interface by interfusing optical interconnects on one wafer with optical interconnects on a second wafer, interfusing electrical interconnects on one wafer with electrical interconnects on the second wafer, and interfusing a dielectric intermediary bonding layer on one wafer with the dielectric intermediary bonding layer on the second wafer to bond the wafers together with electrical interconnections and optical interconnections between the wafers. The methods are also applicable to the bonding of semiconductor wafers to provide a high density of electrical interconnects between wafers.

Abstract: An electrowetting display device including an electrowetting element with a first support plate, a second support plate, a first fluid and a second fluid immiscible with the first fluid. A voltage may be applied between a first electrode and a second electrode. At least one of the first electrode and the second electrode comprises a semiconducting material.

Abstract: Provided is a method for producing a Group III nitride-based compound semiconductor having an M-plane main surface. The method employs a sapphire substrate having a main surface which is inclined by 30° with respect to R-plane about a line of intersection Lsapph-AM formed by R-plane and A-plane perpendicular thereto. R-plane surfaces of the sapphire substrate are exposed, and a silicon dioxide mask is formed on the main surface of the substrate. AlN buffer layers are formed on the exposed R-plane surfaces. A GaN layer is formed on the AlN buffer layers. At an initial stage of GaN growth, the top surface of the sapphire substrate is entirely covered with the GaN layer through lateral growth.

Abstract: A semiconductor wafer can include a substrate, a poly template layer, and a semiconductor layer. The substrate has a central region and an edge region, the poly template layer is disposed along a peripheral edge of the substrate, and a semiconductor layer over the central region, wherein the semiconductor layer is monocrystalline. In an embodiment, the poly template layer and the monocrystalline layer are laterally spaced apart from each other by an intermediate region. In another embodiment, the semiconductor layer can include aluminum. A process of forming the substrate can include forming a patterned poly template layer within the edge region and forming a semiconductor layer over the primary surface. Another process of forming the substrate can include forming a semiconductor layer over the primary surface and removing a portion of the semiconductor layer so that the semiconductor layer is spaced apart from an edge of the substrate.

Abstract: A method for manufacturing a chip package is provided. The method including: arranging a plurality of dies over a carrier; depositing encapsulation material over the carrier wherein the plurality of dies are covered by the encapsulation material thereby forming a structure including the encapsulation material and the plurality of dies; and removing encapsulation material thereby forming a thinned portion of the structure and a further portion of the structure including encapsulation material thicker than the thinned portion.

Abstract: A method for producing a product wafer having chips thereon, comprising the steps of: processing the first side of the product wafer bonding the product wafer with its first side onto a first rigid carrier wafer with a first intermediate layer consisting of one first adhesion layer applied at least on the edge side, processing a second side of the product wafer, bonding of the product wafer with its second side on a second rigid carrier wafer with a second intermediate layer consisting of one second adhesion layer applied at least on the edge side, characterized in that the first intermediate layer and the second intermediate layer are made different such that the first carrier wafer can be separated selectively before the second carrier wafer.

Abstract: Composite substrates include a silicon layer disposed on a ceramic layer. Different thermal expansion coefficient for the composite substrates can be achieved by changing the thermal expansion coefficient of the ceramic layer. Composite substrates can include two layers of silicon sandwiching a layer of ceramic.

Abstract: An integrated semiconductor device and method for fabricating the same are provided wherein the integrated semiconductor device comprises a substrate a first stress-inducing layer, a second stress-inducing layer and an integrated circuit layer. The first stress-inducing layer covers on the substrate. The second stress-inducing layer partially covers on the first stress-inducing layer. The integrated circuit layer is bonded over the substrate.

Abstract: A high voltage switching circuit includes first and second group III-V transistors, the second group III-V transistor having a greater breakdown voltage than the first group III-V transistor. The circuit further includes a silicon diode in a parallel arrangement with the first group III-V transistor, the parallel arrangement being in cascade with the second group III-V transistor. The circuit is effectively a three-terminal device, where a first terminal is coupled to a gate of the second III-V transistor, a source of the first III-V transistor, and an anode of the silicon diode. A second terminal is coupled to a gate of the first group III-V transistor, and a third terminal is coupled to a drain of the second group III-V transistor. The first group III-V transistor might be an enhancement mode transistor. The second group III-V transistor might be a depletion mode transistor. The first and second group III-V transistors can be GaN HEMTs.

Abstract: A chip includes a semiconductor substrate, a well region in the semiconductor substrate, and a transistor formed at a front side of the semiconductor substrate. A source/drain region of the transistor is disposed in the well region. A well pickup region is disposed in the well region, wherein the well pickup region is at a back side of the semiconductor substrate. A through-via penetrates through the semiconductor substrate, wherein the through-via electrically inter-couples the well pickup region and the source/drain region.

Abstract: A method includes applying a reinforcing wafer to a semiconductor wafer, thereby forming a composite wafer. Further the method includes dividing the composite wafer, thereby generating a plurality of composite chips each including a semiconductor chip and a reinforcing chip.

Abstract: A method for reducing light point defects of a semiconductor-on-insulator structure and a method for reducing the surface roughness of a semiconductor-on-insulator structure are disclosed. The methods can include a combination of thermally annealing the structure followed by a non-contact smoothing process.

Abstract: A semiconductor device includes a first semiconductor substrate including a first integrated circuit, a second semiconductor substrate mounted over the first semiconductor substrate, the second semiconductor substrate including a second integrated circuit, a post made of an inorganic substance and formed over the first semiconductor substrate, an adhesive layer made of an organic substance arranged between the first and the second semiconductor substrates, and a substrate-through-via made of an electrical conductor extending through the second semiconductor substrate and the post, the substrate-through-via extending to the first semiconductor substrate.

Abstract: An embodiment of a die comprising: a semiconductor body including a front side, a back side, and a lateral surface; an electronic device, formed in said semiconductor body and including an active area facing the front side; a vertical conductive connection, extending through the semiconductor body and defining a conductive path between the front side and the back side of the semiconductor body; and a conductive contact, defining a conductive path on the front side of the semiconductor body, between the active area and the vertical conductive connection, wherein the vertical conductive connection is formed on the lateral surface of the die, outside the active area.

Abstract: A method for manufacturing a semiconductor device with a treated member, includes: subjecting an adhesive support having a substrate and an adhesive layer capable of increasing or decreasing in adhesiveness upon irradiation with an actinic ray, radiation or heat to irradiation of the adhesive layer with an actinic ray, radiation or heat, adhering a first surface of a to-be-treated member to the adhesive layer of the adhesive support, applying a mechanical or chemical treatment to a second surface different from the first surface of the to-be-treated member to obtain a treated member, and detaching a first surface of the treated member from the adhesive layer of the adhesive support, wherein the irradiation of the adhesive layer with an actinic ray, radiation or heat is conducted so that adhesiveness decreases toward an outer surface from an inner surface on the substrate side of the adhesive layer.

Abstract: A method for fabricating an integrated circuit includes providing a conductive material overlying a semiconductor substrate and a dielectric material overlying the conductive material, wherein an opening exposes a surface of the conductive material and sidewalls of the dielectric material and selectively depositing a first layer of a first barrier material on the surface of the conductive material with the sidewalls of the dielectric material remaining exposed, the first barrier material being such that, if annealed in an annealing process, the first barrier material would diffuse into the conductive material. The method further includes modifying the first barrier material on the exposed surface to form a second barrier material, the second barrier material being such that, during an annealing process, the second barrier material does not diffuse into the conductive material and depositing a second layer of the first barrier material along the sidewalls of the opening.

Abstract: In a method of forming a CIGS film absorption layer, a first precursor is provided including a first substrate having a major process precursor film formed thereon, the major process precursor film containing two or more of Cu, In, Ga, and Se. A second precursor is provided including a second substrate having an element supplying precursor film formed thereon, the element supply precursor film containing two or more of Cu, In, Ga and Se. The precursors are oriented with the major process precursor film and element supplying precursor film facing one another so as to allow diffusion of elements between the films during annealing. The oriented films are annealed and then the precursors are separated, wherein the CIGS film is formed over the first substrate and either a CIGS film or a precursor film containing two or more of Cu, In, Ga, and Se remains over the second substrate.

Abstract: A semiconductor wafer contains first semiconductor die. TSVs are formed through the semiconductor wafer. Second semiconductor die are mounted to a first surface of the semiconductor wafer. A first tape is applied to on a second surface of the semiconductor wafer. A protective material is formed over the second die and first surface of the wafer. The protective material can be encapsulant or polyvinyl alcohol and water. The wafer is singulated between the second die into individual die-to-wafer packages each containing the second die stacked on the first die. The protective material protects the wafer during singulation. The die-to-wafer package can be mounted to a substrate. A build-up interconnect structure can be formed over the die-to-wafer package. The protective material can be removed. Underfill material can be deposited beneath the first and second die. An encapsulant is deposited over the die-to-wafer package.

Abstract: Embodiments of a method for thinning a wafer are provided. The method includes placing a wafer on a support assembly and securing an etching mask to a backside of the wafer. The etching mask covers a peripheral portion of the wafer. The method further includes performing a wet etching process on the backside of the wafer to form a thinned wafer, and the thinned wafer includes peripheral portions having a first thickness and a central portion having a second thickness smaller than the first thickness. Embodiments of system for forming the thinned wafer are also provided.

Abstract: Provided is a power semiconductor device and a fabrication method thereof are provided. The power semiconductor device includes: a first epitaxial layer; a collector layer formed on one side of the first epitaxial layer; and a second epitaxial layer formed on another side of the first epitaxial layer, the first epitaxial layer having a higher doping concentration than the second epitaxial layer.

Abstract: The invention relates to a process for manufacturing a semiconductor structure comprising a functionalized layer on a support substrate, comprising the following steps: (a) implanting ionic species in a source substrate comprising the said functionalized layer and a sacrificial buffer layer located under the functionalized layer relative to the direction of implantation, to a depth delimiting the thickness of an upper part of the source substrate comprising the functionalized layer and at least part of the buffer layer; (b) bonding the source substrate to the support substrate; (c) fracturing the source substrate and transferring the upper part of the source substrate to the support substrate; (d) removing the buffer layer by selective etching with respect to the functionalized layer.

Abstract: According to the present invention, there is provided a method for manufacturing an SOI wafer having the step of performing a first sacrificial oxidation treatment on the aforementioned bonded SOI wafer in which the delamination has been performed after a first RTA treatment has been performed thereon and then performing a second sacrificial oxidation treatment thereon after a second RTA treatment has been performed thereon, wherein the first and second RTA treatments are performed under a hydrogen gas containing atmosphere and at a temperature of 1100° C. or more, wherein after a thermal oxide film has been formed on the aforementioned SOI layer front surface by performing only thermal oxidation by a batch type heat treating furnace at a temperature of 900° C. or more and 1000° C. or less in the first and second sacrificial oxidation treatments, a treatment for removing the thermal oxide film is performed.

Abstract: A method of transferring a layer including: a) providing a layer joined to an initial substrate with a binding energy E0; b) bonding a front face of the layer on an intermediate substrate according to an intermediate bonding energy Ei; c) detaching the initial substrate from the layer; e) bonding a rear face onto a final substrate according to a final bonding energy Ef; and f) debonding the intermediate substrate from the layer to transfer the layer onto the final substrate; step b) comprising a step of forming siloxane bonds Si—O—Si, step c) being carried out in a first anhydrous atmosphere and step f) being carried out in a second wet atmosphere such that the intermediate bonding energy Ei takes a first value Ei1 in step c) and a second value Ei2 in step f), with Ei1>E0 and Ei2<Ef.

Abstract: A via hole is formed on a base substrate before a device circuit is formed, and thermal oxidation is performed to form a thermal oxidation layer on a surface of the base substrate on which the device circuit is formed and a surface in the via hole. The device circuit having a conductive section is formed on the base substrate after the thermal oxidation, and then, a conductive body is embedded in the via hole.

Abstract: A semiconductor device has a semiconductor die with a plurality of composite bumps formed over a surface of the semiconductor die. The composite bumps have a fusible portion and non-fusible portion, such as a conductive pillar and bump formed over the conductive pillar. The composite bumps can also be tapered. Conductive traces are formed over a substrate with interconnect sites having edges parallel to the conductive trace from a plan view for increasing escape routing density. The interconnect site can have a width less than 1.2 times a width of the conductive trace. The composite bumps are wider than the interconnect sites. The fusible portion of the composite bumps is bonded to the interconnect sites so that the fusible portion covers a top surface and side surface of the interconnect sites. An encapsulant is deposited around the composite bumps between the semiconductor die and substrate.

Abstract: A spall releasing plane is formed embedded within a Group III nitride material layer. The spall releasing plane includes a material that has a different strain, a different structure and a different composition compared with the Group III nitride material portions that provide the Group III nitride material layer and embed the spall releasing plane. The spall releasing plane provides a weakened material plane region within the Group III nitride material layer which during a subsequently performed spalling process can be used to release one of the portions of Group III nitride material from the original Group III nitride material layer. In particular, during the spalling process crack initiation and propagation occurs within the spall releasing plane embedded within the original Group III nitride material layer.

Abstract: According to a semiconductor substrate (40), a space (A) between a plurality of Si thin film (16), which are provide apart from one another on the insulating substrate (30), is (I) larger than a difference between elongation of part of the insulating substrate which part corresponds to the space (A) and elongation of each of Si wafers (10) when a change is made from room temperature to 600° C. and (II) smaller than 5 mm. This causes an increase in a region of each of a plurality of semiconductor thin films which region has a uniform thickness, and therefore prevents transferred semiconductor layers and the insulating substrate from being fractured or chipped.