Thinning Of Semiconductor Substrate Patents (Class 438/459)
  • Patent number: 8981531
    Abstract: A composite wafer 10 includes a supporting substrate 12 and a semiconductor substrate 14 which are bonded to each other by direct bonding. The supporting substrate 12 is a translucent alumina substrate with an alumina purity of 99% or more. The linear transmittance of the supporting substrate 12 at the visible light range is 40% or less. Furthermore, the total light transmittance from the front at a wavelength of 200 to 250 nm of the supporting substrate 12 is 60% or more. The average crystal grain size of the supporting substrate 12 is 10 to 35 ?m. The semiconductor substrate 14 is a single crystal silicon substrate. Such a composite wafer 10 has insulation performance and thermal conduction comparable to those of a SOS wafer, can be manufactured at low cost, and can be easily made to have a large diameter.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: March 17, 2015
    Assignee: NGK Insulators, Ltd.
    Inventors: Yasunori Iwasaki, Akiyoshi Ide, Yuji Hori, Tomoyoshi Tai, Sugio Miyazawa
  • Patent number: 8982270
    Abstract: A deformable focal plane array (DFPA) for imaging systems is disclosed. In one embodiment, the DFPA includes a detection circuitry on one side. For example, the thickness of the DFPA is in a range of about 5 to 40 microns. In one exemplary embodiment, the DFPA when warped to a desired shape provides a substantially wider field of view (FOV) than a flat focal plane array (FPA).
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: March 17, 2015
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Dennis P. Bowler, Raymond J. Silva, Gerard A. Esposito
  • Patent number: 8980671
    Abstract: A manufacturing method of a semiconductor device according to embodiments includes forming a photodiode layer, which is an active region including a photodiode, on a main surface of a first substrate, forming a wiring layer, which includes a wire and a dielectric layer covering the wire, on the photodiode layer, and forming a dielectric film on the wiring layer. The manufacturing method of the semiconductor device according to the embodiments further includes bonding a second substrate to the dielectric film of the first substrate so that a crystal orientation of the photodiode layer matches a crystal orientation of the second substrate.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: March 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Hongo, Kazumasa Tanida, Akihiro Hori, Kenji Takahashi, Hideo Numata
  • Publication number: 20150072505
    Abstract: Provided is an apparatus and a method of holding a device. The apparatus includes a wafer chuck having first and second holes that extend therethrough, and a pressure control structure that can independently and selectively vary a fluid pressure in each of the first and second holes between pressures above and below an ambient pressure. The method includes providing a wafer chuck having first and second holes that extend therethrough, and independently and selectively varying a fluid pressure in each of the first and second holes between pressures above and below an ambient pressure.
    Type: Application
    Filed: September 19, 2014
    Publication date: March 12, 2015
    Inventors: Ping-Yin Liu, Chung-Yi Yu, Che Ying Hsu, Yeur-Luen Tu, Da-Hsiang Chou, Chia-Shiung Tsai
  • Patent number: 8975157
    Abstract: The present invention provides a temporary carrier bonding and detaching process. A first surface of a semiconductor wafer is mounted on a first carrier by a first adhesive, and a first isolation coating is disposed between the first adhesive and the first carrier. Then, a second carrier is mounted on the second surface of the semiconductor wafer. The first carrier is detached. The method of the present invention utilizes the second carrier to support and protect the semiconductor wafer, after which the first carrier is detached. Therefore, the semiconductor wafer will not be damaged or broken, thereby improving the yield rate of the semiconductor process. Furthermore, the simplicity of the detaching method for the first carrier allows for improvement in efficiency of the semiconductor process.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: March 10, 2015
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Wei-Min Hsiao
  • Patent number: 8975188
    Abstract: A plasma etching method is provided for forming a hole using a first processing gas to etch a silicon layer of a substrate to be processed including a silicon oxide film that is formed into a predetermined pattern. The method includes a first depositing step (S11) of depositing a protective film on a surface of the silicon oxide film using a second processing gas containing carbon monoxide gas, a first etching step (S12) of etching the silicon layer using the first processing gas, a second depositing step (S13) of depositing the protective film on a side wall of a hole etched by the first etching step using the second processing gas, and a second etching step (S14) of further etching the silicon layer using the first processing gas. The second depositing step (S13) and the second etching step (S14) are alternately repeated at least two times each.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: March 10, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Yusuke Hirayama, Kazuhito Tohnoe
  • Patent number: 8975183
    Abstract: A method for forming a semiconductor structure. A semiconductor substrate including a plurality of dies mounted thereon is provided. The substrate includes a first portion proximate to the dies and a second portion distal to the dies. In some embodiments, the first portion may include front side metallization. The second portion of the substrate is thinned and a plurality of conductive through substrate vias (TSVs) is formed in the second portion of the substrate after the thinning operation. Prior to thinning, the second portion may not contain metallization. In one embodiment, the substrate may be a silicon interposer. Further back side metallization may be formed to electrically connect the TSVs to other packaging substrates or printed circuit boards.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: March 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jing-Cheng Lin
  • Patent number: 8975158
    Abstract: A method for bonding of a first contact surface of a first substrate to a second contact surface of a second substrate. The method comprises: forming at least one reservoir in at least one reservoir formation layer on the first substrate and/or the second substrate, the reservoir comprised of an amorphous material, at least partial filling of the reservoir/reservoirs with a first educt or a first group of educts, forming or applying a reaction layer which contains a second educt or a second group of educts to the reservoir and/or the reservoir, the first contact surface making contact with the second contact surface for formation of a prebond connection, and forming a permanent bond between the first and second contact surface, at least partially strengthened by the reaction of the first educt or the first group with the second educt or the second group.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: March 10, 2015
    Assignee: EV Group E. Thallner GmbH
    Inventors: Thomas Plach, Kurt Hingerl, Markus Wimplinger, Christoph Flötgen
  • Patent number: 8975160
    Abstract: According to one embodiment, a first adhesive layer is formed on one major surface of a first substrate. The first substrate and a second substrate are adhered using a second adhesive layer that has thermosetting properties and covers the first adhesive layer, wherein a bonding strength between the second substrate is greater than a bonding strength between the second substrate and the first adhesive layer. The other major surface of the first substrate is polished, and the first substrate is thinned. A physical force is then applied to peripheral parts of the second adhesive layer, and a circular notched part is formed along the outer perimeter of the second adhesive layer to separate the first substrate and the second substrate at the interface between the first adhesive layer and the second adhesive layer.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: March 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Eiji Takano
  • Patent number: 8962448
    Abstract: A computer readable medium is provided that is encoded with a program comprising instructions for performing a method for fabricating a 3D integrated circuit structure. Provided are an interface wafer including a first wiring layer and through-silicon vias, and a first active circuitry layer wafer including active circuitry. The first active circuitry layer wafer is bonded to the interface wafer. Then, a first portion of the first active circuitry layer wafer is removed such that a second portion remains attached to the interface wafer. A stack structure including the interface wafer and the second portion of the first active circuitry layer wafer is bonded to a base wafer. Next, the interface wafer is thinned so as to form an interface layer, and metallizations coupled through the through-silicon vias in the interface layer to the first wiring layer are formed on the interface layer.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Robert Hannon, Subramanian S. Iyer, Steven J. Koester, Fei Liu, Sampath Purushothaman, Albert M. Young, Roy R. Yu
  • Patent number: 8956955
    Abstract: A method to prevent contamination of the principal surface side in a process of grinding the back surface side of a semiconductor wafer. At an intersection of a scribe region of a semiconductor wafer whose back surface side is to be ground, a plurality of insulating layers is laminated over the principal surface in the same manner as an insulating layer constituting a wiring layer laminated over a device region. Moreover, in the same layer as an uppermost wiring disposed at the uppermost layer among a plurality of the wiring layers formed for a device region, a metal pattern is formed. Furthermore, a second insulating layer covering the uppermost wiring is also formed over the metal pattern so as to cover the same.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: February 17, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Shoetsu Kogawa, Satoru Nakayama, Seigo Kamata, Shigemitsu Seito
  • Patent number: 8956951
    Abstract: A method for manufacturing an SOI wafer includes performing a flattening heat treatment on an SOI wafer under an atmosphere containing an argon gas, in which conditions of SOI wafer preparation are set so that a thickness of an SOI layer of the SOI wafer to be subjected to the flattening heat treatment is 1.4 or more times thicker than that of a BOX layer, and the thickness of the SOI layer is reduced to less than a thickness 1.4 times the thickness of the BOX layer by performing a sacrificial oxidation treatment on the SOI layer of the SOI wafer after the flattening heat treatment.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: February 17, 2015
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Isao Yokokawa, Masahiro Kato, Masayuki Imai
  • Patent number: 8951886
    Abstract: A method for mechanically separating a laminar structure from a first carrier assembly, comprising or consisting of a first carrier, wherein the laminar structure comprises a wafer and a second, stretchable carrier is disclosed. Also disclosed are the use of a particular separating aid for separating a laminar structure and a device for carrying out the method.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: February 10, 2015
    Assignee: Thin Materials AG
    Inventor: Franz Richter
  • Patent number: 8951882
    Abstract: A method of fabricating an optoelectronic integrated circuit substrate includes defining a photonic device region on a first substrate, the photonic device region having a photonic device formed thereon, forming a trench in the photonic device region on a top surface of the first substrate, the trench having a first depth, filling the trench with a dielectric, bonding a second substrate on the first substrate to cover the trench, and thinning the second substrate to a first thickness.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seong-ho Cho
  • Patent number: 8946055
    Abstract: A laser processing method is provided, which, even when a substrate formed with a laminate part including a plurality of functional devices is thick, can cut the substrate and laminate part with a high precision. This laser processing method irradiates a substrate 4 with laser light L while using a rear face 21 as a laser light entrance surface and locating a light-converging point P within the substrate 4, so as to form modified regions 71, 72, 73 within the substrate 4. Here, the HC modified region 73 is formed at a position between the segmented modified region 72 closest to the rear face 21 and the rear face 21, so as to generate a fracture 24 extending along a line to cut from the HC modified region 73 to the rear face 21.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: February 3, 2015
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Takeshi Sakamoto, Kenshi Fukumitsu
  • Patent number: 8946051
    Abstract: It is an object to provide a method for manufacturing an SOI substrate in which crystal defects of a single crystal semiconductor layer are reduced even when a single crystal semiconductor substrate in which crystal defects exist is used. Such an SOI substrate can be manufactured through the steps of forming a single crystal semiconductor layer which has an extremely small number of defects over a single crystal semiconductor substrate by an epitaxial growth method; forming an oxide film on the single crystal semiconductor substrate by thermal oxidation treatment; introducing ions into the single crystal semiconductor substrate through the oxide film; bonding the single crystal semiconductor substrate into which the ions are introduced and a semiconductor substrate to each other; causing separation by heat treatment; and performing planarization treatment on the single crystal semiconductor layer provided over the semiconductor substrate.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: February 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Eriko Nishida
  • Patent number: 8945988
    Abstract: There is provided a method of fabricating a semiconductor device, method including: a) forming semiconductor elements in plural element regions surrounded by assumed dicing lines on a first principal surface of a semiconductor wafer; b) grinding the second principal surface in such a way that an outer peripheral portion of a second principal surface on the opposite side of the first principal surface of the semiconductor wafer becomes thicker than an inner peripheral portion of the second principal surface; c) forming a metal film, in such a way as to avoid sections corresponding to the dicing lines, on the second principal surface that has been ground in the grinding step; and d) cutting the semiconductor wafer from the second principal surface side along portions where the metal film is not formed on the dicing lines.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: February 3, 2015
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventor: Hiroyuki Numaguchi
  • Publication number: 20150021784
    Abstract: Embodiments of mechanisms of forming a semiconductor device structure are provided. The semiconductor device structure includes a first semiconductor wafer and a second semiconductor wafer. The first semiconductor wafer includes a first transistor formed in a front-side of the first semiconductor wafer, and the second semiconductor wafer includes a second transistor formed in a front-side of the second semiconductor wafer. A backside of the second semiconductor wafer is bonded to the front-side of the first semiconductor wafer. The semiconductor device structure further includes an interconnect structure formed over the front-side of the second semiconductor wafer, and at least one first through substrate via (TSV) directly contacts a conductive feature of the first semiconductor wafer and the interconnect structure.
    Type: Application
    Filed: July 16, 2013
    Publication date: January 22, 2015
    Inventor: Jing-Cheng LIN
  • Publication number: 20150021786
    Abstract: A method is disclosed that includes the steps outlined below. A first oxide layer is formed to divide a first semiconductor substrate into a first part and a second part. A second oxide layer is formed on the first part of the first semiconductor substrate. The first oxide layer is bonded to a third oxide layer of a second semiconductor substrate. The second part of first semiconductor substrate and the first oxide layer are removed to expose the first part of the first semiconductor substrate.
    Type: Application
    Filed: July 18, 2013
    Publication date: January 22, 2015
    Inventor: Jing-Cheng Lin
  • Publication number: 20150021785
    Abstract: Embodiments of forming a semiconductor device structure are provided. The semiconductor device structure includes a first semiconductor wafer and a second semiconductor wafer bonded via a hybrid bonding structure, and the hybrid bonding structure includes a first conductive material embedded in a first polymer material and a second conductive material embedded in a second polymer material. The first conductive material is bonded to the second conductive material and the first polymer material is bonded to the second polymer material. The semiconductor device also includes at least one through silicon via (TSV) extending from a bottom surface of the first semiconductor wafer to a metallization structure of the first semiconductor wafer. The semiconductor device structure also includes an interconnect structure formed over the bottom surface of the first semiconductor wafer, and the interconnect structure is electrically connected to the metallization structure via the TSV.
    Type: Application
    Filed: July 16, 2013
    Publication date: January 22, 2015
    Inventor: Jing-Cheng LIN
  • Publication number: 20150021771
    Abstract: Embodiments of mechanisms of forming a semiconductor device are provided. The semiconductor device includes a first semiconductor wafer comprising a first transistor formed in a front-side of the first semiconductor wafer. The semiconductor device also includes a second semiconductor wafer comprising a second transistor formed in a front-side of the second semiconductor wafer, and a backside of the second semiconductor wafer is bonded to the front-side of the first semiconductor wafer. The semiconductor device further includes an first interconnect structure formed between the first semiconductor wafer and the second semiconductor wafer, and the first interconnect structure comprises a first cap metal layer formed over a first conductive feature. The first interconnect structure is electrically connected to first transistor, and the first cap metal layer is configured to prevent diffusion and cracking of the first conductive feature.
    Type: Application
    Filed: July 16, 2013
    Publication date: January 22, 2015
    Inventor: Jing-Cheng LIN
  • Patent number: 8936999
    Abstract: An SOI substrate including a semiconductor layer whose thickness is even is provided. According to a method for manufacturing the SOI substrate, the semiconductor layer is formed over a base substrate. In the method, a first surface of a semiconductor substrate is polished to be planarized; a second surface of the semiconductor substrate which is opposite to the first surface is irradiated with ions, so that an embrittled region is formed in the semiconductor substrate; the second surface is attached to the base substrate, so that the semiconductor substrate is attached to the base substrate; and separation in the embrittled region is performed. The value of 3? (? denotes a standard deviation of thickness of the semiconductor layer) is less than or equal to 1.5 nm.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: January 20, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Keiichi Sekiguchi, Kazuya Hanaoka, Daigo Ito
  • Patent number: 8937328
    Abstract: A light emitting device includes a light emitting element that emits light having a wavelength of 250 nm to 500 nm and a fluorescent layer that is disposed on the light emitting element. The fluorescent layer includes a phosphor having a composition expressed by the equation, ((M1?x1Eux1)3?ySi13?zAl3+zO2+uN21?w), and an average particle diameter of 12 ?m or more, wherein in the equation, M is an element that is selected from IA group elements, IIA group elements, IIIA group elements, IIIB group elements except Al, rare-earth elements, and IVB group elements, and x1, y, z, u, and w satisfy each of the inequalities simultaneously, that is to say each of the following inequalities is satisfied by the choice of values of the identified paramaters within the noted ranges of 0<x1<1, ?0.1<y<0.3, ?3<z?1, ?3<u?w?1.5, 2<u, w<21.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: January 20, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Iwao Mitsuishi, Yumi Fukuda, Aoi Okada, Naotoshi Matsuda, Shinya Nunoue, Keiko Albessard, Masahiro Kato
  • Patent number: 8932938
    Abstract: A method of producing a composite structure comprises a step of producing a first layer of microcomponents on one face of a first substrate, the first substrate being held flush against a holding surface of a first support during production of the microcomponents, and a step of bonding the face of the first substrate comprising the layer of microcomponents onto a second substrate. During the bonding step, the first substrate is held flush against a second support, the holding surface of which has a flatness that is less than or equal to that of the first support used during production of the first layer of microcomponents.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: January 13, 2015
    Assignee: Soitec
    Inventors: Arnaud Castex, Marcel Broekaart
  • Patent number: 8932910
    Abstract: The invention relates to a method for producing chip stacks with the following method sequence: applying an especially dielectric and/or photostructurable base layer to one carrier side of a carrier which on its carrier side is provided with an adhesively acting adhesion zone and a less adhesively acting support zone, the base layer being applied largely over the entire surface at least to the support zone, building up the chip stacks on the base layer, potting of the chip stacks, detaching the carrier from the base layer. Moreover the invention relates to a carrier for executing this method.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: January 13, 2015
    Assignee: EV Group E. Thallner GmbH
    Inventor: Markus Wimplinger
  • Patent number: 8928120
    Abstract: Among other things, one or more wafer edge protection structures and techniques for forming such wafer edge protection structures are provided. A substrate of a semiconductor wafer comprises an edge, such as a beveled wafer edge portion, that is susceptible to Epi growth which results in undesirable particle contamination of the semiconductor wafer. Accordingly, a wafer edge protection structure is formed over the beveled wafer edge portion. The wafer edge protection structure comprises an Epi growth resistant material, such as an amorphous material, a non-crystalline material, oxide, or other material. In this way, the wafer edge protection structure mitigates Epi growth on the beveled wafer edge portion, where the Epi growth increases a likelihood of particle contamination from cracking or peeling of an Epi film resulting from the Epi growth. The wafer edge protection structure thus mitigates at least some contamination of the wafer.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ming Chyi Liu, Sheng-de Liu, Chi-Ming Chen, Yuan-Tai Tseng, Chung-Yen Chou, Chia-Shiung Tsai
  • Patent number: 8927320
    Abstract: A method of bonding by molecular bonding between at least one lower wafer and an upper wafer comprises positioning the upper wafer on the lower wafer. In accordance with the invention, a contact force is applied to a peripheral side of at least one of the two wafers in order to initiate a bonding wave between the two wafers.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: January 6, 2015
    Assignee: Soitec
    Inventors: Chrystelle Lagahe Blanchard, Marcel Broekaart, Arnaud Castex
  • Patent number: 8921203
    Abstract: A method for forming a semiconductor device includes providing a substrate having a first major surface and a second major surface, removing a first portion of the substrate to form a cavity at the first major surface of the substrate, bonding the first major surface of the substrate to a carrier substrate after forming the cavity, and reducing a thickness of the substrate. The method further includes forming a first accelerometer device at the second major surface such that at least a portion of the first accelerometer device is over the cavity and forming a second accelerometer device at the second major surface such that the second accelerometer device is not disposed over the cavity.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: December 30, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Lisa H. Karlin, Hemant D. Desai, Kemiao Jia
  • Patent number: 8916407
    Abstract: A method of manufacturing a micromachined resonator having a moveable member comprising forming the moveable member from a material having a first concentration of dopants of a first impurity type, depositing a dopant carrier layer on or over at least a portion of the moveable member, wherein the dopant carrier layer includes one or more dopants of the first impurity type, transferring at least a portion of the one or more dopants from the dopant carrier layer to the moveable member, wherein, in response, the concentration of dopants of the first impurity type in the moveable member increases (for example, to greater than 1019 cm?3, and preferably between 1019 cm?3 and 1021 cm?3). The method further includes removing the dopant carrier layer and may include providing an encapsulation structure over the moveable member of the micromachined resonator.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 23, 2014
    Assignee: SiTime Corporation
    Inventors: Charles I Grosjean, Ginel Hill, Paul M. Hagelin, Renata Melamud Berger, Aaron Partridge, Markus Lutz
  • Publication number: 20140367777
    Abstract: A method for forming integrated circuit includes providing a first semiconductor substrate having a front surface and a back surface that is opposite to the front surface. One or more first trenches are in the first semiconductor substrate from the front surface side, the first trenches being characterized by a first depth. One or more second trenches are formed in the first semiconductor substrate from the front surface side, the second trenches being characterized by a second depth which greater than the first depth. A horizontal isolation layer is formed parallel to the front surface and at a third depth from the front surface. The method also includes forming a first recessed region extending in the first semiconductor substrate from the back surface side to the horizontal isolation layer that results in a thinned semiconductor region having a thickness substantially equal to the third depth.
    Type: Application
    Filed: November 19, 2013
    Publication date: December 18, 2014
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Herb He HUANG, Cliff DROWLEY
  • Patent number: 8912055
    Abstract: Disclosed are methods for forming hybrid metal-oxide-semiconductor field effect transistors (MOSFETs) and the hybrid MOSFETS thus obtained. In one embodiment, a method is disclosed that includes providing a first substrate comprising a first region and a second region, providing a second substrate comprising a second semiconductor layer and an insulating layer overlaying the second semiconductor layer, and direct substrate bonding the second substrate to the first substrate, thereby contacting the first region and the second region with the insulating layer. The method further includes selectively removing the second semiconductor layer and the insulating layer in the first region, thereby exposing the first semiconductor layer in the first region, forming a first gate stack of a first MOSFET on the exposed first semiconductor layer in the first region, and forming a second gate stack of a second MOSFET on the second semiconductor layer in the second region.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: December 16, 2014
    Assignee: IMEC
    Inventors: Thomas Y. Hoffman, Matty Caymax, Niamh Waldron, Geert Hellings
  • Patent number: 8906775
    Abstract: A method for fabricating a semiconductor device includes forming a first semiconductor wafer, in which a circuit part and a first bonding layer are stacked, on a first semiconductor substrate, forming a second semiconductor wafer, which includes structures and an insulating layer for gap-filling between the structures, on a second semiconductor substrate, the structures including a pillar and bit lines stacked therein, bonding the first semiconductor wafer with the second semiconductor wafer so that the first bonding layer faces the insulating layer, and separating the second semiconductor substrate from the bonded second semiconductor wafer.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: December 9, 2014
    Assignee: SK Hynix Inc.
    Inventors: Heung-Jae Cho, Eui-Seong Hwang, Tae-Yoon Kim, Kyu-Hyung Yoon
  • Patent number: 8906781
    Abstract: The present invention relates to a method for electrically connecting wafers, which physically bonds two wafers through an oxide-to-oxide bonding method and then electrically connects the two wafers through a butting contact structure. The wafers are physically bonded to each other through a relatively simple method, and then electrically connected to through TSVs or butting contact holes. Therefore, since the fabrication process may be simplified, a process error may be reduced, and the product yield may be improved.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: December 9, 2014
    Assignee: Siliconfile Technologies Inc.
    Inventor: In Gyun Jeon
  • Patent number: 8906778
    Abstract: The present invention related to a method for manufacturing a semiconductor, comprising steps of: providing a growing substrate; forming a semiconductor substrate on the growing substrate; forming a first structure with plural grooves and between the growing substrate and the semiconductor substrate; and changing the temperature of the growing substrate and the semiconductor substrate.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: December 9, 2014
    Assignee: National Chiao Tung University
    Inventors: YewChung Sermon Wu, Bau-Ming Wang, Feng-Ching Hsiao
  • Publication number: 20140353853
    Abstract: The invention relates to a method for manufacturing a multilayer strucute on a first substrate, the method including: using the first substrate made of a first material having a Young's modulus Ev and a thickness ev, and using a second substrate covered by the multilayer structure, the second substrate being made of a second material having a Young's modulus Es that is different from the Young's modulus Ev and a thickness es, the thicknesses es and ev complying, plus or minus 10%, with the relation (I); molecularly bonding the first substrate and the multilayer structure together; and removing the second substrate.
    Type: Application
    Filed: December 27, 2012
    Publication date: December 4, 2014
    Inventors: Umberto Rossini, Thierry Flahaut, Vincent Larrey
  • Patent number: 8900971
    Abstract: The invention provides a method for manufacturing a bonded substrate by bonding a base substrate to a bond substrate through an insulator film, including: a porous layer forming step of partially forming a porous layer or forming a porous layer whose thickness partially varies on a bonding surface of the base substrate; an insulator film forming step of changing the porous layer into the insulator film, and thereby forming the insulator film whose thickness partially varies on the bonding surface of the base substrate; a bonding step of bonding the base substrate to the bond substrate through the insulator film; and a film thickness reducing step of reducing a film thickness of the bonded bond substrate to form a thin-film layer. As a result, there is provided the method for manufacturing a bonded substrate that enables obtaining an insulator film whose thickness partially varies with use of a simple method.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: December 2, 2014
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tsuyoshi Ohtsuki, Wei Feng Qu, Fumio Tahara, Yuuki Ooi, Kyoko Mitani
  • Patent number: 8900966
    Abstract: Provided is an apparatus that includes an integrated circuit located in a first region of a substrate having first and second opposing major surfaces and an alignment mark located in a second region of the substrate and extending through the substrate between the first and second surfaces.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: December 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Cheng Liu, Dun-Nian Yaung, Shou-Gwo Wuu
  • Patent number: 8895362
    Abstract: Methods and apparatus provide for a structure, including: a first glass material layer; and a second material layer bonded to the first glass material layer via bonding material, where the bonding material is formed from one of glass frit material, ceramic frit material, glass ceramic frit material, and metal paste, which has been melted and cured.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: November 25, 2014
    Assignee: Corning Incorporated
    Inventors: James Gregory Couillard, Christopher Paul Daigler, Jiangwei Feng, Yawei Sun, Lili Tian, Ian David Tracy
  • Patent number: 8896639
    Abstract: An object of the present invention is to provide a small-sized active matrix type liquid crystal display device that may achieve large-sized display, high precision, high resolution and multi-gray scales. According to the present invention, gray scale display is performed by combining time ratio gray scale and voltage gray scale in a liquid crystal display device which performs display in OCB mode. In doing so, one frame is divided into subframes corresponding to the number of bit for the time ratio gray scale. Initialize voltage is applied onto the liquid crystal upon display of a subframe.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: November 25, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Publication number: 20140342530
    Abstract: A temporary adhesive material for a wafer includes a first temporary adhesive layer of a silicone-containing polymer layer containing a photo base generator and a second temporary adhesive layer of a silicone-containing polymer layer which is laminated on the first temporary adhesive layer, does not contain the photo base generator, and is different from the polymer layer. Thereby, there can be formed a temporary adhesive layer having high thickness uniformity, even on a wafer having a step. Because of the thickness uniformity, a thin wafer having a uniform thickness of 50 ?m or less can be easily obtained. When a thin wafer is produced and then delaminated from a support, the wafer can be delaminated from the support by exposure at a low exposure dose without stress. Therefore, a brittle thin wafer can be easily handled without causing damage, and a thin wafer can be easily produced.
    Type: Application
    Filed: May 6, 2014
    Publication date: November 20, 2014
    Applicant: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Hiroyuki YASUDA, Michihiro SUGO
  • Patent number: 8890276
    Abstract: A three-dimensional integrated structure is formed from a first integrated circuit with a first cavity filled with a first conductive material and a second integrated circuit with a second cavity filled with a second conductive material, the second cavity facing the first cavity. The filled first cavity forms a first element and the filled second cavity forms a second element, the first and second elements separated from each other by a cavity. The first and second conductive materials have different thermal expansion coefficients. A contact detection circuit is electrically connected to the filled first and second cavities, and is operable to sense electrical contact between the first and second conductive materials in response to a change in temperature.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: November 18, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Laurent-Luc Chapelon
  • Patent number: 8883609
    Abstract: According to an embodiment, a method for manufacturing a semiconductor structure includes providing a first monocrystalline semiconductor portion having a first lattice constant in a reference direction and forming a second monocrystalline semiconductor portion having a second lattice constant in the reference direction, which is different to the first lattice constant, on the first monocrystalline semiconductor portion.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: November 11, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Mathias Plappert, Hans-Joachim Schulze
  • Patent number: 8883613
    Abstract: A disclosed method of manufacturing a semiconductor device includes forming a groove on a first surface of a semiconductor wafer along an outer periphery of the semiconductor wafer, forming a semiconductor device on the first surface, forming an adhesive layer on the first surface to cover the semiconductor device, bonding a support substrate to the first surface by the adhesive layer, grinding after the adhering of the support substrate a second surface of the semiconductor wafer opposite to the first surface, and dicing after the grinding the semiconductor wafer into individual semiconductor chips.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: November 11, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Tamotsu Owada
  • Patent number: 8877637
    Abstract: Through-silicon-via (TSV) based 3D integrated circuit (3D IC) stacks are aligned, bonded and electrically interconnected using a transparent alignment material in the TSVs until the wafers are bonded. Embodiments include providing a first wafer having a first device layer and at least one first TSV filled with a conductive material, providing a second wafer having a second device layer, forming at least one second TSV in the second wafer, filling each second TSV with an alignment material, thinning the second wafer until the transparent material extends all the way through the wafer, aligning the first and second wafers, bonding the first and second wafers, removing the alignment material from the second wafer, and filling each second TSV in the second wafer with a conductive material.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: November 4, 2014
    Assignee: GlobalFoundries Singapore Pte. Ltd
    Inventors: Hong Yu, Huang Liu
  • Patent number: 8877077
    Abstract: A method of printing comprises the steps of: providing a solid state material having an exposed surface; applying an auxiliary layer to the exposed surface to form a composite structure, the auxiliary layer having a stress pattern; subjecting the composite structure to conditions facilitating fracture of the solid state material along a plane at a depth therein; and removing the auxiliary layer and, therewith, a layer of the solid state material terminating at the fracture depth, wherein an exposed surface of the removed layer of solid state material has a surface topology corresponding to the stress pattern.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: November 4, 2014
    Assignee: Siltectra GmbH
    Inventor: Lukas Lichtensteiger
  • Patent number: 8877609
    Abstract: A method for manufacturing a bonded substrate that has an insulator layer in part of the bonded substrate includes: partially forming a porous layer or forming a porous layer whose thickness partially varies on a bonding surface of the base substrate; performing a heat treatment to the base substrate having the porous layer formed thereon to change the porous layer into the insulator layer, and thereby forming the insulator layer whose thickness partially varies on the bonding surface of the base substrate; removing the insulator layer whose thickness varies by an amount corresponding to a thickness of a small-thickness portion by etching; bonding the bonding surface of the base substrate on which an unetched remaining insulator layer is exposed to a bond substrate; and reducing a thickness of the bonded bond substrate and thereby forming a thin film layer.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: November 4, 2014
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tsuyoshi Ohtsuki, Wei Feng Qu, Fumio Tahara, Yuuki Ooi, Kyoko Mitani
  • Patent number: 8877559
    Abstract: Embodiments of the present invention provide a novel process integration for air gap formation at the sidewalls for a Through Silicon Via (TSV) structure. The sidewall air gap formation scheme for the TSV structure of disclosed embodiments reduces parasitic capacitance and depletion regions in between the substrate silicon and TSV conductor, and serves to also reduce mechanical stress in silicon substrate surrounding the TSV conductor.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: November 4, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Shan Gao, Seung Man Choi
  • Patent number: 8871607
    Abstract: A method for producing a hybrid substrate, including a support substrate, a continuous buried insulator layer and, on this continuous layer, a hybrid layer including alternating zones of a first material and at least one second material, wherein these two materials are different by their nature and/or their crystallographic characteristics. The method forms a hybrid layer, including alternating zones of first and second materials, on a homogeneous substrate, assembles this hybrid layer, the continuous insulator layer and the support substrate, and eliminates a part at least of the homogeneous substrate, before or after the assembling.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: October 28, 2014
    Assignees: S.O.I. TEC Silicon on Insulator Technologies, Commissariat a l'Energie Atomique
    Inventors: Thomas Signamarcheix, Franck Fournel, Hubert Moriceau
  • Patent number: 8871588
    Abstract: A method of fabricating a memory cell comprises forming a plurality of doped semiconductor layers on a carrier substrate. The method further comprises forming a plurality of digit lines separated by an insulating material. The digit lines are arrayed over the doped semiconductor layers. The method further comprises etching a plurality of trenches into the doped semiconductor layers. The method further comprises depositing an insulating material into the plurality of trenches to form a plurality of electrically isolated transistor pillars. The method further comprises bonding at least a portion of the structure formed on the carrier substrate to a host substrate. The method further comprises separating the carrier substrate from the host substrate.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: October 28, 2014
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, H. Montgomery Manning
  • Patent number: 8871610
    Abstract: To increase adhesion between a single crystal semiconductor layer and a base substrate and to reduce bonding defects therebetween. To perform radical treatment on a surface of a semiconductor substrate to form a first insulating film on the semiconductor substrate; irradiate the semiconductor substrate with accelerated ions through the first insulating film to form an embrittlement region in the semiconductor substrate; form a second insulating film on the first insulating film; perform heat treatment after bonding a surface of the second insulating film and a surface of the base substrate to perform separation along the embrittlement region so that a semiconductor layer is formed over the base substrate with the first and second insulating films interposed therebetween; etch the semiconductor layer; and irradiate the semiconductor layer on which the etching is performed with a laser beam.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: October 28, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihisa Shimomura, Masaki Koyama, Eiji Higa