Having Specified Scribe Region Structure (e.g., Alignment Mark, Plural Grooves, Etc.) Patents (Class 438/462)
  • Patent number: 10847475
    Abstract: An integrated circuit (IC) structure includes an active area of the IC structure insulator positioned over a substrate. The active area includes an interconnection structure comprised of a first plurality of levels. Each of the interconnect structure levels including an interlayer dielectric (ILD) layer, a barrier layer disposed over the ILD and a conductor metal layer over the barrier layer. The structure also includes a crack stop area which includes a crack stop structure having a second plurality of levels. The interconnect and crack stop structures have an equal number of levels. A third plurality of the crack stop structure levels include a high modulus layer unique to the respective crack stop structure level as compared to the corresponding interconnect structure level.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: November 24, 2020
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Baozhen Li, Xiao Hu Liu, Griselda Bonilla
  • Patent number: 10840194
    Abstract: An integrated circuit (IC) structure includes an active area of the IC structure insulator positioned over a substrate. The active area includes an interconnection structure comprised of a plurality of levels, each of the interconnect structure levels including an interlayer dielectric (ILD) layer, a barrier layer disposed over the ILD and a conductor metal layer over the barrier layer. The IC structure also includes a crack stop area which includes a crack stop structure having an equal plurality of levels as the interconnect structure. Each of the crack stop structure levels includes at least one of the layers of the interconnection structure at a same level. At least one crack stop structure level also includes a high modulus layer unique to the crack stop structure level as compared to the corresponding interconnect structure level.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: November 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Baozhen Li, Xiao Hu Liu, Griselda Bonilla
  • Patent number: 10840195
    Abstract: A method for creating an integrated circuit (IC) structure includes an active area of the IC structure insulator positioned over a substrate. The active area includes an interconnection structure comprised of a plurality of levels, each of the interconnect structure levels including an interlayer dielectric (ILD) layer, a barrier layer disposed over the ILD and a conductor metal layer over the barrier layer. The IC structure also includes a crack stop area which includes a crack stop structure having an equal plurality of levels as the interconnect structure. Each of the crack stop structure levels includes at least one of the layers of the interconnection structure at a same level. At least one crack stop structure level also includes a high modulus layer unique to the crack stop structure level as compared to the corresponding interconnect structure level. In another aspect of the invention, a method for producing the structure is described.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: November 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Baozhen Li, Xiao Hu Liu, Griselda Bonilla
  • Patent number: 10815121
    Abstract: A composite wafer includes a first silicon die with a first top surface; and a polymer substrate with a top surface and a bottom surface. The silicon die is embedded in the polymer substrate such that the top surface of the substrate and the first top surface of the first silicon die are coplanar and the bottom surface of the polymer substrate is planar.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: October 27, 2020
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Si-lam J. Choy, Chien-Hua Chen, Michael W. Cumbie, Devin Alexander Mourey
  • Patent number: 10811458
    Abstract: A method of processing a wafer having devices disposed in respective regions demarcated on a front face thereof by a grid of a plurality of projected dicing lines on the front face, the method includes a mask layer forming step of covering the front face of the wafer except for the regions where grooves are to be formed along the projected dicing lines with a resin material mixed with an ultraviolet ray absorber, and forming a mask layer on the front face of the wafer, a plasma etching step of performing plasma etching on the wafer from the mask layer side using a fluorine-based stable gas as an etching gas, and forming grooves in the wafer along the projected dicing lines, and a mask layer removing step of removing the mask layer after the plasma etching step is performed.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: October 20, 2020
    Assignee: DISCO CORPORATION
    Inventors: Ryugo Oba, Yukinobu Ohura, Hideyuki Sandoh
  • Patent number: 10796963
    Abstract: Implementations of methods of singulating a plurality of die comprised in a substrate may include forming a plurality of die on a first side of a substrate, forming a backside metal layer on a second side of a substrate, applying a polymer layer over the backside metal layer and forming a groove entirely through the polymer layer and partially through a thickness of the backside metal layer. The groove may be located in a die street of the substrate. The method may also include etching through a remaining portion of the backside metal layer located in the die street, removing the polymer layer, singulating the plurality of die in the substrate by removing substrate material in the die street.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: October 6, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. Seddon
  • Patent number: 10796960
    Abstract: A manufacturing process of an element chip, comprising a substrate preparing step for preparing a substrate having first and second sides opposed to each other, and including a plurality of dicing regions and element regions defined by the dicing regions, the first side being covered by a protective film, a first laser-grooving step for forming a plurality of grooves by irradiating a laser beam to the first side along the dicing regions, and a plasma-dicing step for plasma-etching the substrate along the grooves in depth through a plasma exposure, thereby to dice the substrate into a plurality of element chips, wherein the second side of the substrate and an annular frame are held on a holding sheet in the substrate preparing step, and wherein the laser beam is irradiated only in a region inside an outer edge of the substrate in the first laser-grooving step.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: October 6, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hidefumi Saeki, Atsushi Harikai
  • Patent number: 10777508
    Abstract: A semiconductor device includes a substrate including a plurality of chip areas and a scribe line defined thereon, and a mark pattern disposed in the scribe line. The mark pattern includes a plurality of unit cells immediately adjacent to each other, and each unit cell includes a first active region, a second active region isolated from the first active region, a plurality of first gate structures extending along a first direction and arranged along a second direction perpendicular to the first direction, and a plurality of first conductive structures. The first gate structures straddle the first active region and the second active region. The first conductive structures are disposed on the first active region, the second active region, and two opposite sides of the first gate structures.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: September 15, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Kang, Sheng-Yuan Hsueh, Yi-Chung Sheng, Kuo-Yu Liao, Shu-Hung Yu, Hung-Hsu Lin, Hsiang-Hung Peng
  • Patent number: 10770432
    Abstract: A die structure includes a first die having a first surface and a second surface opposite the first surface. The first die includes sidewalls extending between the first and second surfaces. The die structure includes conductive ink printed traces including a first group of the conductive ink printed traces on the first surface of the first semiconductor die. A second group of the conductive ink printed traces are on the second surface of the semiconductor die, and a third group of the conductive ink printed traces are on the sidewalls of the semiconductor die.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: September 8, 2020
    Assignee: STMICROELECTRONICS S.r.l.
    Inventor: Federico Giovanni Ziglioli
  • Patent number: 10763112
    Abstract: According to one embodiment, a method for manufacturing a device includes a first process, a second process, a third process, and a fourth process. The first process includes providing a structure body at a first surface of a substrate. The substrate is light-transmissive and has a second surface. A light transmissivity of the structure body is lower than a light transmissivity of the substrate. The second process includes providing a negative-type photoresist at the second surface. The third process includes irradiating the substrate with light to expose a portion of the photoresist. The light is irradiated in a first direction from the first surface toward the second surface. The light passes through the substrate. The fourth process includes developing the photoresist to remain the portion of the photoresist in a state of being adhered to the second surface and to remove other portion of the photoresist.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: September 1, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Etsuo Hamada
  • Patent number: 10757817
    Abstract: A circuit board with embedded components includes an inner layer board, electronic component disposed in the inner layer circuit board, and third to sixth conductive circuit layers. The third and fourth conductive circuit layers are on opposite surfaces of the inner circuit board through first and second adhesive layers. The third conductive circuit layer and the fourth conductive circuit layer are electrically connected to the first conductive circuit layer and the second conductive circuit layer.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: August 25, 2020
    Assignees: HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., Avary Holding (Shenzhen) Co., Limited.
    Inventor: Chih-Chieh Fu
  • Patent number: 10734299
    Abstract: A method includes forming a polymer layer covering a metal via in a wafer, grooving the wafer to form a trench, wherein the trench extends from a top surface of the polymer layer into the wafer, and performing a die-saw on the wafer to separate the wafer into a plurality of device dies. A kerf passes through the trench. One of the device dies is placed over a carrier. An encapsulating material is dispensed over and around the device die. The method further includes pressing and curing the encapsulating material. After the encapsulating material is cured, a sidewall of the polymer layer is tilted. A planarization is performed on the encapsulating material until the polymer layer and the metal via are exposed. A redistribution line is formed over and electrically coupled to the metal via.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Yen Chiu, Hsin-Chieh Huang, Ching Fu Chang
  • Patent number: 10693279
    Abstract: In an example, the present invention provides a gallium and nitrogen containing structure. The structure has a plurality of gallium and nitrogen containing semiconductor substrates, each of the gallium and nitrogen containing semiconductor substrates having one or more epitaxially grown layers. The structure has a first handle substrate coupled to each of the substrates. The orientation of a reference crystal direction for each of the substrates are parallel to within 10 degrees or less. The structure has a first bonding medium provided between the first handle substrate and each of the substrates.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: June 23, 2020
    Assignee: Soraa Laser Diode, Inc.
    Inventors: Melvin McLaurin, Alexander Sztein, Po Shan Hsu, James W. Raring
  • Patent number: 10692227
    Abstract: A system for determining a sample map for alignment measurements includes a metrology tool and a controller. The controller defines a full sampling map including a plurality of measurement locations. The controller directs the metrology tool to measure alignment at each measurement location of the full sampling map for a plurality of samples to generate a reference alignment dataset, generates candidate sampling maps, each being a subset of the full sampling map. The controller may further estimate alignment as a function of location based on the two or more candidate sampling maps at each measurement location of the full sampling map, and determine a working sampling map by comparing the estimated alignment to the reference alignment dataset and selecting the candidate sampling map having a smallest number of alignment estimates exceeding a selected tolerance.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: June 23, 2020
    Assignee: KLA-Tencor Corporation
    Inventors: Brent A. Riggs, Onur N. Demirer, William Pierson
  • Patent number: 10622404
    Abstract: There is provided semiconductor devices and methods of forming the same, including: a first substrate; and a second substrate adjacent to the first substrate, where a side wall of the second substrate includes one or more diced portions that can include a blade diced portion and a stealth diced portion; and also imaging devices and methods of forming the same, including: a first substrate; a transparent layer; an adhesive layer between the first substrate and the transparent layer; a second substrate, where the first substrate is disposed between the adhesive layer and the second substrate; and a groove extending from the adhesive layer to the second substrate, where the groove is filled with the adhesive layer.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: April 14, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Masanari Yamaguchi, Taizo Takachi, Shunsuke Furuse, Takashi Oinoue, Yuki Ikebe
  • Patent number: 10607846
    Abstract: Method of manufacturing an element chip which can suppress residual debris in plasma dicing. A back surface of a semiconductor wafer is held on a dicing tape. Then, a surface of the wafer is coated with a mask that includes a water-insoluble lower mask and a water-soluble upper mask. Subsequently, an opening is formed in the mask by irradiating the mask with laser light to expose a dividing region. Then, the semiconductor wafer is caused to come into contact with water to remove the upper mask covering each of the element regions while leaving the lower layer. After that, the wafer is exposed to plasma to perform etching on the dividing region exposed from the opening until the etching reaches the back surface, thereby dicing the semiconductor wafer into a plurality of element chips. Thereafter, the lower layer mask left on the front surface of the semiconductor chips is removed.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: March 31, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hidehiko Karasaki, Noriyuki Matsubara, Atsushi Harikai, Hidefumi Saeki
  • Patent number: 10607941
    Abstract: A method includes encapsulating a device die in an encapsulating material, forming a first dielectric layer over the device die and the encapsulating material, forming first redistribution lines extending into the first dielectric layer to electrically couple to the device die, forming an alignment mark over the first dielectric layer, wherein the alignment mark includes a plurality of elongated strips, forming a second dielectric layer over the first redistribution lines and the alignment mark, and forming second redistribution lines extending into the second dielectric layer to electrically couple to the first redistribution lines. The second redistribution lines are formed using the alignment mark for alignment.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: March 31, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jhih-Yu Wang, Yung-Chi Chu, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
  • Patent number: 10593658
    Abstract: A method of forming a light emitting device is provided. A carrier with a plurality of buffer pads and a plurality of light emitting diode chips is provided, wherein the buffer pads are disposed between the carrier and the light emitting diode chips and are with Young's modulus of 2˜10 GPa. The carrier is positioned over a receiving substrate. A thermal bonding process is performed to electrically connect the light emitting diode chips to the receiving substrate, and wherein the buffer pads and the receiving substrate are located at opposite sides of each light emitting diode chip.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: March 17, 2020
    Assignee: PlayNitride Inc.
    Inventors: Tzu-Yang Lin, Yu-Hung Lai, Yu-Yun Lo
  • Patent number: 10586898
    Abstract: A method of manufacturing a light emitting device in which a plurality of light emitting devices are formed collectively and then separated into individual light emitting devices, wherein each light emitting device includes a light emitting element, the method including, a base member providing step of providing a base member including: a wiring electrode to be connected to the light emitting elements, and an alignment mark, wherein the wiring electrode and the alignment mark are disposed on an upper surface of the base member; a mounting step of mounting each of the light emitting elements at a predetermined position; an alignment mark covering step of covering the alignment mark with a light-transmissive resin; a reflective resin forming step of forming a reflective resin surrounding the light emitting element so as to expose at least a part of a surface of the light-transmissive resin, the reflective resin reflecting light from the light emitting element; and a cutting step of recognizing the alignment mar
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: March 10, 2020
    Assignee: NICHIA CORPORATION
    Inventor: Yoshiki Sato
  • Patent number: 10553490
    Abstract: A processing method for a wafer including a crack detection step for irradiating illumination of a wavelength transparent to wafer, picking up an image of the wafer, and detecting whether a crack is generated within the wafer, a crack direction verification step for verifying, when a crack is detected, to which one of the first and second directions a direction in which the crack extends is nearer, a first cutting step for positioning the cutting blade to a scheduled division line of a direction decided to be a direction farther from the direction in which the crack extends from between the first and second directions and cutting the scheduled division line, and next a second cutting step for positioning the cutting blade to a scheduled division line of a direction decided to be nearer to the direction in which the crack extends and cutting the scheduled division line.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: February 4, 2020
    Assignee: DISCO CORPORATION
    Inventors: Hiroshi Morikazu, Noboru Takeda
  • Patent number: 10534276
    Abstract: Techniques are provided for fabricating and utilizing optically opaque non-planar alignment structures in non-die areas (e.g., kerf areas) of a wafer to align photomasks to die areas on the wafer. For example, an insulating layer is formed over non-die and die areas of the wafer. A non-planar alignment feature is formed in the insulating layer in the non-die area. An optically opaque layer stack is formed in the die and non-die areas of the wafer, which conformally covers the non-planar alignment feature to form an optically opaque non-planar alignment structure in the non-die area. A lithographic patterning process is performed to pattern the optically opaque layer stack in the die area, wherein the optically opaque non-planar alignment structure in the non-die area is utilized to align a photomask to the die area. The optically opaque non-planar alignment structure can include any type of non-planar structure having a stepped sidewall surface.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: January 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Hao Tang, Dominik Metzler, Cornelius Brown Peethala
  • Patent number: 10483149
    Abstract: A wafer processing method includes: a protective member placing step of placing a protective member on the face side of a wafer; a shield tunnel forming step of applying a laser beam, which has a wavelength that is transmittable through single-crystal silicon, to areas of the wafer that correspond to projected dicing lines from a reverse side of the wafer, thereby successively forming a plurality of shield tunnels in the wafer, each including a fine pore extending from the reverse side to the face side of the wafer and an amorphous region surrounding the fine pore; and a dividing step of dividing the wafer into individual device chips by etching the shield tunnels according to plasma etching. The pulsed laser beam used in the shield tunnel forming step has a wavelength of 1950 nm or higher.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: November 19, 2019
    Assignee: DISCO CORPORATION
    Inventor: Hiroshi Morikazu
  • Patent number: 10468303
    Abstract: A device chip manufacturing method includes a passivation film removing step of removing a passivation film along each division line, a wafer dividing step of performing plasma etching using a fluorine-based gas to the front side of a wafer in the condition where the passivation film is used as a mask, thereby dividing the wafer along the division lines, and a die attach film removing step of performing plasma etching using an oxygen-based gas to the front side of the wafer in the condition where the passivation film is used as a mask, thereby removing a part or the whole of a die attach film along each division line.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: November 5, 2019
    Assignee: DISCO CORPORATION
    Inventor: Tomotaka Tabuchi
  • Patent number: 10431958
    Abstract: In an example, the present invention provides a gallium and nitrogen containing multilayered structure. The structure has a plurality of gallium and nitrogen containing semiconductor substrates, each of the gallium and nitrogen containing semiconductor substrates (“substrates”) having a plurality of epitaxially grown layers overlaying a top-side of each of the substrates. The structure has an orientation of a reference crystal direction for each of the substrates. The structure has a first handle substrate coupled to each of the substrates such that each of the substrates is aligned to a spatial region configured in a selected direction of the first handle substrate. The reference crystal direction for each of the substrates is parallel to the spatial region in the selected direction within 10 degrees or less.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: October 1, 2019
    Assignee: Soraa Laser Diode, Inc.
    Inventors: Melvin McLaurin, Alexander Sztein, Po Shan Hsu, James W. Raring
  • Patent number: 10424512
    Abstract: A sector-shaped wafer piece is processed according to the shape of the piece obtained by dividing a wafer into quarters. Information is collected on the shapes of four patterns of the quarter wafer pieces different in the position of a circular arc of an outer periphery and on processing feed quantities corresponding to the shapes of the four patterns. A pattern is selected by calculating a region of a square having vertical and horizontal sides equal to the two sides of the quarter wafer piece, imaging each of the sides to search for the presence/absence of a target pattern, and selecting that one of the four patterns to which the held quarter wafer piece corresponds. The held quarter wafer piece is processed along division lines with a processing feed quantity corresponding to the selected pattern.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: September 24, 2019
    Assignee: DISCO CORPORATION
    Inventor: Makoto Tanaka
  • Patent number: 10421157
    Abstract: A method of forming an electrode structure for a capacitive touch sensor in a first transparent conductive layer (19) which is located on a first side of a glass substrate (5) on the second side of which is a color filter layer (11,12,13) over-coated with a transparent non-conductive layer (15) and a second transparent conductive layer (7), by a direct write laser scribing process using a pulsed solid state laser (22), the laser wavelength in the range 257 nm to 266 nm and a pulse length in the range 50 fs to 50 ns so grooves (21) are formed in the first transparent conductive layer (19) to electrically isolate areas of the first transparent conductive layer (19) on opposite sides of each groove (21). This selection of wavelength and pulse length enables the grooves (21) to be formed with substantially no damage to the underlying color filter layer (11, 12, 13), the transparent non-conductive layer (15) or the second transparent conductive layer (7) on the second side of the glass substrate (5).
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: September 24, 2019
    Assignee: M-SOLV LTD.
    Inventors: Yuk Kwan Chan, Camilo Prieto Rio
  • Patent number: 10332777
    Abstract: A wafer processing method includes a liquid supplying step of supplying a liquid to the front side of a wafer, a close contact making step of pressing a protective film against the front side of the wafer with the liquid interposed therebetween, thereby bringing the protective film into close contact with the front side of the wafer, a protective member fixing step of covering the protective film, with a protective member formed from a liquid resin curable by external stimulus, thereby fixing the protective member through the protective film to the front side of the wafer, a grinding step of grinding the back side of the wafer to reduce the thickness of the wafer, and a peeling step of peeling the protective film and the protective member from the wafer thinned by the grinding step.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: June 25, 2019
    Assignee: Disco Corporation
    Inventor: Kazuma Sekiya
  • Patent number: 10204826
    Abstract: A method for fabricating semiconductor device includes the steps of: forming an inter-metal dielectric (IMD) layer on a substrate; forming a trench in the IMD layer; performing a treatment process to transform part of the IMD layer into a damaged layer adjacent to the trench; forming a protective layer on a sidewall of the damaged layer; forming a metal layer in the trench; and removing the damaged layer to form an air gap adjacent to the protective layer.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: February 12, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Min-Shiang Hsu, Yuan-Fu Ko, Chih-Sheng Chang
  • Patent number: 10177063
    Abstract: A method for manufacturing an element chip includes a protection film stacking step of staking a protection film to the element region, and the dividing region, the part of the exposed second damaged region and a protection film etching step of removing a part of the protection film which is stacked on the dividing region and the protection film which is stacked on the element region by exposing the substrate to second plasma and remaining the protection film for covering the part of the second damaged region. Furthermore, the method for manufacturing an element chip includes a plasma dicing step of dividing the substrate to a plurality of element chips by exposing the substrate to third plasma in a state where the second main surface is supported by a supporting member.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: January 8, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Bunzi Mizuno, Mitsuru Hiroshima, Shogo Okita, Noriyuki Matsubara, Atsushi Harikai
  • Patent number: 10081076
    Abstract: A wafer is produced from an ingot having an end surface. The method includes an end surface measuring step of measuring undulation present on the end surface, and a separation plane forming step of setting the focal point of a laser beam inside the ingot at a predetermined depth from the end surface, which depth corresponds to the thickness of the wafer to be produced, and next applying the laser beam to the end surface to thereby form a separation plane containing a modified layer and cracks extending from the modified layer. The height of an objective lens for forming the focal point of the laser beam is controlled so that the focal point is set in the same plane to form the separation plane, according to the numerical aperture NA of the lens, the refractive index N of the ingot, and the undulation present on the end surface.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: September 25, 2018
    Assignee: DISCO CORPORATION
    Inventors: Kazuya Hirata, Yoko Nishino, Tomoki Yoshino
  • Patent number: 10079169
    Abstract: A method of forming a plurality of semiconductor devices includes applying a tape material to a back side of a semiconductor device having a silicon layer on the back side and a circuitry layer on the front side, lasing with an infrared laser the silicon layer through the tape material, lasing with a second laser the circuitry layer, and expanding the tape material for form a plurality of semiconductor devices. The second layer may be an ultraviolet laser. The lasers may be irradiated in a pattern on the bottom side and the top side. The second layer may form a groove in the circuitry layer that does not penetrate the silicon layer. The infrared laser may cleave a portion of the silicon lattice of the silicon layer. A coating may be applied to the circuitry layer prior to being irradiated with the second laser.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: September 18, 2018
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Andy E. Hooper, Nicholas Wade Clyde
  • Patent number: 10007387
    Abstract: Disclosed is a display device, a pressure detecting method and a pressure detecting device. Since a FPC electrode disposed on a side of a FPC board facing a display panel, an upper electrode for grounding disposed on a side of the display panel facing the flexible printed board and an elastically deformable dielectric material disposed between the FPC electrode and the upper electrode and contacting therewith respectively are additionally disposed between the FPC board and the upper electrode, or a FPC electrode disposed on a side of a FPC board facing a support frame and an elastically deformable dielectric material disposed between the FPC electrode and the support frame and contacting therewith respectively are additionally disposed between the FPC board and the support frame, it is possible to detect a magnitude of a pressure exerted on the display panel, thereby overcoming the defect that the existing display device can not realize pressure detection, thus improving user experience.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: June 26, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiangxiang Zou, Jiayang Zhou, Xuefei Wang
  • Patent number: 9999138
    Abstract: A method of making connection elements for a microelectronic device is provided, including foil ling a conducting layer on a support on which there is at least one conducting pad located on a front face of the support opposite a back face thereof, the conducting layer including a first conducting portion in contact with at least one conducting pad, the first conducting portion extending on the front face and being connected to at least one second conducting portion extending in contact with at least one given wall of the support being located between the front and back faces and forming a non-zero angle with the front face; thinning the support at the back face to release one conducting end of the second conducting portion as a free conducting end projecting from the back face; and after the thinning, bending the free conducting end projecting from the back face.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: June 12, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Stephan Borel
  • Patent number: 9947606
    Abstract: A semiconductor device is disclosed including material for absorbing EMI and/or RFI. The device includes a substrate, one or more semiconductor die, and molding compound around the one or more semiconductor die. The material for absorbing EMI and/or RFI may be provided within or on a solder mask layer on the substrate, or within a dielectric core of the substrate. The device may further include EMI/RFI-absorbing material around the molding compound and in contact with the EMI/RFI-absorbing material on the substrate to completely enclose the one or more semiconductor die in EMI/RFI-absorbing material.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: April 17, 2018
    Assignee: SANDISK INFORMATION TECHNOLOGY (SHANGHAI) CO., LTD.
    Inventors: Dacheng Huang, Ye Bai, Kaiyou Qian, Chin-Tien Chiu
  • Patent number: 9935055
    Abstract: A method of manufacturing a semiconductor device includes forming a separation trench into a first main surface of a semiconductor substrate and removing substrate material from a second main surface of the semiconductor substrate, so as to thin the substrate to a thickness of less than 100 ?m, the second main surface being opposite to the first main surface, so as to uncover a bottom side of the trench. Additional methods of manufacturing semiconductor devices are provided.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: April 3, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Andreas Meiser, Markus Zundel, Martin Poelzl, Paul Ganitzer, Georg Ehrentraut
  • Patent number: 9887140
    Abstract: There is provided a wafer processing method for dividing a wafer having a plurality of devices formed in regions partitioned by a plurality of crossing division lines on a front surface of a substrate having a birefringent crystal structure, into individual device chips. The wafer processing method includes a detection step of detecting the division line formed on the front surface of the wafer by an imaging unit from the back side of the wafer. In the detection step, a polarizer disposed on an optical axis connecting an imaging element and an image forming lens provided in the imaging unit intercepts extraordinary light appearing due to birefringence in the substrate and guides ordinary light to the imaging element.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: February 6, 2018
    Assignee: DISCO CORPORATION
    Inventors: Noboru Takeda, Takumi Shotokuji
  • Patent number: 9865425
    Abstract: Disclosed herein is a sample holder which holds a sample such that a surface is exposed and can be mounted in each of multiple measurement devices that perform measurement based on different measurement principles so that properties of the sample can be measured by each of the measurement devices. The sample holder includes: a main body that surrounds the sample; alignment marks that are arranged at each of two or more different positions in a surface of the main body and can be detected by the measurement devices; and a sample-retaining portion that is disposed within the main body and retains the sample such that a height difference between a mark surface of the alignment mark and the surface of the sample is set to a predetermined value.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: January 9, 2018
    Assignee: HITACHI HIGH-TECH SCIENCE CORPORATION
    Inventor: Kazunori Ando
  • Patent number: 9859478
    Abstract: A light emitting device includes a first substrate, a second substrate and a plurality of micro epitaxial structures. The second substrate is disposed opposite to the first substrate. The micro epitaxial structures are periodically disposed on the substrate and located between the first substrate and the second substrate. A coefficient of thermal expansion of the first substrate is CTE1, a coefficient of thermal expansion of the second substrate is CTE2, a side length of each of the micro epitaxial structures is W, W is in the range between 1 micrometer and 100 micrometers, and a pitch of any two adjacent micro epitaxial structures is P, wherein W/P=0.1 to 0.95, and CTE2/CTE1=0.8 to 1.2.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: January 2, 2018
    Assignee: PlayNitride Inc.
    Inventors: Tzu-Yang Lin, Yu-Hung Lai, Yu-Yun Lo
  • Patent number: 9824926
    Abstract: A wafer is transferred to a holding surface of a chuck table by using a transfer unit having a suction pad. The front side of the wafer is held under suction through a protective tape on the holding surface, and the suction pad is removed from the back side of the wafer. A modified layer is formed on the back side of the wafer along division lines. The wafer is transferred by mounting the wafer held by the suction pad on the holding surface and sandwiching the wafer between the suction pad and the holding surface of the chuck table. A suction force is applied to the holding surface of the chuck table to thereby hold the front side of the wafer through the protective tape on the holding surface of the chuck table under suction, and the suction pad is then removed from the back side of the wafer.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: November 21, 2017
    Assignee: DISCO CORPORATION
    Inventor: Masaru Nakamura
  • Patent number: 9786562
    Abstract: A method is described of radiatively cutting a wafer, the method comprising the steps of low power cutting of two trenches followed by high power cutting of a fissure. A single pulsed radiation beam is split into a first pulsed radiation beam for cutting at least one of the trenches and a second pulsed radiation beam for cutting the fissure. When cutting a fissure on the wafer in a cutting direction along a cutting street, the first and second radiation beams are directed simultaneously with the first radiation beam leading and the second radiation beam trailing. For cutting a fissure in the opposite cutting direction, a third pulsed radiation beam for trenching is split from said single pulsed radiation beam.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: October 10, 2017
    Assignee: ASM TECHNOLOGY SINGAPORE PTE LTD
    Inventor: Karel Maykel Richard Van Der Stam
  • Patent number: 9780063
    Abstract: A semiconductor wafer has a plurality of semiconductor die with contact pads for electrical interconnect. An insulating layer is formed over the semiconductor wafer. A bump structure is formed over the contact pads. The bump structure has a buffer layer formed over the insulating layer and contact pad. A portion of the buffer layer is removed to expose the contact pad and an outer portion of the insulating layer. A UBM layer is formed over the buffer layer and contact pad. The UBM layer follows a contour of the buffer layer and contact pad. A ring-shaped conductive pillar is formed over the UBM layer using a patterned photoresist layer filled with electrically conductive material. A conductive barrier layer is formed over the ring-shaped conductive pillar. A bump is formed over the conductive barrier layer. The buffer layer reduces thermal and mechanical stress on the bump and contact pad.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: October 3, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: JoonYoung Choi, YoungJoon Kim, SungWon Cho
  • Patent number: 9700961
    Abstract: An ablation method of applying a laser beam to a die attach film to perform ablation. The ablation method includes a protective film forming step of applying a liquid resin containing a fine powder of oxide having absorptivity to the wavelength of the laser beam to at least a subject area of the die attach film to be ablated, thereby forming a protective film containing the fine powder on at least the subject area of the die attach film, and a laser processing step of applying the laser beam to the subject area coated with the protective film, thereby performing ablation through the protective film to the subject area of the die attach film after performing the protective film forming step.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: July 11, 2017
    Assignee: DISCO CORPORATION
    Inventor: Nobuyasu Kitahara
  • Patent number: 9673351
    Abstract: A method of manufacturing semiconductor chips includes: forming grooves on a front face side of a substrate; and forming grooves on a back face side of the substrate as defined herein, and in manufacturing conditions in which a variation range of a top section of the cutting member having a tapered tip end shape with no top face in the groove width direction changes from a range included in the groove on the front face side to a range away from the groove on the front face side as wear of the cutting member advances, the use of the cutting member is stopped before the variation range changes from the range included in the groove on the front face side to the range away from the groove on the front face side.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: June 6, 2017
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Takeshi Minamiru, Michiaki Murata, Kenji Yamazaki, Tsutomu Otsuka
  • Patent number: 9649775
    Abstract: A workpiece dividing method for dividing a platelike workpiece into a plurality of individual chips. The workpiece dividing method includes a workpiece preparing step of preparing the platelike workpiece, at least one side of the workpiece being formed as a mat surface, a holding step of holding the workpiece on a holding surface of a chuck table in the condition where the mat surface of the workpiece is exposed, a cut groove forming step of cutting the mat surface of the workpiece held on the holding surface of the chuck table by using a cutting blade to thereby form a cut groove with a remaining portion, and a laser cutting step of applying a laser beam to the workpiece along the cut groove to thereby cut the remaining portion.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: May 16, 2017
    Assignee: Disco Corporation
    Inventor: Satoshi Kumazawa
  • Patent number: 9601531
    Abstract: A wafer level packaging structure for image sensors and a wafer level packaging method for image sensors are provided. The wafer level packaging structure includes: a wafer to be packaged including multiple chip regions and scribe line regions between the chip regions; pads and image sensing regions located on a first surface of the wafer and located in the chip regions; first dike structures covering surfaces of the pads and the scribe line regions; a packaging cover arranged facing the first surface of the wafer; and second dike structures located on a surface of the packaging cover. The second dike structures are arranged corresponding to the scribe line regions. The packaging cover and the wafer are jointed fixedly via the second dike structures and the first dike structures.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: March 21, 2017
    Assignee: China Wafer Level CSP Co., Ltd.
    Inventors: Zhiqi Wang, Qiong Yu, Wei Wang
  • Patent number: 9583375
    Abstract: Methods and systems for forming water soluble masks by dry film lamination are described. Also described are methods of wafer dicing, including formation of a water soluble mask by dry film lamination. In one embodiment, a method involves moisturizing an inner area of a water soluble dry film. The method involves stretching the water soluble dry film over a surface of the semiconductor wafer, and attaching the moistened inner area of the stretched film to the surface of the semiconductor wafer. A method of wafer dicing may further involve patterning the water soluble dry film, exposing regions of the semiconductor wafer between the ICs, and etching the semiconductor wafer through gaps in the patterned water soluble dry film.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: February 28, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, James S. Papanu, Brad Eaton, Ajay Kumar
  • Patent number: 9555502
    Abstract: Methods and systems for forming a scribe line in a thin film stack on an inner surface of a thin film photovoltaic superstrate are provided via the use of a cleaning laser beam and a scribing laser beam. The cleaning laser beam is focused directly onto the exposed surface of the superstrate such that the cleaning laser beam removes debris from the exposed surface of the superstrate, and the scribing laser beam is focused through the exposed surface of the superstrate and onto the thin film stack such that the scribing laser beam passes through the superstrate to form a scribe within the thin film stack on the inner surface of the superstrate. The method and system can further utilize a conveyor to transport the superstrate in a machine direction to move the superstrate past the cleaning laser source and the scribing laser source.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: January 31, 2017
    Assignee: First Solar, Inc.
    Inventors: Scott Daniel Feldman-Peabody, William J. Schaffer
  • Patent number: 9548274
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a non-rectangular die area, a dicing ring and a reticle area surrounding the non-rectangular die. The dicing ring is within the reticle area and surrounds the non-rectangular die area. The number of edges of the reticle area is not equal to 4.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: January 17, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chen-Hua Yu, Ming-Fa Chen, Sung-Feng Yeh
  • Patent number: 9481051
    Abstract: A method for producing a hexagonal single crystal wafer from a hexagonal single crystal ingot includes a separation start point forming step of setting the focal point of a laser beam inside the ingot at a predetermined depth from the upper surface of the ingot, which depth corresponds to the thickness of the wafer to be produced, and next applying the laser beam to the upper surface of the ingot while relatively moving the focal point and the ingot to thereby form a modified layer parallel to the upper surface and cracks extending from the modified layer along a c-plane in the ingot, thus forming a separation start point. The ingot is immersed in water after forming the separation start point in the ingot, and ultrasonic vibration is applied to the ingot to thereby separate a plate-shaped member corresponding to the wafer from the ingot.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: November 1, 2016
    Assignee: DISCO CORPORATION
    Inventors: Kazuya Hirata, Yoko Nishino, Kunimitsu Takahashi
  • Patent number: 9484368
    Abstract: A solid-state imaging device includes a semiconductor substrate configured to include a solid-state imaging element that is provided with a photoelectric conversion region, and a scribe line region that is provided along a periphery of the solid-state imaging element, a wiring layer that is formed to be layered on the semiconductor substrate, a support substrate that is formed to be layered on the wiring layer, and a groove that is provided between a blade region in the scribe line region and the solid-state imaging element, in the semiconductor substrate and penetrates through the semiconductor substrate.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: November 1, 2016
    Assignee: Sony Corporation
    Inventor: Hiroyuki Kawashima