Having Specified Scribe Region Structure (e.g., Alignment Mark, Plural Grooves, Etc.) Patents (Class 438/462)
  • Patent number: 11145548
    Abstract: A manufacturing process of an element chip comprises a preparing step for preparing a substrate having first and second sides opposed to each other, the substrate containing a semiconductor layer, a wiring layer and a resin layer formed on the first side, and the substrate including a plurality of dicing regions and element regions defined by the dicing regions. Also, the manufacturing process comprises a laser grooving step for irradiating a laser beam onto the dicing regions to form grooves so as to expose the semiconductor layer along the dicing regions. Further, the manufacturing process comprises a dicing step for plasma-etching the semiconductor layer along the dicing regions through the second side to divide the substrate into a plurality of the element chips. The laser grooving step includes a melting step for melting a surface of the semiconductor layer exposed along the dicing regions.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: October 12, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hidefumi Saeki, Atsushi Harikai, Shogo Okita
  • Patent number: 11145515
    Abstract: In a manufacturing method of a semiconductor device including a substrate having a front surface and a rear surface, and a film attached to the rear surface, the film is attached on the rear surface, a rear surface side groove is provided by half-cutting the substrate from the rear surface together with the film, a protective member is attached to the film after the rear surface side groove is provided, and a front surface side groove connected to the rear surface side groove is provided by dicing the substrate from the front surface after the protective member is attached.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: October 12, 2021
    Assignee: DENSO CORPORATION
    Inventors: Shuntaro Yamada, Akinori Kanda, Tetsuo Yoshioka, Takashige Nagao, Kouichi Miyashita
  • Patent number: 11139626
    Abstract: A thermocompression apparatus includes a stage and a heater chip. The stage includes an installation surface on which a component having a scheduled portion of thermocompression is placed. The heater chip is disposed to be freely movable to and from the scheduled portion of thermocompression of the component opposite to the installation surface of the stage and is configured to heat and press the scheduled portion of thermocompression. The installation surface includes a maximum convex and a pair of slope surfaces. The maximum convex is configured to contact with a bottom surface of the component. The pair of slope surfaces has heights decreasing respectively from the maximum convex toward both sides of the installation surface in a width direction of the component.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: October 5, 2021
    Assignee: TDK CORPORATION
    Inventor: Koki Sato
  • Patent number: 11139252
    Abstract: A semiconductor package includes a semiconductor die, a plurality of conductive bumps, a shielding layer, an encapsulant and a redistribution layer. The semiconductor die has an active surface, a backside surface and a lateral surface. The conductive bumps are disposed on the active surface of the semiconductor die. The shielding layer is disposed on the lateral surface of the semiconductor die. The encapsulant covers the shielding layer, and has a first surface and a second surface opposite to the first surface. The redistribution layer is disposed on the first surface of the encapsulant and electrically connected to the semiconductor die through the conductive bumps. The shielding layer is electrically connected to the redistribution layer.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: October 5, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Nan Fang, Chun-Jun Zhuang, Yung I. Yeh
  • Patent number: 11127700
    Abstract: An integrated circuit device includes a substrate and an integrated circuit area on the substrate. The integrated circuit area includes a dielectric stack. A cap layer is disposed on the dielectric stack. A seal ring is disposed in the dielectric stack and around a periphery of the integrated circuit area. A trench is formed around the seal ring to expose a sidewall of the dielectric stack. A MIM capacitor including a CTM layer and a CBM layer is disposed on the dielectric stack. A moisture blocking layer continuously covers the integrated circuit area and the MIM capacitor. The cap layer is interposed between the CTM layer and the CBM layer of the MIM capacitor and functions as a capacitor dielectric layer of the MIM capacitor. The moisture blocking layer extends to the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: September 21, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Kuo-Yuh Yang, Chia-Huei Lin, Chu-Chun Chang
  • Patent number: 11103959
    Abstract: Provided is a laser processing method including a first step of forming a first modified region along a cutting line by converging laser light on an object having a surface and a back surface with the back surface as an incident surface and moving a first converging point along the cutting line set to pass between an effective region and an ineffective region adjacent to each other while maintaining a distance between a surface and the first converging point at a first distance, and a second step of forming a second modified region along the cutting line by converging the laser light on the object with the back surface as the incident surface and moving a second converging point along the cutting line while maintaining a distance between the surface and the second converging point at a second distance larger than the first distance.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: August 31, 2021
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Takafumi Ogiwara, Yuta Kondoh
  • Patent number: 11069625
    Abstract: A method for forming a package structure and method for forming the same are provided. The method includes forming a package layer over a substrate, and forming a first dielectric layer over the package layer. The method further includes forming a first alignment mark and a second alignment mark over the first dielectric layer. The method includes forming a second dielectric layer over the first dielectric layer and removing a portion of the second dielectric layer to form a first trench to expose the first alignment mark, and to form a first opening to expose the second alignment.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu
  • Patent number: 11038082
    Abstract: A method comprises forming a mask on a first surface of a substrate. The mask is patterned to form openings on the first surface of the substrate. Notches are formed in the first surface of the substrate in the openings. The mask is removed from the first surface of the substrate A plurality of LEDs are provided on the first surface of the substrate and between notches. A second surface of the substrate is thinned to expose the notches and separate the LEDs. The second surface of the substrate is opposite of the first surface of the substrate.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: June 15, 2021
    Assignee: Lumileds LLC
    Inventors: Filip Ilievski, Norbertus Antonius Maria Sweegers, Kwong-Hin Henry Choy, Marc Andre De Samber
  • Patent number: 11024542
    Abstract: A manufacturing method of a device chip includes a die bonding resin providing step of supplying a die bonding resin in a liquid state to a back surface side of a wafer with device chips formed on a front surface thereof and solidifying the die bonding resin, a water-soluble resin providing step of covering the die bonding resin with a water-soluble resin, a laser processing step of applying a laser beam from the back surface side of the wafer to remove the die bonding resin and the water-soluble resin, an etching step of etching an exposed portion on the back surface side of the wafer to divide the wafer, and a water-soluble resin removing step of supplying water on the back surface side of the wafer to remove the water-soluble resin.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: June 1, 2021
    Assignee: DISCO CORPORATION
    Inventor: Heidi Lan
  • Patent number: 10998202
    Abstract: A semiconductor package includes a die and an encapsulant. The die has an active surface and an opposite backside surface. The encapsulant wraps around the die and has a recess reaching the backside surface. A span of the recess differs from a span of the backside surface and a span of the encapsulant. A manufacturing method includes at least the following steps. A blanket die attach film is spin-coated. A light exposure process is performed to the blanket die attach film. Blanket die attach film is developed to form a patterned die adhesive. A die is disposed over the patterned die adhesive with a backside surface closer to the patterned die adhesive. The patterned die adhesive is cured to affix the die. The die and the cured die adhesive are encapsulated in an encapsulant. The cured die adhesive is removed.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: May 4, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Han Wang, Hung-Jui Kuo, Yu-Hsiang Hu
  • Patent number: 10964596
    Abstract: Implementations of methods of singulating a plurality of die included in a substrate may include forming a plurality of die on a first side of a substrate, forming a backside metal layer on a second side of a substrate, applying a photoresist layer over the backside metal layer, patterning the photoresist layer along a die street of the substrate, and etching through the backside metal layer located in the die street of the substrate. The substrate may be exposed through the etch. The method may also include singulating the plurality of die included in the substrate through removing a substrate material in the die street.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: March 30, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. Seddon
  • Patent number: 10957657
    Abstract: A method for constructing an advanced crack stop structure is described. An interconnection structure is formed comprised of a plurality of levels. Each level has an interconnect structure section and a crack stop section. In a first level of the interconnection structure, a high modulus layer is formed in the crack stop recess but not the interconnect recess and a barrier layer and a conductive metal layer is formed in both the interconnection recess and the crack stop recess of the first level. In a second level of the interconnection structure and the crack stop structure, a second high modulus layer is formed in the crack stop recess but not the interconnect recess and a barrier layer and a conductive metal layer is formed in both the interconnection recess and the crack stop recess of the second level. The barrier layers and high modulus layers are deposited in different steps.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: March 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Baozhen Li, Xiao Hu Liu, Griselda Bonilla
  • Patent number: 10896819
    Abstract: Implementations of die singulation systems and related methods may include forming a plurality of die on a first side of a substrate, forming a backside metal layer on a second side of a substrate, applying a photoresist layer over the backside metal layer, patterning the photoresist layer along a die street of the substrate, and forming a groove at the pattern of the photoresist layer only partially through a thickness of the backside metal layer. The groove may be located in the die street of the substrate. The method may also include etching through a remaining portion of the backside metal layer located in the die street, removing the photoresist layer, and singulating the plurality of die included in the substrate by removing substrate material in the die street.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: January 19, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Takashi Noma, Michael J. Seddon
  • Patent number: 10896849
    Abstract: A substrate has first and second surfaces, and includes a plurality of element regions and dividing region defining the element regions. A method for manufacturing an element chip includes: a step of spray coating, to the first surface of the substrate, a mixture containing a water-soluble resin and an organic solvent having a higher vapor pressure than water, and drying the coated mixture at a temperature of 50° C. or less, to form a protective film; a laser grooving step of removing portions of the protective film covering the dividing regions; a step of dicing the substrate into element chips by plasma etching the substrate; and a step of removing the portions of the protective film covering the element regions. The mixture has a solid component ratio of 200 g/L or more, and droplets of the sprayed mixture have an average particle size of 12 ?m or less.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: January 19, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hidehiko Karasaki, Shogo Okita, Noriyuki Matsubara, Hidefumi Saeki
  • Patent number: 10884284
    Abstract: The present disclosure provides a color film substrate and a preparation method therefor, a display device and a glue applying system. The method for preparing a color film substrate includes forming a transparent insulating layer, wherein thickness of the transparent insulating layer is determined according to thickness of a metal film layer on an array substrate that is paired with the color film substrate.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: January 5, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Yanchun Lu
  • Patent number: 10879190
    Abstract: Methods are provided for patterning an active region formed in a semiconductor wafer. In one aspect, the methods generally include providing active regions and kerf regions between active regions in the semiconductor wafer, wherein the active regions and the kerf regions include a patterned dielectric layer, a metal conductor, and a liner layer between the dielectric layer and the metal conductor. An upper surface of the active regions and the kerf regions is planarized to form a planar surface. The metal conductor from the kerf regions is selectively removed to form a trench. An optically opaque layer is conformally deposited onto the semiconductor wafer to form a recessed alignment mark in the kerf regions. The active regions are then patterned using the recessed alignment mark in the kerf region.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: December 29, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chih-Chao Yang, Hao Tang, Dominik Metzler, Cornelius Brown Peethala
  • Patent number: 10872819
    Abstract: A processing method for processing a plate-shaped workpiece having a division line on the front side and a multilayer member containing metal formed on the back side is provided. The processing method includes a holding step of holding the front side of the workpiece on a holding table in the condition where the multilayer member formed on the back side of the workpiece is exposed, a cutting step of cutting the workpiece along the division line by using a cutting blade after performing the holding step, thereby forming a cut groove dividing the multilayer member, and a laser processing step of applying a laser beam to the workpiece along the cut groove after performing the cutting step. The cutting step includes the step of supplying a cutting fluid containing an organic acid and an oxidizing agent to the workpiece.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: December 22, 2020
    Assignee: DISCO CORPORATION
    Inventor: Kenji Takenouchi
  • Patent number: 10850436
    Abstract: Disclosed herein is a method of manufacturing an interior material, which can implement various and distinct light emission effects by disposing a light-blocking layer configured to block light emitted from a light source at a location adjacent to an inner transparent film and then allowing the component of the transparent film to fill lighting grooves formed by laser-etching. Since a tape configured to support an island is employed, stable manufacturing is possible throughout an overall process.
    Type: Grant
    Filed: November 18, 2018
    Date of Patent: December 1, 2020
    Assignee: INTOPS CO., LTD.
    Inventors: Keun ha Kim, Won jae Choi, Hong il Lee
  • Patent number: 10847475
    Abstract: An integrated circuit (IC) structure includes an active area of the IC structure insulator positioned over a substrate. The active area includes an interconnection structure comprised of a first plurality of levels. Each of the interconnect structure levels including an interlayer dielectric (ILD) layer, a barrier layer disposed over the ILD and a conductor metal layer over the barrier layer. The structure also includes a crack stop area which includes a crack stop structure having a second plurality of levels. The interconnect and crack stop structures have an equal number of levels. A third plurality of the crack stop structure levels include a high modulus layer unique to the respective crack stop structure level as compared to the corresponding interconnect structure level.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: November 24, 2020
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Baozhen Li, Xiao Hu Liu, Griselda Bonilla
  • Patent number: 10840195
    Abstract: A method for creating an integrated circuit (IC) structure includes an active area of the IC structure insulator positioned over a substrate. The active area includes an interconnection structure comprised of a plurality of levels, each of the interconnect structure levels including an interlayer dielectric (ILD) layer, a barrier layer disposed over the ILD and a conductor metal layer over the barrier layer. The IC structure also includes a crack stop area which includes a crack stop structure having an equal plurality of levels as the interconnect structure. Each of the crack stop structure levels includes at least one of the layers of the interconnection structure at a same level. At least one crack stop structure level also includes a high modulus layer unique to the crack stop structure level as compared to the corresponding interconnect structure level. In another aspect of the invention, a method for producing the structure is described.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: November 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Baozhen Li, Xiao Hu Liu, Griselda Bonilla
  • Patent number: 10840194
    Abstract: An integrated circuit (IC) structure includes an active area of the IC structure insulator positioned over a substrate. The active area includes an interconnection structure comprised of a plurality of levels, each of the interconnect structure levels including an interlayer dielectric (ILD) layer, a barrier layer disposed over the ILD and a conductor metal layer over the barrier layer. The IC structure also includes a crack stop area which includes a crack stop structure having an equal plurality of levels as the interconnect structure. Each of the crack stop structure levels includes at least one of the layers of the interconnection structure at a same level. At least one crack stop structure level also includes a high modulus layer unique to the crack stop structure level as compared to the corresponding interconnect structure level.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: November 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Baozhen Li, Xiao Hu Liu, Griselda Bonilla
  • Patent number: 10815121
    Abstract: A composite wafer includes a first silicon die with a first top surface; and a polymer substrate with a top surface and a bottom surface. The silicon die is embedded in the polymer substrate such that the top surface of the substrate and the first top surface of the first silicon die are coplanar and the bottom surface of the polymer substrate is planar.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: October 27, 2020
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Si-lam J. Choy, Chien-Hua Chen, Michael W. Cumbie, Devin Alexander Mourey
  • Patent number: 10811458
    Abstract: A method of processing a wafer having devices disposed in respective regions demarcated on a front face thereof by a grid of a plurality of projected dicing lines on the front face, the method includes a mask layer forming step of covering the front face of the wafer except for the regions where grooves are to be formed along the projected dicing lines with a resin material mixed with an ultraviolet ray absorber, and forming a mask layer on the front face of the wafer, a plasma etching step of performing plasma etching on the wafer from the mask layer side using a fluorine-based stable gas as an etching gas, and forming grooves in the wafer along the projected dicing lines, and a mask layer removing step of removing the mask layer after the plasma etching step is performed.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: October 20, 2020
    Assignee: DISCO CORPORATION
    Inventors: Ryugo Oba, Yukinobu Ohura, Hideyuki Sandoh
  • Patent number: 10796963
    Abstract: Implementations of methods of singulating a plurality of die comprised in a substrate may include forming a plurality of die on a first side of a substrate, forming a backside metal layer on a second side of a substrate, applying a polymer layer over the backside metal layer and forming a groove entirely through the polymer layer and partially through a thickness of the backside metal layer. The groove may be located in a die street of the substrate. The method may also include etching through a remaining portion of the backside metal layer located in the die street, removing the polymer layer, singulating the plurality of die in the substrate by removing substrate material in the die street.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: October 6, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. Seddon
  • Patent number: 10796960
    Abstract: A manufacturing process of an element chip, comprising a substrate preparing step for preparing a substrate having first and second sides opposed to each other, and including a plurality of dicing regions and element regions defined by the dicing regions, the first side being covered by a protective film, a first laser-grooving step for forming a plurality of grooves by irradiating a laser beam to the first side along the dicing regions, and a plasma-dicing step for plasma-etching the substrate along the grooves in depth through a plasma exposure, thereby to dice the substrate into a plurality of element chips, wherein the second side of the substrate and an annular frame are held on a holding sheet in the substrate preparing step, and wherein the laser beam is irradiated only in a region inside an outer edge of the substrate in the first laser-grooving step.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: October 6, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hidefumi Saeki, Atsushi Harikai
  • Patent number: 10777508
    Abstract: A semiconductor device includes a substrate including a plurality of chip areas and a scribe line defined thereon, and a mark pattern disposed in the scribe line. The mark pattern includes a plurality of unit cells immediately adjacent to each other, and each unit cell includes a first active region, a second active region isolated from the first active region, a plurality of first gate structures extending along a first direction and arranged along a second direction perpendicular to the first direction, and a plurality of first conductive structures. The first gate structures straddle the first active region and the second active region. The first conductive structures are disposed on the first active region, the second active region, and two opposite sides of the first gate structures.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: September 15, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Kang, Sheng-Yuan Hsueh, Yi-Chung Sheng, Kuo-Yu Liao, Shu-Hung Yu, Hung-Hsu Lin, Hsiang-Hung Peng
  • Patent number: 10770432
    Abstract: A die structure includes a first die having a first surface and a second surface opposite the first surface. The first die includes sidewalls extending between the first and second surfaces. The die structure includes conductive ink printed traces including a first group of the conductive ink printed traces on the first surface of the first semiconductor die. A second group of the conductive ink printed traces are on the second surface of the semiconductor die, and a third group of the conductive ink printed traces are on the sidewalls of the semiconductor die.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: September 8, 2020
    Assignee: STMICROELECTRONICS S.r.l.
    Inventor: Federico Giovanni Ziglioli
  • Patent number: 10763112
    Abstract: According to one embodiment, a method for manufacturing a device includes a first process, a second process, a third process, and a fourth process. The first process includes providing a structure body at a first surface of a substrate. The substrate is light-transmissive and has a second surface. A light transmissivity of the structure body is lower than a light transmissivity of the substrate. The second process includes providing a negative-type photoresist at the second surface. The third process includes irradiating the substrate with light to expose a portion of the photoresist. The light is irradiated in a first direction from the first surface toward the second surface. The light passes through the substrate. The fourth process includes developing the photoresist to remain the portion of the photoresist in a state of being adhered to the second surface and to remove other portion of the photoresist.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: September 1, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Etsuo Hamada
  • Patent number: 10757817
    Abstract: A circuit board with embedded components includes an inner layer board, electronic component disposed in the inner layer circuit board, and third to sixth conductive circuit layers. The third and fourth conductive circuit layers are on opposite surfaces of the inner circuit board through first and second adhesive layers. The third conductive circuit layer and the fourth conductive circuit layer are electrically connected to the first conductive circuit layer and the second conductive circuit layer.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: August 25, 2020
    Assignees: HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., Avary Holding (Shenzhen) Co., Limited.
    Inventor: Chih-Chieh Fu
  • Patent number: 10734299
    Abstract: A method includes forming a polymer layer covering a metal via in a wafer, grooving the wafer to form a trench, wherein the trench extends from a top surface of the polymer layer into the wafer, and performing a die-saw on the wafer to separate the wafer into a plurality of device dies. A kerf passes through the trench. One of the device dies is placed over a carrier. An encapsulating material is dispensed over and around the device die. The method further includes pressing and curing the encapsulating material. After the encapsulating material is cured, a sidewall of the polymer layer is tilted. A planarization is performed on the encapsulating material until the polymer layer and the metal via are exposed. A redistribution line is formed over and electrically coupled to the metal via.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Yen Chiu, Hsin-Chieh Huang, Ching Fu Chang
  • Patent number: 10693279
    Abstract: In an example, the present invention provides a gallium and nitrogen containing structure. The structure has a plurality of gallium and nitrogen containing semiconductor substrates, each of the gallium and nitrogen containing semiconductor substrates having one or more epitaxially grown layers. The structure has a first handle substrate coupled to each of the substrates. The orientation of a reference crystal direction for each of the substrates are parallel to within 10 degrees or less. The structure has a first bonding medium provided between the first handle substrate and each of the substrates.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: June 23, 2020
    Assignee: Soraa Laser Diode, Inc.
    Inventors: Melvin McLaurin, Alexander Sztein, Po Shan Hsu, James W. Raring
  • Patent number: 10692227
    Abstract: A system for determining a sample map for alignment measurements includes a metrology tool and a controller. The controller defines a full sampling map including a plurality of measurement locations. The controller directs the metrology tool to measure alignment at each measurement location of the full sampling map for a plurality of samples to generate a reference alignment dataset, generates candidate sampling maps, each being a subset of the full sampling map. The controller may further estimate alignment as a function of location based on the two or more candidate sampling maps at each measurement location of the full sampling map, and determine a working sampling map by comparing the estimated alignment to the reference alignment dataset and selecting the candidate sampling map having a smallest number of alignment estimates exceeding a selected tolerance.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: June 23, 2020
    Assignee: KLA-Tencor Corporation
    Inventors: Brent A. Riggs, Onur N. Demirer, William Pierson
  • Patent number: 10622404
    Abstract: There is provided semiconductor devices and methods of forming the same, including: a first substrate; and a second substrate adjacent to the first substrate, where a side wall of the second substrate includes one or more diced portions that can include a blade diced portion and a stealth diced portion; and also imaging devices and methods of forming the same, including: a first substrate; a transparent layer; an adhesive layer between the first substrate and the transparent layer; a second substrate, where the first substrate is disposed between the adhesive layer and the second substrate; and a groove extending from the adhesive layer to the second substrate, where the groove is filled with the adhesive layer.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: April 14, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Masanari Yamaguchi, Taizo Takachi, Shunsuke Furuse, Takashi Oinoue, Yuki Ikebe
  • Patent number: 10607846
    Abstract: Method of manufacturing an element chip which can suppress residual debris in plasma dicing. A back surface of a semiconductor wafer is held on a dicing tape. Then, a surface of the wafer is coated with a mask that includes a water-insoluble lower mask and a water-soluble upper mask. Subsequently, an opening is formed in the mask by irradiating the mask with laser light to expose a dividing region. Then, the semiconductor wafer is caused to come into contact with water to remove the upper mask covering each of the element regions while leaving the lower layer. After that, the wafer is exposed to plasma to perform etching on the dividing region exposed from the opening until the etching reaches the back surface, thereby dicing the semiconductor wafer into a plurality of element chips. Thereafter, the lower layer mask left on the front surface of the semiconductor chips is removed.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: March 31, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hidehiko Karasaki, Noriyuki Matsubara, Atsushi Harikai, Hidefumi Saeki
  • Patent number: 10607941
    Abstract: A method includes encapsulating a device die in an encapsulating material, forming a first dielectric layer over the device die and the encapsulating material, forming first redistribution lines extending into the first dielectric layer to electrically couple to the device die, forming an alignment mark over the first dielectric layer, wherein the alignment mark includes a plurality of elongated strips, forming a second dielectric layer over the first redistribution lines and the alignment mark, and forming second redistribution lines extending into the second dielectric layer to electrically couple to the first redistribution lines. The second redistribution lines are formed using the alignment mark for alignment.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: March 31, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jhih-Yu Wang, Yung-Chi Chu, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
  • Patent number: 10593658
    Abstract: A method of forming a light emitting device is provided. A carrier with a plurality of buffer pads and a plurality of light emitting diode chips is provided, wherein the buffer pads are disposed between the carrier and the light emitting diode chips and are with Young's modulus of 2˜10 GPa. The carrier is positioned over a receiving substrate. A thermal bonding process is performed to electrically connect the light emitting diode chips to the receiving substrate, and wherein the buffer pads and the receiving substrate are located at opposite sides of each light emitting diode chip.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: March 17, 2020
    Assignee: PlayNitride Inc.
    Inventors: Tzu-Yang Lin, Yu-Hung Lai, Yu-Yun Lo
  • Patent number: 10586898
    Abstract: A method of manufacturing a light emitting device in which a plurality of light emitting devices are formed collectively and then separated into individual light emitting devices, wherein each light emitting device includes a light emitting element, the method including, a base member providing step of providing a base member including: a wiring electrode to be connected to the light emitting elements, and an alignment mark, wherein the wiring electrode and the alignment mark are disposed on an upper surface of the base member; a mounting step of mounting each of the light emitting elements at a predetermined position; an alignment mark covering step of covering the alignment mark with a light-transmissive resin; a reflective resin forming step of forming a reflective resin surrounding the light emitting element so as to expose at least a part of a surface of the light-transmissive resin, the reflective resin reflecting light from the light emitting element; and a cutting step of recognizing the alignment mar
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: March 10, 2020
    Assignee: NICHIA CORPORATION
    Inventor: Yoshiki Sato
  • Patent number: 10553490
    Abstract: A processing method for a wafer including a crack detection step for irradiating illumination of a wavelength transparent to wafer, picking up an image of the wafer, and detecting whether a crack is generated within the wafer, a crack direction verification step for verifying, when a crack is detected, to which one of the first and second directions a direction in which the crack extends is nearer, a first cutting step for positioning the cutting blade to a scheduled division line of a direction decided to be a direction farther from the direction in which the crack extends from between the first and second directions and cutting the scheduled division line, and next a second cutting step for positioning the cutting blade to a scheduled division line of a direction decided to be nearer to the direction in which the crack extends and cutting the scheduled division line.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: February 4, 2020
    Assignee: DISCO CORPORATION
    Inventors: Hiroshi Morikazu, Noboru Takeda
  • Patent number: 10534276
    Abstract: Techniques are provided for fabricating and utilizing optically opaque non-planar alignment structures in non-die areas (e.g., kerf areas) of a wafer to align photomasks to die areas on the wafer. For example, an insulating layer is formed over non-die and die areas of the wafer. A non-planar alignment feature is formed in the insulating layer in the non-die area. An optically opaque layer stack is formed in the die and non-die areas of the wafer, which conformally covers the non-planar alignment feature to form an optically opaque non-planar alignment structure in the non-die area. A lithographic patterning process is performed to pattern the optically opaque layer stack in the die area, wherein the optically opaque non-planar alignment structure in the non-die area is utilized to align a photomask to the die area. The optically opaque non-planar alignment structure can include any type of non-planar structure having a stepped sidewall surface.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: January 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Hao Tang, Dominik Metzler, Cornelius Brown Peethala
  • Patent number: 10483149
    Abstract: A wafer processing method includes: a protective member placing step of placing a protective member on the face side of a wafer; a shield tunnel forming step of applying a laser beam, which has a wavelength that is transmittable through single-crystal silicon, to areas of the wafer that correspond to projected dicing lines from a reverse side of the wafer, thereby successively forming a plurality of shield tunnels in the wafer, each including a fine pore extending from the reverse side to the face side of the wafer and an amorphous region surrounding the fine pore; and a dividing step of dividing the wafer into individual device chips by etching the shield tunnels according to plasma etching. The pulsed laser beam used in the shield tunnel forming step has a wavelength of 1950 nm or higher.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: November 19, 2019
    Assignee: DISCO CORPORATION
    Inventor: Hiroshi Morikazu
  • Patent number: 10468303
    Abstract: A device chip manufacturing method includes a passivation film removing step of removing a passivation film along each division line, a wafer dividing step of performing plasma etching using a fluorine-based gas to the front side of a wafer in the condition where the passivation film is used as a mask, thereby dividing the wafer along the division lines, and a die attach film removing step of performing plasma etching using an oxygen-based gas to the front side of the wafer in the condition where the passivation film is used as a mask, thereby removing a part or the whole of a die attach film along each division line.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: November 5, 2019
    Assignee: DISCO CORPORATION
    Inventor: Tomotaka Tabuchi
  • Patent number: 10431958
    Abstract: In an example, the present invention provides a gallium and nitrogen containing multilayered structure. The structure has a plurality of gallium and nitrogen containing semiconductor substrates, each of the gallium and nitrogen containing semiconductor substrates (“substrates”) having a plurality of epitaxially grown layers overlaying a top-side of each of the substrates. The structure has an orientation of a reference crystal direction for each of the substrates. The structure has a first handle substrate coupled to each of the substrates such that each of the substrates is aligned to a spatial region configured in a selected direction of the first handle substrate. The reference crystal direction for each of the substrates is parallel to the spatial region in the selected direction within 10 degrees or less.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: October 1, 2019
    Assignee: Soraa Laser Diode, Inc.
    Inventors: Melvin McLaurin, Alexander Sztein, Po Shan Hsu, James W. Raring
  • Patent number: 10424512
    Abstract: A sector-shaped wafer piece is processed according to the shape of the piece obtained by dividing a wafer into quarters. Information is collected on the shapes of four patterns of the quarter wafer pieces different in the position of a circular arc of an outer periphery and on processing feed quantities corresponding to the shapes of the four patterns. A pattern is selected by calculating a region of a square having vertical and horizontal sides equal to the two sides of the quarter wafer piece, imaging each of the sides to search for the presence/absence of a target pattern, and selecting that one of the four patterns to which the held quarter wafer piece corresponds. The held quarter wafer piece is processed along division lines with a processing feed quantity corresponding to the selected pattern.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: September 24, 2019
    Assignee: DISCO CORPORATION
    Inventor: Makoto Tanaka
  • Patent number: 10421157
    Abstract: A method of forming an electrode structure for a capacitive touch sensor in a first transparent conductive layer (19) which is located on a first side of a glass substrate (5) on the second side of which is a color filter layer (11,12,13) over-coated with a transparent non-conductive layer (15) and a second transparent conductive layer (7), by a direct write laser scribing process using a pulsed solid state laser (22), the laser wavelength in the range 257 nm to 266 nm and a pulse length in the range 50 fs to 50 ns so grooves (21) are formed in the first transparent conductive layer (19) to electrically isolate areas of the first transparent conductive layer (19) on opposite sides of each groove (21). This selection of wavelength and pulse length enables the grooves (21) to be formed with substantially no damage to the underlying color filter layer (11, 12, 13), the transparent non-conductive layer (15) or the second transparent conductive layer (7) on the second side of the glass substrate (5).
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: September 24, 2019
    Assignee: M-SOLV LTD.
    Inventors: Yuk Kwan Chan, Camilo Prieto Rio
  • Patent number: 10332777
    Abstract: A wafer processing method includes a liquid supplying step of supplying a liquid to the front side of a wafer, a close contact making step of pressing a protective film against the front side of the wafer with the liquid interposed therebetween, thereby bringing the protective film into close contact with the front side of the wafer, a protective member fixing step of covering the protective film, with a protective member formed from a liquid resin curable by external stimulus, thereby fixing the protective member through the protective film to the front side of the wafer, a grinding step of grinding the back side of the wafer to reduce the thickness of the wafer, and a peeling step of peeling the protective film and the protective member from the wafer thinned by the grinding step.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: June 25, 2019
    Assignee: Disco Corporation
    Inventor: Kazuma Sekiya
  • Patent number: 10204826
    Abstract: A method for fabricating semiconductor device includes the steps of: forming an inter-metal dielectric (IMD) layer on a substrate; forming a trench in the IMD layer; performing a treatment process to transform part of the IMD layer into a damaged layer adjacent to the trench; forming a protective layer on a sidewall of the damaged layer; forming a metal layer in the trench; and removing the damaged layer to form an air gap adjacent to the protective layer.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: February 12, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Min-Shiang Hsu, Yuan-Fu Ko, Chih-Sheng Chang
  • Patent number: 10177063
    Abstract: A method for manufacturing an element chip includes a protection film stacking step of staking a protection film to the element region, and the dividing region, the part of the exposed second damaged region and a protection film etching step of removing a part of the protection film which is stacked on the dividing region and the protection film which is stacked on the element region by exposing the substrate to second plasma and remaining the protection film for covering the part of the second damaged region. Furthermore, the method for manufacturing an element chip includes a plasma dicing step of dividing the substrate to a plurality of element chips by exposing the substrate to third plasma in a state where the second main surface is supported by a supporting member.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: January 8, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Bunzi Mizuno, Mitsuru Hiroshima, Shogo Okita, Noriyuki Matsubara, Atsushi Harikai
  • Patent number: 10081076
    Abstract: A wafer is produced from an ingot having an end surface. The method includes an end surface measuring step of measuring undulation present on the end surface, and a separation plane forming step of setting the focal point of a laser beam inside the ingot at a predetermined depth from the end surface, which depth corresponds to the thickness of the wafer to be produced, and next applying the laser beam to the end surface to thereby form a separation plane containing a modified layer and cracks extending from the modified layer. The height of an objective lens for forming the focal point of the laser beam is controlled so that the focal point is set in the same plane to form the separation plane, according to the numerical aperture NA of the lens, the refractive index N of the ingot, and the undulation present on the end surface.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: September 25, 2018
    Assignee: DISCO CORPORATION
    Inventors: Kazuya Hirata, Yoko Nishino, Tomoki Yoshino
  • Patent number: 10079169
    Abstract: A method of forming a plurality of semiconductor devices includes applying a tape material to a back side of a semiconductor device having a silicon layer on the back side and a circuitry layer on the front side, lasing with an infrared laser the silicon layer through the tape material, lasing with a second laser the circuitry layer, and expanding the tape material for form a plurality of semiconductor devices. The second layer may be an ultraviolet laser. The lasers may be irradiated in a pattern on the bottom side and the top side. The second layer may form a groove in the circuitry layer that does not penetrate the silicon layer. The infrared laser may cleave a portion of the silicon lattice of the silicon layer. A coating may be applied to the circuitry layer prior to being irradiated with the second laser.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: September 18, 2018
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Andy E. Hooper, Nicholas Wade Clyde
  • Patent number: 10007387
    Abstract: Disclosed is a display device, a pressure detecting method and a pressure detecting device. Since a FPC electrode disposed on a side of a FPC board facing a display panel, an upper electrode for grounding disposed on a side of the display panel facing the flexible printed board and an elastically deformable dielectric material disposed between the FPC electrode and the upper electrode and contacting therewith respectively are additionally disposed between the FPC board and the upper electrode, or a FPC electrode disposed on a side of a FPC board facing a support frame and an elastically deformable dielectric material disposed between the FPC electrode and the support frame and contacting therewith respectively are additionally disposed between the FPC board and the support frame, it is possible to detect a magnitude of a pressure exerted on the display panel, thereby overcoming the defect that the existing display device can not realize pressure detection, thus improving user experience.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: June 26, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiangxiang Zou, Jiayang Zhou, Xuefei Wang