Having Specified Scribe Region Structure (e.g., Alignment Mark, Plural Grooves, Etc.) Patents (Class 438/462)
  • Patent number: 10468303
    Abstract: A device chip manufacturing method includes a passivation film removing step of removing a passivation film along each division line, a wafer dividing step of performing plasma etching using a fluorine-based gas to the front side of a wafer in the condition where the passivation film is used as a mask, thereby dividing the wafer along the division lines, and a die attach film removing step of performing plasma etching using an oxygen-based gas to the front side of the wafer in the condition where the passivation film is used as a mask, thereby removing a part or the whole of a die attach film along each division line.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: November 5, 2019
    Assignee: DISCO CORPORATION
    Inventor: Tomotaka Tabuchi
  • Patent number: 10431958
    Abstract: In an example, the present invention provides a gallium and nitrogen containing multilayered structure. The structure has a plurality of gallium and nitrogen containing semiconductor substrates, each of the gallium and nitrogen containing semiconductor substrates (“substrates”) having a plurality of epitaxially grown layers overlaying a top-side of each of the substrates. The structure has an orientation of a reference crystal direction for each of the substrates. The structure has a first handle substrate coupled to each of the substrates such that each of the substrates is aligned to a spatial region configured in a selected direction of the first handle substrate. The reference crystal direction for each of the substrates is parallel to the spatial region in the selected direction within 10 degrees or less.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: October 1, 2019
    Assignee: Soraa Laser Diode, Inc.
    Inventors: Melvin McLaurin, Alexander Sztein, Po Shan Hsu, James W. Raring
  • Patent number: 10421157
    Abstract: A method of forming an electrode structure for a capacitive touch sensor in a first transparent conductive layer (19) which is located on a first side of a glass substrate (5) on the second side of which is a color filter layer (11,12,13) over-coated with a transparent non-conductive layer (15) and a second transparent conductive layer (7), by a direct write laser scribing process using a pulsed solid state laser (22), the laser wavelength in the range 257 nm to 266 nm and a pulse length in the range 50 fs to 50 ns so grooves (21) are formed in the first transparent conductive layer (19) to electrically isolate areas of the first transparent conductive layer (19) on opposite sides of each groove (21). This selection of wavelength and pulse length enables the grooves (21) to be formed with substantially no damage to the underlying color filter layer (11, 12, 13), the transparent non-conductive layer (15) or the second transparent conductive layer (7) on the second side of the glass substrate (5).
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: September 24, 2019
    Assignee: M-SOLV LTD.
    Inventors: Yuk Kwan Chan, Camilo Prieto Rio
  • Patent number: 10424512
    Abstract: A sector-shaped wafer piece is processed according to the shape of the piece obtained by dividing a wafer into quarters. Information is collected on the shapes of four patterns of the quarter wafer pieces different in the position of a circular arc of an outer periphery and on processing feed quantities corresponding to the shapes of the four patterns. A pattern is selected by calculating a region of a square having vertical and horizontal sides equal to the two sides of the quarter wafer piece, imaging each of the sides to search for the presence/absence of a target pattern, and selecting that one of the four patterns to which the held quarter wafer piece corresponds. The held quarter wafer piece is processed along division lines with a processing feed quantity corresponding to the selected pattern.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: September 24, 2019
    Assignee: DISCO CORPORATION
    Inventor: Makoto Tanaka
  • Patent number: 10332777
    Abstract: A wafer processing method includes a liquid supplying step of supplying a liquid to the front side of a wafer, a close contact making step of pressing a protective film against the front side of the wafer with the liquid interposed therebetween, thereby bringing the protective film into close contact with the front side of the wafer, a protective member fixing step of covering the protective film, with a protective member formed from a liquid resin curable by external stimulus, thereby fixing the protective member through the protective film to the front side of the wafer, a grinding step of grinding the back side of the wafer to reduce the thickness of the wafer, and a peeling step of peeling the protective film and the protective member from the wafer thinned by the grinding step.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: June 25, 2019
    Assignee: Disco Corporation
    Inventor: Kazuma Sekiya
  • Patent number: 10204826
    Abstract: A method for fabricating semiconductor device includes the steps of: forming an inter-metal dielectric (IMD) layer on a substrate; forming a trench in the IMD layer; performing a treatment process to transform part of the IMD layer into a damaged layer adjacent to the trench; forming a protective layer on a sidewall of the damaged layer; forming a metal layer in the trench; and removing the damaged layer to form an air gap adjacent to the protective layer.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: February 12, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Min-Shiang Hsu, Yuan-Fu Ko, Chih-Sheng Chang
  • Patent number: 10177063
    Abstract: A method for manufacturing an element chip includes a protection film stacking step of staking a protection film to the element region, and the dividing region, the part of the exposed second damaged region and a protection film etching step of removing a part of the protection film which is stacked on the dividing region and the protection film which is stacked on the element region by exposing the substrate to second plasma and remaining the protection film for covering the part of the second damaged region. Furthermore, the method for manufacturing an element chip includes a plasma dicing step of dividing the substrate to a plurality of element chips by exposing the substrate to third plasma in a state where the second main surface is supported by a supporting member.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: January 8, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Bunzi Mizuno, Mitsuru Hiroshima, Shogo Okita, Noriyuki Matsubara, Atsushi Harikai
  • Patent number: 10081076
    Abstract: A wafer is produced from an ingot having an end surface. The method includes an end surface measuring step of measuring undulation present on the end surface, and a separation plane forming step of setting the focal point of a laser beam inside the ingot at a predetermined depth from the end surface, which depth corresponds to the thickness of the wafer to be produced, and next applying the laser beam to the end surface to thereby form a separation plane containing a modified layer and cracks extending from the modified layer. The height of an objective lens for forming the focal point of the laser beam is controlled so that the focal point is set in the same plane to form the separation plane, according to the numerical aperture NA of the lens, the refractive index N of the ingot, and the undulation present on the end surface.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: September 25, 2018
    Assignee: DISCO CORPORATION
    Inventors: Kazuya Hirata, Yoko Nishino, Tomoki Yoshino
  • Patent number: 10079169
    Abstract: A method of forming a plurality of semiconductor devices includes applying a tape material to a back side of a semiconductor device having a silicon layer on the back side and a circuitry layer on the front side, lasing with an infrared laser the silicon layer through the tape material, lasing with a second laser the circuitry layer, and expanding the tape material for form a plurality of semiconductor devices. The second layer may be an ultraviolet laser. The lasers may be irradiated in a pattern on the bottom side and the top side. The second layer may form a groove in the circuitry layer that does not penetrate the silicon layer. The infrared laser may cleave a portion of the silicon lattice of the silicon layer. A coating may be applied to the circuitry layer prior to being irradiated with the second laser.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: September 18, 2018
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Andy E. Hooper, Nicholas Wade Clyde
  • Patent number: 10007387
    Abstract: Disclosed is a display device, a pressure detecting method and a pressure detecting device. Since a FPC electrode disposed on a side of a FPC board facing a display panel, an upper electrode for grounding disposed on a side of the display panel facing the flexible printed board and an elastically deformable dielectric material disposed between the FPC electrode and the upper electrode and contacting therewith respectively are additionally disposed between the FPC board and the upper electrode, or a FPC electrode disposed on a side of a FPC board facing a support frame and an elastically deformable dielectric material disposed between the FPC electrode and the support frame and contacting therewith respectively are additionally disposed between the FPC board and the support frame, it is possible to detect a magnitude of a pressure exerted on the display panel, thereby overcoming the defect that the existing display device can not realize pressure detection, thus improving user experience.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: June 26, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiangxiang Zou, Jiayang Zhou, Xuefei Wang
  • Patent number: 9999138
    Abstract: A method of making connection elements for a microelectronic device is provided, including foil ling a conducting layer on a support on which there is at least one conducting pad located on a front face of the support opposite a back face thereof, the conducting layer including a first conducting portion in contact with at least one conducting pad, the first conducting portion extending on the front face and being connected to at least one second conducting portion extending in contact with at least one given wall of the support being located between the front and back faces and forming a non-zero angle with the front face; thinning the support at the back face to release one conducting end of the second conducting portion as a free conducting end projecting from the back face; and after the thinning, bending the free conducting end projecting from the back face.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: June 12, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Stephan Borel
  • Patent number: 9947606
    Abstract: A semiconductor device is disclosed including material for absorbing EMI and/or RFI. The device includes a substrate, one or more semiconductor die, and molding compound around the one or more semiconductor die. The material for absorbing EMI and/or RFI may be provided within or on a solder mask layer on the substrate, or within a dielectric core of the substrate. The device may further include EMI/RFI-absorbing material around the molding compound and in contact with the EMI/RFI-absorbing material on the substrate to completely enclose the one or more semiconductor die in EMI/RFI-absorbing material.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: April 17, 2018
    Assignee: SANDISK INFORMATION TECHNOLOGY (SHANGHAI) CO., LTD.
    Inventors: Dacheng Huang, Ye Bai, Kaiyou Qian, Chin-Tien Chiu
  • Patent number: 9935055
    Abstract: A method of manufacturing a semiconductor device includes forming a separation trench into a first main surface of a semiconductor substrate and removing substrate material from a second main surface of the semiconductor substrate, so as to thin the substrate to a thickness of less than 100 ?m, the second main surface being opposite to the first main surface, so as to uncover a bottom side of the trench. Additional methods of manufacturing semiconductor devices are provided.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: April 3, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Andreas Meiser, Markus Zundel, Martin Poelzl, Paul Ganitzer, Georg Ehrentraut
  • Patent number: 9887140
    Abstract: There is provided a wafer processing method for dividing a wafer having a plurality of devices formed in regions partitioned by a plurality of crossing division lines on a front surface of a substrate having a birefringent crystal structure, into individual device chips. The wafer processing method includes a detection step of detecting the division line formed on the front surface of the wafer by an imaging unit from the back side of the wafer. In the detection step, a polarizer disposed on an optical axis connecting an imaging element and an image forming lens provided in the imaging unit intercepts extraordinary light appearing due to birefringence in the substrate and guides ordinary light to the imaging element.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: February 6, 2018
    Assignee: DISCO CORPORATION
    Inventors: Noboru Takeda, Takumi Shotokuji
  • Patent number: 9865425
    Abstract: Disclosed herein is a sample holder which holds a sample such that a surface is exposed and can be mounted in each of multiple measurement devices that perform measurement based on different measurement principles so that properties of the sample can be measured by each of the measurement devices. The sample holder includes: a main body that surrounds the sample; alignment marks that are arranged at each of two or more different positions in a surface of the main body and can be detected by the measurement devices; and a sample-retaining portion that is disposed within the main body and retains the sample such that a height difference between a mark surface of the alignment mark and the surface of the sample is set to a predetermined value.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: January 9, 2018
    Assignee: HITACHI HIGH-TECH SCIENCE CORPORATION
    Inventor: Kazunori Ando
  • Patent number: 9859478
    Abstract: A light emitting device includes a first substrate, a second substrate and a plurality of micro epitaxial structures. The second substrate is disposed opposite to the first substrate. The micro epitaxial structures are periodically disposed on the substrate and located between the first substrate and the second substrate. A coefficient of thermal expansion of the first substrate is CTE1, a coefficient of thermal expansion of the second substrate is CTE2, a side length of each of the micro epitaxial structures is W, W is in the range between 1 micrometer and 100 micrometers, and a pitch of any two adjacent micro epitaxial structures is P, wherein W/P=0.1 to 0.95, and CTE2/CTE1=0.8 to 1.2.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: January 2, 2018
    Assignee: PlayNitride Inc.
    Inventors: Tzu-Yang Lin, Yu-Hung Lai, Yu-Yun Lo
  • Patent number: 9824926
    Abstract: A wafer is transferred to a holding surface of a chuck table by using a transfer unit having a suction pad. The front side of the wafer is held under suction through a protective tape on the holding surface, and the suction pad is removed from the back side of the wafer. A modified layer is formed on the back side of the wafer along division lines. The wafer is transferred by mounting the wafer held by the suction pad on the holding surface and sandwiching the wafer between the suction pad and the holding surface of the chuck table. A suction force is applied to the holding surface of the chuck table to thereby hold the front side of the wafer through the protective tape on the holding surface of the chuck table under suction, and the suction pad is then removed from the back side of the wafer.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: November 21, 2017
    Assignee: DISCO CORPORATION
    Inventor: Masaru Nakamura
  • Patent number: 9786562
    Abstract: A method is described of radiatively cutting a wafer, the method comprising the steps of low power cutting of two trenches followed by high power cutting of a fissure. A single pulsed radiation beam is split into a first pulsed radiation beam for cutting at least one of the trenches and a second pulsed radiation beam for cutting the fissure. When cutting a fissure on the wafer in a cutting direction along a cutting street, the first and second radiation beams are directed simultaneously with the first radiation beam leading and the second radiation beam trailing. For cutting a fissure in the opposite cutting direction, a third pulsed radiation beam for trenching is split from said single pulsed radiation beam.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: October 10, 2017
    Assignee: ASM TECHNOLOGY SINGAPORE PTE LTD
    Inventor: Karel Maykel Richard Van Der Stam
  • Patent number: 9780063
    Abstract: A semiconductor wafer has a plurality of semiconductor die with contact pads for electrical interconnect. An insulating layer is formed over the semiconductor wafer. A bump structure is formed over the contact pads. The bump structure has a buffer layer formed over the insulating layer and contact pad. A portion of the buffer layer is removed to expose the contact pad and an outer portion of the insulating layer. A UBM layer is formed over the buffer layer and contact pad. The UBM layer follows a contour of the buffer layer and contact pad. A ring-shaped conductive pillar is formed over the UBM layer using a patterned photoresist layer filled with electrically conductive material. A conductive barrier layer is formed over the ring-shaped conductive pillar. A bump is formed over the conductive barrier layer. The buffer layer reduces thermal and mechanical stress on the bump and contact pad.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: October 3, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: JoonYoung Choi, YoungJoon Kim, SungWon Cho
  • Patent number: 9700961
    Abstract: An ablation method of applying a laser beam to a die attach film to perform ablation. The ablation method includes a protective film forming step of applying a liquid resin containing a fine powder of oxide having absorptivity to the wavelength of the laser beam to at least a subject area of the die attach film to be ablated, thereby forming a protective film containing the fine powder on at least the subject area of the die attach film, and a laser processing step of applying the laser beam to the subject area coated with the protective film, thereby performing ablation through the protective film to the subject area of the die attach film after performing the protective film forming step.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: July 11, 2017
    Assignee: DISCO CORPORATION
    Inventor: Nobuyasu Kitahara
  • Patent number: 9673351
    Abstract: A method of manufacturing semiconductor chips includes: forming grooves on a front face side of a substrate; and forming grooves on a back face side of the substrate as defined herein, and in manufacturing conditions in which a variation range of a top section of the cutting member having a tapered tip end shape with no top face in the groove width direction changes from a range included in the groove on the front face side to a range away from the groove on the front face side as wear of the cutting member advances, the use of the cutting member is stopped before the variation range changes from the range included in the groove on the front face side to the range away from the groove on the front face side.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: June 6, 2017
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Takeshi Minamiru, Michiaki Murata, Kenji Yamazaki, Tsutomu Otsuka
  • Patent number: 9649775
    Abstract: A workpiece dividing method for dividing a platelike workpiece into a plurality of individual chips. The workpiece dividing method includes a workpiece preparing step of preparing the platelike workpiece, at least one side of the workpiece being formed as a mat surface, a holding step of holding the workpiece on a holding surface of a chuck table in the condition where the mat surface of the workpiece is exposed, a cut groove forming step of cutting the mat surface of the workpiece held on the holding surface of the chuck table by using a cutting blade to thereby form a cut groove with a remaining portion, and a laser cutting step of applying a laser beam to the workpiece along the cut groove to thereby cut the remaining portion.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: May 16, 2017
    Assignee: Disco Corporation
    Inventor: Satoshi Kumazawa
  • Patent number: 9601531
    Abstract: A wafer level packaging structure for image sensors and a wafer level packaging method for image sensors are provided. The wafer level packaging structure includes: a wafer to be packaged including multiple chip regions and scribe line regions between the chip regions; pads and image sensing regions located on a first surface of the wafer and located in the chip regions; first dike structures covering surfaces of the pads and the scribe line regions; a packaging cover arranged facing the first surface of the wafer; and second dike structures located on a surface of the packaging cover. The second dike structures are arranged corresponding to the scribe line regions. The packaging cover and the wafer are jointed fixedly via the second dike structures and the first dike structures.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: March 21, 2017
    Assignee: China Wafer Level CSP Co., Ltd.
    Inventors: Zhiqi Wang, Qiong Yu, Wei Wang
  • Patent number: 9583375
    Abstract: Methods and systems for forming water soluble masks by dry film lamination are described. Also described are methods of wafer dicing, including formation of a water soluble mask by dry film lamination. In one embodiment, a method involves moisturizing an inner area of a water soluble dry film. The method involves stretching the water soluble dry film over a surface of the semiconductor wafer, and attaching the moistened inner area of the stretched film to the surface of the semiconductor wafer. A method of wafer dicing may further involve patterning the water soluble dry film, exposing regions of the semiconductor wafer between the ICs, and etching the semiconductor wafer through gaps in the patterned water soluble dry film.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: February 28, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, James S. Papanu, Brad Eaton, Ajay Kumar
  • Patent number: 9555502
    Abstract: Methods and systems for forming a scribe line in a thin film stack on an inner surface of a thin film photovoltaic superstrate are provided via the use of a cleaning laser beam and a scribing laser beam. The cleaning laser beam is focused directly onto the exposed surface of the superstrate such that the cleaning laser beam removes debris from the exposed surface of the superstrate, and the scribing laser beam is focused through the exposed surface of the superstrate and onto the thin film stack such that the scribing laser beam passes through the superstrate to form a scribe within the thin film stack on the inner surface of the superstrate. The method and system can further utilize a conveyor to transport the superstrate in a machine direction to move the superstrate past the cleaning laser source and the scribing laser source.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: January 31, 2017
    Assignee: First Solar, Inc.
    Inventors: Scott Daniel Feldman-Peabody, William J. Schaffer
  • Patent number: 9548274
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a non-rectangular die area, a dicing ring and a reticle area surrounding the non-rectangular die. The dicing ring is within the reticle area and surrounds the non-rectangular die area. The number of edges of the reticle area is not equal to 4.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: January 17, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chen-Hua Yu, Ming-Fa Chen, Sung-Feng Yeh
  • Patent number: 9481051
    Abstract: A method for producing a hexagonal single crystal wafer from a hexagonal single crystal ingot includes a separation start point forming step of setting the focal point of a laser beam inside the ingot at a predetermined depth from the upper surface of the ingot, which depth corresponds to the thickness of the wafer to be produced, and next applying the laser beam to the upper surface of the ingot while relatively moving the focal point and the ingot to thereby form a modified layer parallel to the upper surface and cracks extending from the modified layer along a c-plane in the ingot, thus forming a separation start point. The ingot is immersed in water after forming the separation start point in the ingot, and ultrasonic vibration is applied to the ingot to thereby separate a plate-shaped member corresponding to the wafer from the ingot.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: November 1, 2016
    Assignee: DISCO CORPORATION
    Inventors: Kazuya Hirata, Yoko Nishino, Kunimitsu Takahashi
  • Patent number: 9484368
    Abstract: A solid-state imaging device includes a semiconductor substrate configured to include a solid-state imaging element that is provided with a photoelectric conversion region, and a scribe line region that is provided along a periphery of the solid-state imaging element, a wiring layer that is formed to be layered on the semiconductor substrate, a support substrate that is formed to be layered on the wiring layer, and a groove that is provided between a blade region in the scribe line region and the solid-state imaging element, in the semiconductor substrate and penetrates through the semiconductor substrate.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: November 1, 2016
    Assignee: Sony Corporation
    Inventor: Hiroyuki Kawashima
  • Patent number: 9484260
    Abstract: In one embodiment, die are singulated from a wafer having a back layer by placing the wafer onto a first carrier substrate with the back layer adjacent the carrier substrate, forming singulation lines through the wafer to expose the back layer within the singulation lines, and using a mechanical device to apply localized pressure to the wafer to separate the back layer in the singulation lines. The localized pressure can be applied through the first carrier substrate proximate to the back layer, or can be applied through a second carrier substrate attached to a front side of the wafer opposite to the back layer. Heat is applied to the first carrier substrate while the localized pressure is applied.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: November 1, 2016
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Gordon M. Grivna
  • Patent number: 9450197
    Abstract: A flexible display apparatus includes a plurality of pixels on a display area of a flexible substrate. A pad area is on a non-display area of the flexible substrate. A driving integrated circuit is electrically connected to the pad area. A support layer is on a surface of the flexible substrate opposite to a surface facing the driving integrated circuit. An adhesion layer attaches the support layer to the substrate. The adhesion layer has a first thickness in an area corresponding to the driving integrated circuit, and a second thickness in another area. The second thickness is less than the first thickness.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: September 20, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Jinsic Min
  • Patent number: 9368406
    Abstract: A method for manufacturing a semiconductor chip includes forming a front-side groove in a front surface of a substrate; forming a back-side groove wider than the front-side groove by a rotating cutting member from the back surface of the substrate toward the front-side groove; attaching a holding member having an adhesive layer to the back surface of the substrate after forming the back-side groove; dry-washing the back surface before attaching the holding member to the back surface; extending the distance between adjacent semiconductor chips by expanding the holding member attached to the back surface; and separating the semiconductor chips at the extended distance therebetween from the holding member.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: June 14, 2016
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Hirokazu Matsuzaki, Kenji Yamazaki, Michiaki Murata, Takahiro Hashimoto, Takeshi Minamiru
  • Patent number: 9343377
    Abstract: A method includes forming an integrated circuit device having device circuitry disposed in a device circuitry area on a substrate and a destroyable circuit formed in a destroyable circuitry area on the substrate; testing at least one operational aspect of the device circuitry using the destroyable circuit; and destroying the destroyable circuit subsequent to testing the at least one operational aspect of the device circuitry.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: May 17, 2016
    Assignee: GOOGLE INC.
    Inventors: Andy Yang, Benjamin Iver Gribstad, Don Stark, Shahriar Rabii, Srenik Mehta
  • Patent number: 9343365
    Abstract: The present invention provides a method for plasma processing a substrate, the method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; loading a work piece onto the work piece support, the work piece having a support film, a frame and the substrate; providing at least two cutting regions on the substrate, the cutting regions being positioned between all adjacent device structures on the substrate; generating a plasma using the plasma source; and processing the work piece using the generated plasma.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: May 17, 2016
    Assignee: Plasma-Therm LLC
    Inventors: Thierry Lazerand, David Pays-Volard, Linnell Martinez, Chris Johnson, Russell Westerman, Gordon M. Grivna
  • Patent number: 9343366
    Abstract: Approaches for hybrid laser scribe and plasma etch dicing process for a wafer having backside solder bumps are described. For example, a method of dicing a semiconductor wafer having integrated circuits on a front side thereof and corresponding arrays of metal bumps on a backside thereof involves applying a dicing tape to the backside of the semiconductor wafer, the dicing tape covering the arrays of metal bumps. The method also involves, subsequently, forming a mask on the front side of the semiconductor wafer, the mask covering the integrated circuits. The method also involves forming scribe lines on the front side of the semiconductor wafer with a laser scribing process, the scribe lines formed in the mask and between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the scribe lines to singulate the integrated circuits, the mask protecting the integrated circuits during the plasma etching.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: May 17, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, James S. Papanu, Aparna Iyer, Brad Eaton, Ajay Kumar
  • Patent number: 9308714
    Abstract: A compliant material is formed between a base substrate and a support structure prior to performing a controlled spalling process. By positioning the compliant material between the base substrate and the support structure, the localized effects of surface perturbations (particles, wafer artifacts, etc.) on spalling mode fracture can be reduced. The method of the present disclosure thus leads to improved surface quality of the spalled material layer and the remaining base substrate. Moreover, the method of the present disclosure can reduce the density of cleaving artifacts.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: April 12, 2016
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Devendra K. Sadana
  • Patent number: 9299670
    Abstract: A stacked microelectronic package can comprise a package body having an external vertical package sidewall, a plurality of microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the external vertical package sidewall. A cavity is formed on an external surface of the package body between a first one of the package edge conductors and a second one of the package edge conductors. Electrically conductive material is in the cavity and in electrical contact with a first and a second one of the package edge conductors, wherein the conductive material in the cavity is within planform dimensions of the microelectronic package.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 29, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Weng F. Yap, Michael B. Vincent, Jason R. Wright
  • Patent number: 9301387
    Abstract: A PCB according to an exemplary embodiment of the present disclosure includes a plurality of unit PCBs arrayed on the PCB, and a sawing line formed among the plurality of unit PCBs. The sawing line disposed among the dummy unit PCBs is formed with a conductive pad including a first layer formed with a PSR (Photo Solder Resistor) and a second layer on which the PSR is removed to open the conductive pad. Burr generation on the unit PCBs during a sawing process is prevented and a dummy area can be reduced.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: March 29, 2016
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Chung Sang Ryou
  • Patent number: 9293304
    Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a plasma thermal shield for a plasma processing chamber includes an annular ring body having an inner opening. A plasma-facing surface of the annular ring body has a general topography. A bottom surface of the annular ring body reciprocates the general topography with recessed regions disposed therein, providing one or more protruding regions at the bottom surface of the annular ring body.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: March 22, 2016
    Assignee: Applied Materials, Inc.
    Inventor: Alan Hiroshi Ouye
  • Patent number: 9275902
    Abstract: Approaches for front side laser scribe plus backside bump formation and laser scribe and plasma etch dicing process are described. For example, a method of dicing a semiconductor wafer having integrated circuits on a front side thereof involves forming first scribe lines on the front side, between the integrated circuits, with a first laser scribing process. The method also involves forming arrays of metal bumps on a backside of the semiconductor wafer, each array corresponding to one of the integrated circuits. The method also involves forming second scribe lines on the backside, between the arrays of metal bumps, with a second laser scribing process, wherein the second scribe lines are aligned with the first scribe lines. The method also involves plasma etching the semiconductor wafer through the second scribe lines to singulate the integrated circuits.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: March 1, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, James S. Papanu, Aparna Iyer, Brad Eaton, Ajay Kumar
  • Patent number: 9275924
    Abstract: A semiconductor package includes a passivation layer overlying a semiconductor substrate, a bump overlying the passivation layer, and a molding compound layer overlying the passivation layer and covering a lower portion of the bump. A sidewall of the passivation layer is covered by the molding compound layer.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: March 1, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Ding Wang, Jung Wei Cheng, Bo-I Lee
  • Patent number: 9269604
    Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of reducing edge warping in a supported semiconductor wafer involves adhering a backside of a semiconductor wafer to an inner portion of a carrier tape of a substrate carrier comprising a tape frame mounted above the carrier tape. The method also involves adhering an adhesive tape to a front side of the semiconductor wafer and to at least a portion of the substrate carrier. The adhesive tape includes an opening exposing an inner region of the front side of the semiconductor wafer.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: February 23, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Brad Eaton, Ajay Kumar
  • Patent number: 9263362
    Abstract: A method includes providing a first semiconductor chip comprising a ring-shaped metal structure extending along a contour of a first main surface of the semiconductor chip. The method includes encapsulating the first semiconductor chip with an encapsulation body thereby defining a second main surface and depositing a metal layer over the first semiconductor chip and the encapsulation body. A plurality of external contact pads are placed over the second main surface of the encapsulation body, the metal layer electrically coupling at least one external contact pad of the plurality of external contact pads to the ring-shaped metal structure. A seal ring is placed between the ring-shaped metal structure and the contour of the first main surface of the first semiconductor chip.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: February 16, 2016
    Assignee: Infineon Technologies AG
    Inventors: Rudolf Lachner, Josef Boeck, Klaus Aufinger, Herbert Knapp
  • Patent number: 9236290
    Abstract: A method for producing a semiconductor device having a sidewall insulation includes providing a semiconductor body having a first side and a second side lying opposite the first side. At least one first trench is at least partly filled with insulation material proceeding from the first side in the direction toward the second side into the semiconductor body. The at least one first trench is produced between a first semiconductor body region for a first semiconductor device and a second semiconductor body region for a second semiconductor device. An isolating trench extends from the first side of the semiconductor body in the direction toward the second side of the semiconductor body between the first and second semiconductor body regions in such a way that at least part of the insulation material of the first trench adjoins at least a sidewall of the isolating trench. The second side of the semiconductor body is partly removed as far as the isolating trench.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: January 12, 2016
    Assignee: Infineon Technologies AG
    Inventors: Carsten Ahrens, Rudolf Berger, Manfred Frank, Uwe Hoeckele, Bernhard Knott, Ulrich Krumbein, Wolfgang Lehnert, Berthold Schuderer, Juergen Wagner, Stefan Willkofer
  • Patent number: 9236284
    Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a tape frame lift assembly for a plasma processing chamber includes a capture single ring having an upper surface for supporting a tape frame of a substrate support and for cooling the tape frame. The tape frame lift assembly also includes one or more capture lift arms for moving the capture single ring to and from transfer and processing positions. The tape frame assembly also includes one or more captured lift plate portions, one captured lift plate portion corresponding to one capture lift arm, the one or more captured lift plate portions for coupling the one or more capture lift arms to the capture single ring.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: January 12, 2016
    Assignee: Applied Materials, Inc.
    Inventor: Alan Hiroshi Ouye
  • Patent number: 9231018
    Abstract: A wafer level packaging structure for image sensors and a wafer level packaging method for image sensors are provided. The wafer level packaging structure includes: a wafer to be packaged including multiple chip regions and scribe line regions between the chip regions; pads and image sensing regions located on a first surface of the wafer and located in the chip regions; first dike structures covering surfaces of the pads; a packaging cover arranged facing the first surface of the wafer; and second dike structures located on a surface of the packaging cover. Projections of the second dike structures onto the first surface of the wafer are included in the scribe line regions. The packaging cover and the wafer are jointed fixedly via the second dike structures, while tops of the first dike structures and the surface of the packaging cover are contacted.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: January 5, 2016
    Assignee: China Wafer Level CSP Co., Ltd.
    Inventors: Zhiqi Wang, Qiong Yu, Wei Wang
  • Patent number: 9224625
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The semiconductor wafer is disposed on a water-soluble die attach film. The mask covers and protects the integrated circuits. The mask is patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to form singulated integrated circuits. The water-soluble die attach film is then patterned with an aqueous solution.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: December 29, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Madhava Rao Yalamanchili, Brad Eaton, Saravjeet Singh, Ajay Kumar
  • Patent number: 9218992
    Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The semiconductor wafer is supported by a substrate carrier. The mask is then patterned with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits while supported by the substrate carrier.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: December 22, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Saravjeet Singh, Brad Eaton, Ajay Kumar, Wei-Sheng Lei, James M. Holden, Madhava Rao Yalamanchili, Todd J. Egan
  • Patent number: 9214423
    Abstract: In one embodiment, a method of forming a HEMT device may include plating a conductor or a plurality of conductors onto an insulator that overlies a plurality of current carrying electrodes of the HEMT device. The method may also include attaching a connector onto the conductor or attaching a plurality of connectors onto the plurality of conductors.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: December 15, 2015
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Ali Salih, Chun-Li Liu, Gordon M. Grivna
  • Patent number: 9209143
    Abstract: An apparatus comprises a first integrated circuit (IC) die that includes a top layer, a bottom surface, a sidewall surface extending from a top surface of the top layer to the bottom surface, and at least one multi-surface contact pad, a second IC die including a top layer, a bottom surface, a sidewall surface extending from a top surface of the top layer to the bottom surface, and at least one multi-surface contact pad, wherein the second IC die is arranged adjacent to the first IC die, and includes an electrically conductive bond in contact with at least one of the top surface or the side surface of the multi-surface contact pad of the first IC die and the top surface of the multi-surface contact pad of the second IC die.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: December 8, 2015
    Assignee: Intel IP Corporation
    Inventors: Georg Seidemann, Sven Albers, Teodora Ossiander, Michael Skinner, Hans-Joachim Barth, Harald Gossner, Reinhard Mahnkopf, Christian Mueller, Wolfgang Molzer
  • Patent number: 9206037
    Abstract: A MEMS device chip manufacturing method including a grinding step of grinding a device forming area of a wafer to thereby form a recess and an annular reinforcing portion surrounding the recess, a MEMS device forming step of performing any processing including etching to the wafer after performing the grinding step to thereby form a plurality of MEMS devices partitioned by a plurality of crossing division lines in the device forming area, and a dividing step of dividing the wafer along the division lines after performing the MEMS device forming step to thereby manufacture a plurality of MEMS device chips.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: December 8, 2015
    Assignee: Disco Corporation
    Inventors: Aris Bernales, Devin Martin, Mark Brown