Having Specified Scribe Region Structure (e.g., Alignment Mark, Plural Grooves, Etc.) Patents (Class 438/462)
  • Patent number: 9029200
    Abstract: A method for manufacturing semiconductor devices is disclosed. In one embodiment a semiconductor substrate having a first surface, a second surface opposite to the first surface and a plurality of semiconductor components is provided. The semiconductor substrate has a device thickness. At least one metallization layer is formed on the second surface of the semiconductor substrate. The metallization layer has a thickness which is greater than the device thickness.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: May 12, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Rudolf Zelsacher, Paul Ganitzer
  • Publication number: 20150123264
    Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions. The contact layer is disposed in the kerf region and the device regions. A structured solder layer is formed over the device regions. The contact layer is exposed at the kerf region after forming the structured solder layer. The contact layer and the substrate in the kerf regions are diced.
    Type: Application
    Filed: November 1, 2013
    Publication date: May 7, 2015
    Inventors: Evelyn Napetschnig, Ulrike Fastner, Alexander Heinrich, Thomas Fischer
  • Patent number: 9023717
    Abstract: To provide a semiconductor device having improved reliability. A method of manufacturing a semiconductor device according to one embodiment includes a step of cutting, in a dicing region arranged between two chip regions adjacent to each other, a wafer along an extending direction of the dicing region. The dicing region has therein a plurality of metal patterns in a plurality of columns. In the step of cutting the wafer, one or more of the columns of metal patterns formed in a plurality of columns are removed, and the metal patterns of the column(s) different from the above-mentioned one or more of the columns are not removed.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: May 5, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuyuki Nakagawa, Shunichi Abe
  • Publication number: 20150118827
    Abstract: A method of manufacturing a semiconductor device includes: forming electrodes on a first major surface of a semiconductor substrate having first and second major surfaces facing in opposite directions; and forming a cleavage-inducing pattern on the first major surface of the semiconductor substrate. The cleavage-inducing pattern extends over a target cleavage position located between the electrodes, has a recess extending over the target cleavage position, and is made of a material different from the material of the semiconductor substrate. The method includes forming a scribed groove in the second major surface of the semiconductor substrate and in a position facing the target cleavage position; and cleaving the semiconductor substrate having the scribed groove and the cleavage-inducing pattern by applying pressure, through a cleaving blade, to the first major surface of the semiconductor substrate.
    Type: Application
    Filed: July 3, 2014
    Publication date: April 30, 2015
    Inventors: Chikara Watatani, Masato Negishi
  • Patent number: 9018073
    Abstract: A method of manufacturing a semiconductor device includes: forming a recessed portion in a semiconductor substrate; forming an insulating film in the recessed portion; after forming the insulating film, forming a silicide layer on the semiconductor substrate in contact with the insulating film; and performing alignment between an electron beam exposure apparatus and the semiconductor substrate by using the insulating film and the silicide layer as an alignment mark.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: April 28, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Makoto Kawano, Shigeki Yoshida
  • Patent number: 9018079
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask is patterned with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. Subsequent to patterning the mask, the exposed regions of the semiconductor wafer are cleaned with a plasma process reactive to the exposed regions of the semiconductor wafer. Subsequent to cleaning the exposed regions of the semiconductor wafer, the semiconductor wafer is plasma etched through the gaps in the patterned mask to singulate the integrated circuits.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: April 28, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Brad Eaton, Madhava Rao Yalamanchili, Ajay Kumar
  • Publication number: 20150111321
    Abstract: A method for processing a silicon substrate, comprising the steps of providing a silicon substrate having a first surface and a second surface, forming a non-penetrated hole extending from the first surface toward the second surface side in the silicon substrate, sticking a sealing tape comprising a support member and an adhesive layer on the first surface and filling at least part of the non-penetrated hole with the adhesive layer, performing reactive ion etching from the second surface toward the first surface side to allow the reactive ion etching to reach the adhesive layer filled in the non-penetrated hole and to expose the adhesive layer, and peeling the sealing tape from the silicon substrate to form a through hole in the silicon substrate.
    Type: Application
    Filed: October 20, 2014
    Publication date: April 23, 2015
    Inventors: Seiko Minami, Toshiyasu Sakai, Masataka Kato, Masaya Uyama, Hiroshi Higuchi, Yoshinao Ogata
  • Publication number: 20150111364
    Abstract: Maskless hybrid laser scribing and plasma etching wafer dicing processes are described. In an example, a method of dicing a semiconductor wafer having a front surface with a plurality of integrated circuits thereon and having a passivation layer disposed between and covering metal pillar/solder bump pairs of the integrated circuits involves laser scribing, without the use of a mask layer, the passivation layer to provide scribe lines exposing the semiconductor wafer. The method also involves plasma etching the semiconductor wafer through the scribe lines to singulate the integrated circuits, wherein the passivation layer protects the integrated circuits during at least a portion of the plasma etching. The method also involves thinning the passivation layer to partially expose the metal pillar/solder bump pairs of the integrated circuits.
    Type: Application
    Filed: August 7, 2014
    Publication date: April 23, 2015
    Inventors: Wei-Sheng Lei, Brad Eaton, James S. Papanu, Ajay Kumar
  • Publication number: 20150111363
    Abstract: Maskless hybrid laser scribing and plasma etching wafer dicing processes are described. In an example, a method of dicing a semiconductor wafer having a front surface with a plurality of integrated circuits thereon and having a passivation layer disposed between and covering metal pillar/solder bump pairs of the integrated circuits involves laser scribing, without the use of a mask layer, the passivation layer to provide scribe lines exposing the semiconductor wafer. The method also involves plasma etching the semiconductor wafer through the scribe lines to singulate the integrated circuits, wherein the passivation layer protects the integrated circuits during at least a portion of the plasma etching. The method also involves thinning the passivation layer to partially expose the metal pillar/solder bump pairs of the integrated circuits.
    Type: Application
    Filed: October 22, 2013
    Publication date: April 23, 2015
    Inventors: Wei-Sheng Lei, Brad Eaton, James S. Papanu, Ajay Kumar
  • Patent number: 9012304
    Abstract: In one embodiment, a method of singulating semiconductor die from a semiconductor wafer includes forming a material on a surface of a semiconductor wafer and reducing a thickness of portions of the material. Preferably, the thickness of the material is reduced near where singulation openings are to be formed in the semiconductor wafer.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: April 21, 2015
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gordon M. Grivna, John M. Parsey, Jr.
  • Patent number: 9012305
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask is patterned with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. Subsequent to patterning the mask, the exposed regions of the semiconductor wafer are cleaned with an anisotropic plasma process non-reactive to the exposed regions of the semiconductor wafer. Subsequent to cleaning the exposed regions of the semiconductor wafer, the semiconductor wafer is plasma etched through the gaps in the patterned mask to singulate the integrated circuits.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: April 21, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Jungrae Park, James S. Papanu, Brad Eaton, Ajay Kumar
  • Patent number: 9010225
    Abstract: A dicing apparatus according to a first aspect of the present invention includes: a work table on which a work is mounted; a processing device which processes the work; an imaging device which images the work on the work table; a plurality of moving device which move the work table, the processing device, and the imaging device relatively to each other; and an alignment camera which is provided on the same moving device as the work table so as to face the imaging device, and which performs imaging in the direction toward the portion where the imaging device is provided. According to the dicing apparatus configured in this way, it is possible to easily measure the relative position of the imaging device and the processing device without processing a dummy work, and it is possible to perform excellent dicing processing without lowering the efficiency of the dicing apparatus.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: April 21, 2015
    Assignee: Tokyo Seimitsu Co., Ltd.
    Inventor: Yoshitami Hojo
  • Publication number: 20150104929
    Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a front surface having a plurality of integrated circuits thereon involves forming a mask layer above the front surface of the semiconductor wafer. The method also involves laser scribing the mask layer and the front surface of the semiconductor wafer to provide scribe lines in the mask layer and partially into the semiconductor wafer. The laser scribing involves use of a dual focus lens to provide a dual focus spot beam. The method also involves etching the semiconductor wafer through the scribe lines to singulate the integrated circuits.
    Type: Application
    Filed: December 11, 2013
    Publication date: April 16, 2015
    Inventors: Wei-Sheng Lei, Brad Eaton, Ajay Kumar
  • Publication number: 20150104930
    Abstract: A wafer processing method divides a wafer into a plurality of individual devices along a plurality of crossing division lines formed on the front side of the wafer. The method includes a functional layer removing step of applying a CO2 laser beam to the wafer along each division line with the spot of the CO2 laser beam, having a width corresponding to the width of each division line set on the upper surface of each division line, thereby removing a functional layer along each division line to form a groove along each division line where the functional layer has been removed, and a groove shaping and debris removing step of applying a laser beam having a wavelength in the ultraviolet region to the wafer along each groove, thereby removing debris sticking to the bottom surface of each groove and also shaping the side walls of each groove.
    Type: Application
    Filed: October 14, 2014
    Publication date: April 16, 2015
    Inventors: Chikara Aikawa, Kunimitsu Takahashi, Nobuyasu Kitahara, Seiji Fujiwara, Yoshiaki Yodo, Junichi Kuki
  • Patent number: 9006051
    Abstract: An object is to improve water resistance and reliability of a semiconductor device by reducing the degree of peeling of a film. In a semiconductor device, a first inorganic insulating layer, a semiconductor element layer, a second inorganic insulating layer, an organic insulating layer, and a third inorganic insulating layer are sequentially stacked over a substrate. The second inorganic insulating layer is in contact with the first inorganic insulating layer in an opening portion provided in the semiconductor element layer. The third inorganic insulating layer is in contact with the second inorganic insulating layer in an opening portion provided in the organic insulating layer. In a region where the second inorganic insulating layer and the third inorganic insulating layer are in contact with each other, the second inorganic insulating layer has a plurality of irregularities or openings.
    Type: Grant
    Filed: April 14, 2009
    Date of Patent: April 14, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiaki Oikawa, Masayuki Kajiwara, Masataka Nakada, Masami Jintyou, Shunpei Yamazaki
  • Patent number: 9006896
    Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a device region formed in the semiconductor substrate; a dielectric layer disposed on the first surface of the semiconductor substrate; a conducting pad structure located in the dielectric layer and electrically connected to the device region, wherein the conducting pad structure comprises a stacked structure of a plurality of conducting pad layers; a support layer disposed on a top surface of the conducting pad structure; and a protection layer disposed on the second surface of the semiconductor substrate.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: April 14, 2015
    Assignee: Xintec Inc.
    Inventors: Yu-Lung Huang, Tsang-Yu Liu, Shu-Ming Chang
  • Publication number: 20150099346
    Abstract: In a wafer processing method, the back side of the wafer is ground to reduce the thickness of the wafer to a predetermined thickness. A modified layer is formed by applying a laser beam to the wafer from the back side of the wafer along each division line with the focal point of the laser beam set inside the wafer. The wafer is mounted on a reinforcing sheet having an insulating function on the back side of the wafer and a dicing tape is attached to the reinforcing sheet. The peripheral portion of the dicing tape is supported by an annular frame. The wafer is heated, which also heats the reinforcing sheet, thereby hardening the reinforcing sheet. An external force is applied to the wafer to divide the wafer into individual devices along each division line and to also break the reinforcing sheet along the individual devices.
    Type: Application
    Filed: October 1, 2014
    Publication date: April 9, 2015
    Inventors: Yohei Yamashita, Kenji Furuta, Yoshiaki Yodo
  • Patent number: 8999818
    Abstract: A semiconductor element is formed on a first surface of the substrate. A resin layer is formed over a second surface of the substrate which is opposite to the first surface of the substrate and on a part of the side surface of the substrate. A step is formed on the side surface of the substrate. The width of the upper section of the substrate with a step is narrower than the lower section of the substrate with a step. Therefore, the substrate can also be a protrusion.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: April 7, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Takahashi, Daiki Yamada, Yohei Monma, Hiroki Adachi, Shunpei Yamazaki
  • Patent number: 8999816
    Abstract: Approaches for protecting a wafer during plasma etching wafer dicing processes are described. In an example, a method of dicing a semiconductor wafer with a front surface having a plurality of integrated circuits thereon involves laminating a pre-patterned mask on the front surface of the semiconductor wafer. The pre-patterned mask covers the integrated circuits and exposes streets between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the streets to singulate the integrated circuits. The pre-patterned mask protects the integrated circuits during the plasma etching.
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: April 7, 2015
    Assignee: Applied Materials, Inc.
    Inventors: James M. Holden, Aparna Iyer, Brad Eaton, Ajay Kumar
  • Publication number: 20150093882
    Abstract: A wafer processing method of processing a wafer having a plurality of devices formed on the front side of the wafer, the devices being respectively formed in a plurality of separate regions defined by a plurality of crossing division lines. The wafer processing method includes a support member providing step of providing a support member on the back side of the wafer, the support member having substantially the same size as that of the wafer, and a dividing step of dicing the wafer from the front side thereof along the division lines after performing the support member providing step, thereby dividing the wafer into a plurality of chips.
    Type: Application
    Filed: September 17, 2014
    Publication date: April 2, 2015
    Inventor: Kazuhisa Arai
  • Patent number: 8993413
    Abstract: A method of manufacturing a semiconductor device includes the steps of preparing a semiconductor wafer having a thick portion in an outer circumferential end portion and a thin portion in a central portion, attaching a support material to one surface of the semiconductor wafer, dividing the semiconductor wafer into the thick portion and the thin portion, and cutting the thin portion, after the division, while supporting the thin portion by the support material.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: March 31, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazunari Nakata, Yoshiaki Terasaki
  • Patent number: 8987867
    Abstract: A wafer includes a first die, a second die, and a scribe lane located between the first die and the second die. The scribe lane includes a first doped silicon region, and does not directly contact the first die and the second die.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: March 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji Hyun Lee, Jong Hyoung Lim
  • Patent number: 8987734
    Abstract: The present invention provides a semiconductor wafer, semiconductor package and semiconductor process. The semiconductor wafer includes a substrate, at least one metal segment and a plurality of dielectric layers. The semiconductor wafer is defined as a plurality of die areas and a plurality of trench areas, each of the die areas has an integrated circuit including a plurality of patterned metal layers disposed between the dielectric layers. The trench areas are disposed between the die areas, and the at least one metal segment is disposed in the trench area and insulated from the integrated circuit of the die area.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 24, 2015
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Yung-Hui Wang
  • Patent number: 8987020
    Abstract: A method for manufacturing a semiconductor light-emitting device includes forming a multilayer body including a first semiconductor layer having a first major surface and a second major surface which is an opposite side from the first major surface, a second semiconductor layer including a light-emitting layer laminated on the second major surface of the first semiconductor layer, and electrodes formed on the second major surface of the first semiconductor layer and on a surface of the second semiconductor layer on an opposite side from the first semiconductor layer. The method includes forming a groove through the first semiconductor layer. The method includes forming a phosphor layer on the first major surface and on a side surface of the first semiconductor layer in the groove.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: March 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiro Kojima, Yoshiaki Sugizaki
  • Publication number: 20150079761
    Abstract: Approaches for backside laser scribe plus front side laser scribe and plasma etch dicing of a wafer or substrate are described. For example, a method of dicing a semiconductor wafer having a plurality of integrated circuits on a front side thereof and metallization on a backside thereof involves patterning the metallization on the backside with a first laser scribing process to provide a first plurality of laser scribe lines on the backside. The method also involves forming a mask on the front side. The method also involves patterning, from the front side, the mask with a second laser scribing process to provide a patterned mask with a second plurality of scribe lines exposing regions of the semiconductor wafer between the integrated circuits, wherein the second plurality of scribe lines is aligned with the first plurality of scribe lines. The method also involves plasma etching the semiconductor wafer through the second plurality of scribe lines to singulate the integrated circuits.
    Type: Application
    Filed: December 11, 2013
    Publication date: March 19, 2015
    Inventors: Wei-Sheng Lei, Brad Eaton, Ajay Kumar
  • Publication number: 20150079760
    Abstract: Alternating masking and laser scribing approaches for wafer dicing using laser scribing and plasma etch are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits includes forming a first mask above the semiconductor wafer. The first mask is patterned with a first laser scribing process to provide a patterned first mask with a first plurality of scribe lines exposing regions of the semiconductor wafer between the integrated circuits. Subsequent to patterning the first mask with the first laser scribing process, a second mask is formed above the patterned first mask. The second mask is patterned with a second laser scribing process to provide a patterned second mask with a second plurality of scribe lines exposing regions of the semiconductor wafer between the integrated circuits. The second plurality of scribe lines is aligned with and overlaps the first plurality of scribe lines.
    Type: Application
    Filed: December 11, 2013
    Publication date: March 19, 2015
    Inventors: Wei-Sheng Lei, Ajay Kumar, Brad Eaton
  • Patent number: 8980727
    Abstract: Approaches for patterning semiconductor or other wafers and dies are described. For example, a method of patterning features within a substrate involves forming a mask layer above a surface of a semiconductor or glass substrate. The method also involves laser ablating the mask layer to provide a pattern of openings through the mask layer. The method also involves plasma etching portions of the semiconductor or glass substrate through the pattern of openings to provide a plurality of trenches in the semiconductor or glass substrate. The plurality of trenches has a pattern corresponding to the pattern of openings and comprising a pattern of through-substrate-via openings or redistribution layer (RDL) openings. The method also involves, subsequent to the plasma etching, removing the mask layer.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: March 17, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Brad Eaton, Ajay Kumar
  • Patent number: 8980697
    Abstract: A reconfigured wafer of resin-encapsulated semiconductor packages is obtained by supporting with a resin, thereafter, a grinding process is performed on top and backside surfaces to expose only a bump interconnection electrode on a surface of a semiconductor chip. Further, a chip-scale package is obtained by a dicing process along a periphery of the chip.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: March 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Yamada, Yutaka Onozuka, Atsuko Iida, Kazuhiko Itaya
  • Patent number: 8980726
    Abstract: Methods of dicing substrates having a plurality of ICs. A method includes forming a mask, patterning the mask with a femtosecond laser scribing process to provide a patterned mask with gaps, and ablating through an entire thickness of a semiconductor substrate to singulate the IC. Following laser-based singulation, a plasma etch is performed to remove a layer of semiconductor sidewall damaged by the laser scribe process. In the exemplary embodiment, a femtosecond laser is utilized and a 1-3 ?m thick damage layer is removed with the plasma etch. Following the plasma etch, the mask is removed, rendering the singulated die suitable for assembly/packaging.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: March 17, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Aparna Iyer, Brad Eaton, Madhava Rao Yalamanchili, Ajay Kumar
  • Publication number: 20150072506
    Abstract: A wafer is divided into a plurality of individual devices along a plurality of crossing division lines formed on the front side of the wafer. The wafer has a substrate, a functional layer formed on the front side of the substrate, and an SiO2 film formed on the front side of the functional layer. The individual devices are formed from the functional layer and partitioned by the division lines. The functional layer is removed by applying a laser beam to the wafer along each division line to thereby remove the functional layer along each division line. The laser beam has an absorption wavelength to the SiO2 film with high absorptivity due to the stretching vibration of an O—H bond or a C—H bond remaining in the SiO2 film. The wafer is then divided into the individual devices.
    Type: Application
    Filed: September 5, 2014
    Publication date: March 12, 2015
    Inventor: Keiji Nomaru
  • Publication number: 20150071585
    Abstract: A fabrication technique for cleaving a substrate in an integrated circuit is described. During this fabrication technique, a trench is defined on a back side of a substrate. For example, the trench may be defined using photoresist and/or a mask pattern on the back side of the substrate. The trench may extend from the back side to a depth less than a thickness of the substrate. Moreover, a buried-oxide layer and a semiconductor layer may be disposed on a front side of the substrate. In particular, the substrate may be included in a silicon-on-insulator technology. By applying a force proximate to the trench, the substrate may be cleaved to define a surface, such as an optical facet. This surface may have high optical quality and may extend across the substrate, the buried-oxide layer and the semiconductor layer.
    Type: Application
    Filed: September 11, 2013
    Publication date: March 12, 2015
    Applicant: Oracle International Corporation
    Inventors: Jin Hyoung Lee, Ivan Shubin, Xuezhe Zheng, II, Ashok V. Krishnamoorthy
  • Publication number: 20150072507
    Abstract: A device wafer has a plurality of devices individually formed in a plurality of separate regions on the front side of the wafer, the separate regions being defined by a plurality of crossing division lines. The wafer is processed by imaging the front side of the wafer to detect and store a target pattern, holding the front side of the wafer and grinding the back side of the wafer to thereby reduce the thickness to a predetermined thickness, imaging the front side of the wafer and next positioning the wafer with respect to a ring frame according to the target pattern stored so that the wafer is oriented to a predetermined direction, and attaching an adhesive tape to the back side of the wafer to thereby mount the wafer through the adhesive tape to the ring frame.
    Type: Application
    Filed: September 9, 2014
    Publication date: March 12, 2015
    Inventor: Kazuma Sekiya
  • Publication number: 20150069578
    Abstract: Consistent with an example embodiment, there is a method for preparing integrated circuit (IC) device die from a wafer substrate having a front-side with active devices and a back-side. The method comprises pre-grinding the backside of a wafer substrate to a thickness. The front-side of the wafer is mounted onto a protective foil. A laser is applied to the backside of the wafer, at first focus depth to define a secondary modification zone in saw lanes. To the backside of the wafer, a second laser process is applied, at a second focus depth shallower than that of the first focus depth, in the saw lanes to define a main modification zone, the secondary modification defined at a pre-determined location within active device boundaries, the active device boundaries defining an active device area. The backside of the wafer is ground down to a depth so as to remove the main modification zone. The IC device die are separated from one another by stretching the protective foil.
    Type: Application
    Filed: March 11, 2014
    Publication date: March 12, 2015
    Applicant: NXP B.V.
    Inventors: Hartmut BUENNING, Sascha MOELLER, Guido ALBERMANN, Martin LAPKE, Thomas ROHLEDER
  • Publication number: 20150069576
    Abstract: A method includes providing a semiconductor wafer including multiple semiconductor chips, forming a first scribe line on a frontside of the semiconductor wafer, wherein the first scribe line has a first width and separates semiconductor chips of the semiconductor wafer, forming a second scribe line on the frontside of the semiconductor wafer, wherein the second scribe line has a second width and separates semiconductor chips of the semiconductor wafer, wherein the first scribe line and the second scribe line intersect in a crossing area which is greater than a product of the first width and the second width, and plasma etching the semiconductor wafer in the crossing area.
    Type: Application
    Filed: September 12, 2013
    Publication date: March 12, 2015
    Inventors: Franco Mariani, Andreas Bauer, Reinhard Hess, Gerhard Leschik
  • Patent number: 8975097
    Abstract: A method of manufacturing a liquid discharge head includes: forming a first hole which penetrates through a wafer and becomes at least part of a liquid supply port and a second hole which does not penetrate through the wafer and becomes at least part of a cut-off portion from a front side of the wafer; arranging a dry film on the front side of the wafer; forming a flow passage forming member by heating and developing the dry film; and cutting off the liquid discharge head from the wafer by grinding the wafer from a back side so that the second hole penetrates through the wafer.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: March 10, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masahisa Watanabe, Kenji Fujii, Keisuke Kishimoto, Ryotaro Murakami
  • Patent number: 8975161
    Abstract: A dicing/die bonding integral film of the present invention includes a base film, a pressure-sensitive adhesive layer which is formed on the base film and to which a wafer ring for blade dicing is bonded, and a bonding layer formed on the adhesive layer and having a central portion to which a semiconductor wafer to be diced is bonded, wherein a planar shape of the bonding layer is circular, an area of the bonding layer is greater than an area of the semiconductor wafer and smaller than an area of each of the base film and the adhesive layer, and a diameter of the bonding layer is greater than a diameter of the semiconductor wafer and less than an inner diameter of the wafer ring, and a difference in diameter between the bonding layer and the semiconductor wafer is greater than 20 mm and less than 35 mm.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: March 10, 2015
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Rie Katou, Takayuki Matsuzaki, Shinya Katou, Ryoji Furutani, Tatsuya Sakuta, Kouji Komorida
  • Publication number: 20150061079
    Abstract: Disclosed herein is a method for dicing a wafer, the method comprising forming a molding compound layer over each of one or more dies disposed on a wafer, the one or more dies separated by scribe lines, the molding compound layer having gaps over the respective scribe lines. The wafer is separated into individual dies along the gaps of the molding compound in the scribe lines. Separating the wafer into individual dies comprises cutting at least a portion of the substrate with a laser. Forming the molding compound layer comprises applying a stencil over the one or more dies and using the stencil to form the molding compound layer.
    Type: Application
    Filed: August 27, 2013
    Publication date: March 5, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Ju Chen, Hsia-Wei Chen
  • Publication number: 20150064877
    Abstract: A method for processing a semiconductor wafer in accordance with various embodiments may include: providing a semiconductor wafer including at least one chip and at least one kerf region adjacent to the at least one chip, the kerf region including at least one auxiliary structure; applying a mask layer to the semiconductor wafer; removing the at least one auxiliary structure in the at least one kerf region; removing the applied mask layer; and separating the semiconductor wafer along the at least one kerf region.
    Type: Application
    Filed: August 30, 2013
    Publication date: March 5, 2015
    Applicant: Infineon Technologies AG
    Inventors: Petra Fischer, Michael Roesner, Gudrun Stranzl
  • Publication number: 20150064878
    Abstract: In embodiments, a hybrid wafer or substrate dicing process involving an initial laser scribe and subsequent plasma etch is implemented for die singulation while also removing an oxidation layer from metal bumps on the wafer. In one embodiment, a method includes forming a mask over the semiconductor wafer covering the plurality of ICs, the plurality of ICs including metal bumps or pads with an oxidation layer. The method includes patterning the mask with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the ICs. The method includes plasma etching the semiconductor wafer through the gaps in the patterned mask to singulate the plurality of ICs and remove the oxidation layer from the metal bumps or pads.
    Type: Application
    Filed: November 26, 2013
    Publication date: March 5, 2015
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Wei-Sheng LEI, Brad EATON, Aparna IYER, Madhava Rao YALAMANCHILI, Ajay KUMAR, Jungrae PARK
  • Patent number: 8969177
    Abstract: Laser and plasma etch wafer dicing using UV-curable adhesive films. A mask is formed covering ICs formed on the wafer, as well as any bumps providing an interface to the ICs. The semiconductor wafer is coupled to a carrier substrate by a double-sided UV-curable adhesive film. The mask is patterned by laser scribing to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer, below thin film layers from which the ICs are formed. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the ICs. The UV-curable adhesive film is partially cured by UV irradiation through the carrier. The singulated ICs are then detached from the partially cured adhesive film still attached to the carrier substrate, for example individually by a pick and place machine. The UV-curable adhesive film may then be further cured for the film's complete removal from the carrier substrate.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: March 3, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Mohammad Kamruzzaman Chowdhury, Wei-Sheng Lei, Todd Egan, Brad Eaton, Madhava Rao Yalamanchili, Ajay Kumar
  • Patent number: 8970025
    Abstract: Provided is a method of forming a package-on-package. An encapsulation is formed to cover a wafer using a wafer level molding process. The wafer includes a plurality of semiconductor chips and a plurality of through silicon vias (TSVs) passing through the semiconductor chips. The encapsulant may have openings aligned with the TSVs. The encapsulant and the semiconductor chips are divided to form a plurality of semiconductor packages. Another semiconductor package is stacked on one selected from the semiconductor packages. The other semiconductor package is electrically connected to the TSVs.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Hun Kim, Jin-Woo Park, Dae-Young Choi, Mi-Yeon Kim, Sun-Hye Lee
  • Patent number: 8962452
    Abstract: In one embodiment, a method of singulating semiconductor die from a semiconductor wafer includes forming a material on a surface of a semiconductor wafer and reducing a thickness of portions of the material. Preferably, the thickness of the material is reduced near where singulation openings are to be formed in the semiconductor wafer.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: February 24, 2015
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Gordon M. Grivna
  • Patent number: 8962451
    Abstract: In a wafer processing method, grooves are formed on the front side of a wafer along all division lines extending in a first direction and along all division lines extending in a second direction perpendicular to the first direction. Each groove has a depth corresponding to a finished thickness of each device in the wafer. The wafer is cut into four sectorial wafer quarters. A protective member is provided on the front side of each wafer quarter; and the back side of the wafer quarter is ground to reduce the thickness of the wafer quarter to the finished thickness until the grooves are exposed to the back side of the wafer quarter, thereby dividing the wafer quarter into the individual devices.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: February 24, 2015
    Assignee: Disco Corporation
    Inventor: Kazuma Sekiya
  • Patent number: 8956955
    Abstract: A method to prevent contamination of the principal surface side in a process of grinding the back surface side of a semiconductor wafer. At an intersection of a scribe region of a semiconductor wafer whose back surface side is to be ground, a plurality of insulating layers is laminated over the principal surface in the same manner as an insulating layer constituting a wiring layer laminated over a device region. Moreover, in the same layer as an uppermost wiring disposed at the uppermost layer among a plurality of the wiring layers formed for a device region, a metal pattern is formed. Furthermore, a second insulating layer covering the uppermost wiring is also formed over the metal pattern so as to cover the same.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: February 17, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Shoetsu Kogawa, Satoru Nakayama, Seigo Kamata, Shigemitsu Seito
  • Patent number: 8956957
    Abstract: In a wafer processing method, a wafer is cut along a division line extending in a first direction through the center of the wafer and along a division line extending in a second direction through the center of the wafer, thereby generating four sectorial wafer quarters. Grooves are formed on the front side of each wafer quarter along other division lines extending in a grid, each groove having a depth corresponding to a finished thickness of each device formed on the wafer quarter. A protective member is provided on the front side of each wafer quarter; and the wafer quarter is held through the protective member on a chuck table. The back side is then ground to reduce the thickness of the wafer quarter until the grooves are exposed to the back side of the wafer quarter, thereby dividing the wafer quarter into the individual devices.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: February 17, 2015
    Assignee: Disco Corporation
    Inventor: Kazuma Sekiya
  • Patent number: 8955212
    Abstract: A micro-electro-mechanical microphone and manufacturing method thereof are provided. The micro-electro-mechanical microphone includes a diaphragm, which is formed on a surface of one side of a semiconductor substrate, exposed to the outside surroundings, and can vibrate freely under the pressure generated by sound waves; an electrode plate with air holes, which is under the diaphragm; an isolation structure for fixing the diaphragm and the electrode plate; an air gap cavity between the diaphragm and the electrode plate, and a back cavity under the electrode plate and in the semiconductor substrate; and a second cavity formed on the surface of the same side of the semiconductor substrate and in an open manner The air gap cavity is connected with the back cavity through the air holes of the electrode plate The back cavity is connected with the second cavity through an air groove formed in the semiconductor substrate.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: February 17, 2015
    Assignee: Lexvu Opto Microelectronics Technology (Shanghai) Ltd
    Inventors: Jianhong Mao, Deming Tang
  • Patent number: 8956956
    Abstract: A wafer processing method includes: a protective member providing step of providing a protective member on the front side of a wafer; a wafer quarter generating step of cutting the wafer along the division line extending in a first direction through the center of the wafer and along the division line extending in a second direction perpendicular to the first direction through the center of the wafer, thereby generating four sectorial wafer quarters; a back grinding step of grinding the back side of each wafer quarter to reduce the thickness of the wafer quarter; a frame providing step of supporting the wafer quarter through an adhesive tape to an annular frame; and a wafer quarter dividing step of fully cutting the wafer quarter along all of the division lines extending in the first and second directions, thereby dividing the wafer quarter into the individual devices.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: February 17, 2015
    Assignee: Disco Corporation
    Inventor: Kazuma Sekiya
  • Patent number: 8956947
    Abstract: A semiconductor substrate is provided in which an alignment mark is formed that can be used for an alignment even after the formation of an impurity diffused layer by the planarization of an epitaxial film. A trench is formed in an alignment region of an N?-type layer formed on an N+-type substrate. This trench is used to leave voids after the formation of a P?-type epitaxial film on the N?-type layer. Then, the voids formed in the N?-type layer can be used as an alignment mark. Thus, such a semiconductor substrate can be used to provide an alignment in the subsequent step of manufacturing the semiconductor apparatus. Thus, the respective components constituting the semiconductor apparatus can be formed at desired positions accurately.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: February 17, 2015
    Assignees: Sumco Corporation, Denso Corporation
    Inventors: Syouji Nogami, Tomonori Yamaoka, Shoichi Yamauchi, Nobuhiro Tsuji, Toshiyuki Morishita
  • Publication number: 20150044810
    Abstract: A die includes a first plurality of edges, and a semiconductor substrate in the die. The semiconductor substrate includes a first portion including a second plurality of edges misaligned with respective ones of the first plurality of edges. The semiconductor substrate further includes a second portion extending from one of the second plurality of edges to one of the first plurality of edges of the die. The second portion includes a first end connected to the one of the second plurality of edges, and a second end having an edge aligned to the one of the first plurality of edges of the die.
    Type: Application
    Filed: October 28, 2014
    Publication date: February 12, 2015
    Inventors: I-I Cheng, Chih-Mu Huang, Pin Chia Su, Chi-Cherng Jeng, Volume Chien, Chih-Kang Chao
  • Publication number: 20150044856
    Abstract: A method for separating semiconductor die includes forming a porous region on a semiconductor wafer and separating the die at the porous region using mechanical or other means.
    Type: Application
    Filed: October 28, 2014
    Publication date: February 12, 2015
    Inventors: Manfred Engelhardt, Petra Fischer