Abstract: A phase change memory device comprises a photolithographically formed phase change memory cell having first and second electrodes and a phase change element positioned between and electrically coupling the opposed contact elements of the electrodes to one another. The phase change element has a width, a length and a thickness. The length, the thickness and the width are less than a minimum photolithographic feature size of the process used to form the phase change memory cell. The size of the photoresist masks used in forming the memory cell may be reduced so that the length and the width of the phase change element are each less than the minimum photolithographic feature size.

Abstract: A method for reducing leakage current of a semiconductor device includes supplying a substantially constant and non-zero bulk bias to a relatively low threshold voltage semiconductor device during formation of a conductive channel of the semiconductor device and during the formation of a non-conductive channel of the semiconductor device.

Abstract: A precision resistor is formed with a controllable resistance to compensate for variations that occur with temperature. An embodiment includes forming a resistive semiconductive element having a width and a length on a substrate, patterning an electrically conductive line across the width of the resistive semiconductive element, but electrically isolated therefrom, and forming a depletion channel in the resistive semiconductive element under the electrically conductive line to control the resistance value of the resistive semiconductive element. The design enables dynamic adjustment of the resistance, thereby improving the reliability of the resistor or allowing for resistance modification during final packaging.

Abstract: An RF switch to controllably withstand an applied RF voltage Vsw, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of Vsw appearing across it may be controlled to approximately zero.

Abstract: A rectifying antenna device is disclosed. The device comprises a pair of electrode structures, and at least one nanostructure diode contacting at least a first electrode structure of the pair and being at least in proximity to a second electrode structure of the pair. At least one electrode structure of the pair receives AC radiation, and the nanostructure diode(s) at least partially rectifies a current generated by the AC radiation.

Abstract: A method of implementing bandgap tuning of a graphene-based switching device includes subjecting a bi-layer graphene to an electric field while simultaneously subjecting the bi-layer graphene to an applied strain that reduces an interlayer spacing between the bi-layer graphene, thereby creating a bandgap in the bi-layer graphene.

Abstract: The present invention provides nanostructured MOS capacitor that comprises a nanowire (2) at least partly enclosed by a dielectric layer (5) and a gate electrode (4) that encloses at least a portion of the dielectric layer (5). Preferably the nanowire (2) protrudes from a substrate (12). The gate electrode (4) defines a gated portion (7) of the nanowire (2), which is allowed to be fully depleted when a first predetermined voltage is applied to the gate electrode (4). A method for providing a variable capacitance in an electronic circuit by using such an nanostructured MOS capacitor is also provided. Thanks to the invention it is possible to provide a MOS capacitor having an increased capacitance modulation range. It is a further advantage of the invention to provide a MOS capacitor which has relatively low depletion capacitance compared to prior art MOS capacitances.

Abstract: Fabricating single-walled carbon nanotube transistor devices includes removing undesirable types of nanotubes. These undesirable types of nanotubes may include nonsemiconducting nanotubes, multiwalled nanotubes, and others. The undesirable nanotubes may be removed electrically using voltage or current, or a combination of these. This approach to removing undesirable nanotubes is sometimes referred to as “burn-off.” The undesirable nanotubes may be removed chemically or using radiation. The undesirable nanotubes of an integrated circuit may be removed in sections or one transistor (or a group of transistors) at a time in order to reduce the electrical current used or prevent damage to the integrated circuit during burn-off.

Abstract: A method of reversing Shockley stacking fault expansion includes providing a bipolar or a unipolar SiC device exhibiting forward voltage drift caused by Shockley stacking fault nucleation and expansion. The SiC device is heated to a temperature above 150° C. A current is passed via forward bias operation through the SiC device sufficient to induce at least a partial recovery of the forward bias drift.

Abstract: The HVIC includes a dielectric layer and an SOI active layer stacked on a silicon substrate, a transistor formed in the surface of the SOI active layer, and a trench isolation region formed around the transistor. The dielectric layer includes a first buried oxide film formed in the surface of the silicon substrate, a shield layer formed below the first buried oxide film opposite the element area, a second buried oxide film formed around the shield layer, and a third buried oxide film formed below the shield layer and the second buried oxide film. Therefore, the potential distribution curves PC within the dielectric layer are low in density and a high withstand voltage is achieved.

Abstract: Efficient power management method in integrated circuit through a nanotube structure is disclosed. In one embodiment, a method includes patterning a nanotube structure adjacent to a transistor layer of an integrated circuit. The transistor layer may be above a semiconductor substrate. The transistor layer above the semiconductor substrate may comprise a plurality of transistors. The method also includes supplying power to the plurality of transistors through one or more power sources. In addition, the method includes coupling the plurality of transistors in the transistor layer to the one or more power sources based on a state of the nanotube structure.

Abstract: A memristor includes a first electrode having a first surface, at least one electrically conductive nanostructure provided on the first surface, in which the at least one electrically conductive nanostructure is relatively smaller than a width of the first electrode, a switching material positioned upon said first surface, in which the switching material covers the at least one electrically conductive nanostructure, and a second electrode positioned upon the switching material substantially in line with the at least one electrically conductive nanostructure, in which an active region in the switching material is formed substantially between the at least one electrically conductive nanostructure and the first electrode.

Abstract: A memory device has a first electrode, a second electrode, and memory material defining an inter-electrode current path between the first electrode and the second electrode. A gap is formed by shrinkage of the shrinkable material between the memory material and a shrinkable material next to the memory material.

Abstract: A semiconductor structure, particularly a pFET, which includes a dielectric material that has a dielectric constant of greater than that of SiO2 and a Ge or Si content of greater than 50% and at least one other means for threshold/flatband voltage tuning by material stack engineering is provided. The other means contemplated in the present invention include, for example, utilizing an insulating interlayer atop the dielectric for charge fixing and/or by forming an engineered channel region. The present invention also relates to a method of fabricating such a CMOS structure.

Abstract: This invention relates to methods and devices for the production of optical microstructures or domains in dielectric substrates based on electrothermal focussing. More specifically, the invention relates to a method of introducing a change of dielectric and/or optical properties in a region of an electrically insulating or electrically semiconducting substrate, and to substrates produced by such method.

Abstract: A method of making a quantum dot memory cell, the quantum dot memory cell including an array of quantum dots disposed between a first electrode and a second electrode, includes obtaining values for a tunneling current through the quantum dot memory cell as a function of a voltage applied to the quantum dot memory cell and selecting parameters of the quantum dot memory cell such that the tunneling current through the quantum dot memory cell exhibits a bistable current for at least some values of the voltage applied to the quantum dot memory cell. The values for the tunneling current are determined on the basis of a density of states of the array of quantum dots.

Abstract: An apparatus includes a primary planar quantum well and a planar distribution of dopant atoms. The primary planar quantum well is formed by a lower barrier layer, a central well layer on the lower barrier layer, and an upper barrier layer on the central well layer. Each of the layers is a semiconductor layer. One of the barrier layers has a secondary planar quantum well and is located between the planar distribution of dopant atoms and the central well layer. The primary planar quantum well may be undoped or substantially undoped, e.g., intrinsic semiconductor.

Abstract: Nanostructures, methods of preparing nanostructures, methods of detecting targets in subjects, and methods of treating diseases in subjects, are disclosed. An embodiment, among others, of the nanostructure includes a quantum dot and a hydrophobic protection structure. The hydrophobic protection structure includes a capping ligand and an amphiphilic copolymer, where the hydrophobic protection structure encapsulates the quantum dot.

Abstract: Tunable diodes and methods of making.

Abstract: A micromachine device processing method for dividing a functional wafer, which has micromachine devices formed in a plurality of regions demarcated by streets formed in a lattice pattern on a face of the functional wafer, along the streets into the individual micromachine devices, each micromachine device having a moving portion and an electrode, comprising: a cap wafer groove forming step of forming dividing grooves, which have a depth corresponding to a finished thickness of a cap wafer for protecting the face of the functional wafer, along regions in one surface of the cap wafer which correspond to areas of the electrodes of the micromachine devices; a cap wafer joining step of joining the one surface of the cap wafer subjected to the cap wafer groove forming step to the face of the functional wafer at peripheries of the moving portions; a cap wafer grinding step of grinding the other surface of the cap wafer joined to the face of the functional wafer to expose the dividing grooves to the outside; and a cu

Abstract: A semiconductor device includes an interlayer insulating film formed above a semiconductor substrate. The interlayer insulating film has a concave portion. A barrier metal layer is formed along a bottom and a sidewall of the concave portion. The barrier metal layer has a first portion provided along the sidewall of the concave portion and a second portion provided along the bottom of the concave portion. A metal wiring layer is formed in the concave portion via the barrier metal layer. The first portion of the barrier metal layer is composed of a titanium nitride layer whose titanium content is more than 50 at %, and the second portion of the barrier metal layer is composed of a titanium nitride layer whose titanium content is relatively larger than the titanium content of the first portion or of a Ti layer.

Abstract: Certain embodiments of the present invention are directed to a method of programming nanowire-to-conductive element electrical connections. The method comprises: providing a substrate including a number of conductive elements overlaid with a first layer of nanowires, at least some of the conductive elements electrically coupled to more than one of the nanowires through individual switching junctions, each of the switching junctions configured in either a low-conductance state or a high-conductance state; and switching a portion of the switching junctions from the low-conductance state to the high-conductance state or the high-conductance state to the low-conductance state so that individual nanowires of the first layer of nanowires are electrically coupled to different conductive elements of the number of conductive elements using a different one of the switching junctions configured in the high-conductance state.

Abstract: In a current rectifying element (10), a barrier height ?A of a center region (14) of a barrier layer (11) in a thickness direction thereof sandwiched between a first electrode layer (12) and a second electrode layer (13) is formed to be larger than a barrier height ?B of a region in the vicinity of an interface (17) between the barrier layer (11) and the first electrode layer (12) and an interface (17) between the barrier layer (11) and the second electrode layer (13). The barrier layer (11) has, for example, a triple-layer structure of barrier layers (11a), (11b) and (11c). The barrier layers (11a), (11b) and (11c) are, for example, formed by SiN layers of SiNx2, SiNx1, and SiNx1 (X1<X2). Therefore, the barrier layer (11) has a barrier height in which the shape changes in a stepwise manner and the height of the center region 14 is large.

Abstract: Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, a coupling layer such as an amino functional silane group is provided on a gate oxide layer on a substrate. The substrate is dip coated in a colloidal solution having metal nanodots, causing the nanodots to attach to sites in the coupling layer. The coupling layer is then dissolved such as by rinsing or nitrogen blow drying, leaving the nanodots on the gate oxide layer. The nanodots react with the coupling layer and become negatively charged and arranged in a uniform monolayer, repelling a deposition of an additional monolayer of nanodots. In a configuration using a control gate over a high-k dielectric floating gate which includes the nanodots, the control gates may be separated by etching while the floating gate dielectric extends uninterrupted since the nanodots are electrically isolated from one another.

Abstract: A semiconductor layer containing defects only in a small density, possessing good quality and exhibiting a large ionic bonding property as to GaN, for example, is formed on a semiconductor layer, such as a silicon carbide layer, which is made of a material possessing a small ionicity and exhibiting a strong covalent bonding property. A method for forming a semiconductor layer includes forming on the surface of a first semiconductor layer 102 possessing a first ionicity a second semiconductor layer 103 possessing a second ionicity larger than the first ionicity. The second semiconductor layer 103 is formed while irradiating the surface of the first semiconductor layer existing on the side for forming the second semiconductor layer with electrons in a vacuum.

Abstract: A semiconductor substrate shaped to have a curved surface profile by anodization. Prior to being anodized, the substrate is finished with an anode pattern on its bottom surface so as to be consolidated into a unitary structure in which the anode pattern is precisely reproduced on the substrate. The anodization utilizes an electrolytic solution which etches out an oxidized portion as soon as it is formed as a result of the anodization, to thereby develop a porous layer in a pattern in match with the anode pattern. The anode pattern brings about an in-plane distribution of varying electric field intensity by which the porous layer develops into a shape complementary to a desired surface profile. Upon completion of the anodization, the curves surface is revealed on the surface of the substrate by etching out the porous layer and the anode pattern from the substrate.

Abstract: A method of forming a microball grid array includes adhering a microball precursor material to a transfer medium under conditions to reflect a selective charge pattern. The method includes transferring the microball precursor material from the transfer medium across a gap and to an integrated circuit substrate under conditions to reflect the selective charge pattern. The method includes achieving the microball grid array without the aid of a mask.

Abstract: An electronic component (100), a first electrode (101), a second electrode (102), and a convertible structure (103) electrically coupled between the first electrode (101) and the second electrode (102), being convertible between at least two states by heating and having different electrical properties in different ones of the at least two states, wherein the convertible structure (103) comprises terminal portions (104, 105) connected to the first electrode (101) and to the second electrode (102), respectively, and comprises a line portion (106) between the terminal portions (104, 105), the line portion (106) having a smaller width or thickness than the terminal portions (104, 105), and wherein the convertible structure (103) is arranged with respect to the first electrode (101) and the second electrode (102) so that, in one of the at least two states, the line portion (106) has an amorphous ‘Spot (107) extending along only a part of the line portion (106).

Abstract: An embodiment of a Geiger-mode avalanche photodiode includes a body of semiconductor material having a first conductivity type, a first surface and a second surface; a trench extending through the body from the first surface and surrounding an active region; a lateral-isolation region within the trench, formed by a conductive region and an insulating region of dielectric material, the insulating region surrounding the conductive region; an anode region having a second conductivity type, extending within the active region and facing the first surface. The active region forms a cathode region extending between the anode region and the second surface, and defines a quenching resistor. The photodiode has a contact region of conductive material, overlying the first surface and in contact with the conductive region for connection thereof to a circuit biasing the conductive region, thereby a depletion region is formed in the active region around the insulating region.

Abstract: During fabrication of single-walled carbon nanotube transistor devices, a porous template with numerous parallel pores is used to hold the single-walled carbon nanotubes. The porous template or porous structure may be anodized aluminum oxide or another material. A gate region may be provided one end or both ends of the porous structure. The gate electrode may be formed and extend into the porous structure.

Abstract: One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect transistor (FET), thereby providing control and variation of threshold voltages of the transistor. Various threshold voltages may be assigned a data value, providing the ability to store one or more bits of data in a single memory cell. To control the threshold voltage, the oxygen vacancies may be manipulated by trapping electrons within the vacancies, freeing trapped electrons from the vacancies, moving the vacancies within the trapping layer and annihilating the vacancies.

Abstract: A wafer is mounted on the top surface of the stage having an electrostatic chuck function, and the wafer at 50° C. or more is cooled to a temperature lower than 50° C. In this step, the voltage to be applied to the internal electrode provided in the stage is raised stepwise to gradually increase the contact area between the back surface of the wafer and the top surface of the stage. Finally, a chuck voltage is applied to the internal electrode, so that the entire back surface of the wafer is uniformly attracted to the top surface of the stage. This reduces damage occurring in the top surface of the stage due to rubbing between the back surface of the wafer and the top surface of the stage.

Abstract: A memory device has a first electrode, a second electrode, and memory material defining an inter-electrode current path between the first electrode and the second electrode. A gap is formed by shrinkage of the shrinkable material between the memory material and a shrinkable material next to the memory material.

Abstract: According to one embodiment, at least a portion of the phase change material including a first crystalline phase is converted to one of a second crystalline phase and an amorphous phase. The second crystalline phase transitions to the amorphous phase more easily than the first crystalline phase. For example, the first crystalline phase may be a hexagonal closed packed structure, and the first crystalline phase may be a face centered cubic structure.

Abstract: Provided is a method for performing etching process or film forming process to a substrate W whereupon a prescribed pattern is formed with an opening. The method is provided with a step of mixing a liquid and a gas, at least one of which contains a component that contributes to the etching process or the film forming process, and generating charged nano-bubbles 85 having a diameter smaller than that of the opening formed on the semiconductor substrate W; a step of forming an electric field to attract the nano-bubbles onto the surface of the substrate W; and a step of performing the process by supplying the substrate with the liquid containing the nano-bubbles 85 while forming the electric field.

Abstract: A semiconductor laser device manufacturing method includes, sequentially, a first aging step S1, a first inspection step S2, a mounting step S3, a second aging step S4 and a second inspection step S5. Since the first aging step S1 on a semiconductor laser chip with a high-temperature direct current conduction is performed before the mounting step S3, threshold current and drive current of the semiconductor laser chip before mounting can be reduced.

Abstract: A negative dielectric is induced by the application of a dc bias-electric field in aggregates of oxide nano-particles whose surfaces have been specially treated. The magnitude of the dielectric constant and the frequency where the negative dielectric constant occurs can be adjusted. Such material systems have profound implications in novel devices as well as in science development, e.g. unusual wave propagation, secured communication and ultra-high temperature superconductivity.

Abstract: Examples of the present invention include methods of assembling structures, such as nanostructures, at predetermined locations on a substrate. A voltage between spaced-apart electrodes supported by substrate attracts the structures to the substrate, and positional registration can be provided the substrate using topographic features such as wells. Examples of the present invention also include devices, such as electronic and optoelectronic devices, prepared by such methods.

Abstract: A method for manufacturing an organic semiconductor device having enhanced uniformity of light-emission and excellent luminance with relatively low driving voltage by a wet process is disclosed. The method for manufacturing an organic semiconductor device, comprises the steps of: forming a first electrode on a substrate; forming an organic semiconductor layer including an ionic salt by coating an organic compound solution on the first electrode and removing an organic solvent from the coated organic compound solution, wherein the organic compound solution includes the organic solvent, the ionic salt and organic semiconductor compounds; forming a second electrode having the opposite electric potential to the first electrode on the organic semiconductor layer including the ionic salt; and treating the organic semiconductor layer including the ionic salt with thermal annealing and electrical annealing simultaneously.

Abstract: Targeted heating is employed to essentially only heat a material that is used as a spacer and to bond a first chip of a flip-chip to a second chip thereof and not the rest of the chips. In order to heat only the spacer-bonding material, one or more wires are located within, or adjacent to, the spacer-bonding material, and an electrical current is passed through the one or more wires causing them to heat. At the time of final bonding the heat generated by the one or more wires causes the spacer-bonding material to heat to its final curing temperature.

Abstract: A semiconductor device manufacturing apparatus which uses a thermal CVD reaction to deposit a film onto a substrate has a ring with an electrode terminal that makes contact with either the substrate or the deposited film thereon, a power supply that applies a current or a potential to this electrode terminal of the ring, and a piston cylinder mechanism for moving the ring up and down, so as to cause its electrode terminal to make and break contact with the substrate or deposited film thereon.

Abstract: A semiconductor substrate is shaped to have a curved surface profile by anodization. Prior to being anodized, the substrate is finished with an anode pattern on its bottom surface so as to be consolidated into a unitary structure in which the anode pattern is precisely reproduced on the substrate. The anodization utilizes an electrolytic solution which etches out oxidized portion as soon as it is formed as a result of the anodization, to thereby develop a porous layer in a pattern in match with the anode pattern. The anode pattern brings about an in-plane distribution of varying electric field intensity by which the porous layer develops into a shape complementary to a desired surface profile. Upon completion of the anodization, the curves surface is revealed on the surface of the substrate by etching out the porous layer and the anode pattern from the substrate.

Abstract: A semiconductor having a an n-type material and a p-type material, wherein the n-type material and p-type material are joined to form a space-charge-free p-n junction. The energy of the Fermi-level of the n-type material is equal to the energy of the Fermi-level of the p-type material. This allows for the pre-alignment of the Fermi-levels of the n-type and the p-type materials. The semiconductor has minimal or no g-r noise. The semiconductor can be operated at TBLIP in the range of about 220° to about 240° K.

Abstract: Embodiments of the present invention provide mesoscale or microscale three-dimensional structures (e.g. components, device, and the like). Embodiments relate to one or more of (1) the formation of such structures which incorporate sheets of dielectric material and/or wherein seed layer material used to allow electrodeposition over dielectric material is removed via planarization operations; (2) the formation of such structures wherein masks used for at least some selective patterning operations are obtained through transfer plating of masking material to a surface of a substrate or previously formed layer, and/or (3) the formation of such structures wherein masks used for forming at least portions of some layers are patterned on the build surface directly from data representing the mask configuration, e.g. in some embodiments mask patterning is achieved by selectively dispensing material via a computer controlled inkjet nozzle or array or via a computer controlled extrusion device.

Abstract: The present invention provides a method for preparation of crystallization of amorphous silicon thin film, which comprises providing a forming a amorphous silicon on a dielectric film formed on a transparent substrate; then forming a conductive layer on the top surface of substrate; applying an electric field to the conductive layer so as to generate heat; and crystallization of amorphous silicon thin film by the generated heat.

Abstract: A microelectromechanical system (MEMS) device with a mechanism layer and a base. The top surface of the base is bonded to the mechanism layer and defines a gap in the top surface of the base. A portion of the mechanism layer is deflected into the gap until it contacts the base, and is bonded to the base.

Abstract: A method of making a nonvolatile memory device includes forming a first electrode, forming at least one nonvolatile memory cell comprising a silicon, germanium or silicon-germanium diode, doping the diode with at least one of nitrogen or carbon, and forming a second electrode over the at least one nonvolatile memory cell.

Abstract: In one disclosed embodiment, the present method for depositing a conductive capping layer on metal lines comprises forming metal lines on a dielectric layer, applying a voltage to the metal lines, and depositing the conductive capping layer on the metal lines. The applied voltage increases the selectivity of the deposition process used, thereby preventing the conductive capping layer from causing a short between the metal lines. The conductive capping layer may be deposited through electroplating, electrolessly, by atomic layer deposition (ALD), or by chemical vapor deposition (CVD), for example. In one embodiment, the present method is utilized to fabricate a semiconductor wafer. In one embodiment, the metal lines comprise copper lines, while the conductive capping layer may comprise tantalum or cobalt. The present method enables deposition of a capping layer having high electromigration resistance.

Abstract: A hybrid method of fabricating magnetic core elements of an on-chip inductor structure addresses issues associated with conventional bottom up and damascene magnetic core plating techniques. The process uses two seed layers: a low resistance seed layer that solves the IR drop problem associated with the damascene plating techniques and a high resistance seed layer that is local to magnetic core features thus avoiding eddy current related performance degradation associated with the bottom up techniques.

Abstract: A nanoscale device and a method for creating and erasing of nanoscale conducting regions at the interface between two insulating oxides SrTiO3 and LaAlO3 is provided. The method uses the tip of a conducting atomic force microscope to locally and reversibly switch between conducting and insulating states. This allows ultra-high density patterning of quasi zero or one dimensional electron gas conductive regions, such as nanowires and conducting quantum dots respectively. The patterned structures are stable at room temperature after removal of the external electric field.