Abstract: A process for forming low k silicon oxide dielectric material having a dielectric constant no greater than 3.0, while suppressing pressure spikes during the formation of the low k silicon oxide dielectric material comprises reacting an organo-silane and hydrogen peroxide in a reactor chamber containing a silicon substrate while maintaining an electrical bias on the substrate. In a preferred embodiment the reactants are flowed into the reactor at a reactant flow ratio of organo-silane reactant to hydrogen peroxide reactant of not more than 10.6 sccm of organo-silane reactant per 0.1 grams/minute of hydrogen peroxide reactant; and the substrate is biased with either a positive DC bias potential, with respect to the grounded reactor chamber walls, of about +50 to +300 volts, or a low frequency AC bias potential ranging from a minimum of +50/-50 volts up to a maximum of about +300/-300 volts.

Abstract: The invention encompasses methods of forming individual silicon-on-insulator layers having varying thicknesses within the individual layers. The invention also encompasses methods of forming transistor devices from silicon-on-insulator layers. Additionally, the invention encompasses semiconductor devices and assemblies utilizing silicon-on-insulator layers. The invention includes a method comprising: a) providing a substrate; b) providing an insulator layer over the substrate; c) providing a semiconductive layer over the insulator layer, the semiconductive layer having a first portion and a second portion; d) forming a depletion region within the semiconductive layer and proximate the insulator layer, the depletion region having a different thickness in the first portion than in the second portion; and f) etching the semiconductive layer to about the depletion region.

Abstract: An electrostatic protected integrated circuit (IC) substrate and a method of making an integrated circuit package with the electrostatic protected IC substrate includes an IC substrate, having a plurality of electrical traces formed on the top of the IC substrate with the electrical traces extending from an IC chip mounting area near the center to the periphery of the IC substrate. Electrically shorting the electrical traces together with a conductive material such as conductive tape or epoxy, thereby, protecting the IC substrate against the accumulation of static charges during the assembly of the IC chip on the IC substrate. The IC chip is mounted in the mounting area on the IC substrate and the conductive material is removed before final testing.

Abstract: A semi conductor manufacturing process including uniform negative polarity wafer charging to remove or immobilize alkali ions such that the device becomes immune to their presence. The wafer is charged with a corona discharge at a 1MV/cm-2MV/cm bias field and low temperature (200.degree. C.-300.degree. C.) heating to bring mobile ions to the wafer's surface. Surface mobile ions are removed with a deionized (DI) water rinse or a standard sequential wafer wet cleaning step, immobilized with a normal gate (polysilicon) or metal contact formation step or both, thereby effectively removing mobile ions from the semiconductor structure.

Abstract: A method for fabricating a semiconductor substrate comprises the steps of employing a diffusion method to diffuse, in a silicon substrate, an element, which is capable of controlling a conductive type, and to form a diffused region, forming a porous layer in the diffused region, forming a non-porous single crystal layer on the porous layer, bonding the non-porous single crystal layer to a base substrate, while an insulation layer is provided either on a surface to be bonded of the non-porous single crystal layer or on a surface to be bonded of the base substrate, and removing the porous layer.

Abstract: The invention encompasses methods of forming individual silicon-on-insulator layers having varying thicknesses within the individual layers. The invention also encompasses methods of forming transistor devices from silicon-on-insulator layers. Additionally, the invention encompasses semiconductor devices and assemblies utilizing silicon-on-insulator layers. The invention includes a method comprising: a) providing a substrate; b) providing an insulator layer over the substrate; c) providing a semiconductive layer over the insulator layer, the semiconductive layer having a first portion and a second portion; d) forming a depletion region within the semiconductive layer and proximate the insulator layer, the depletion region having a different thickness in the first portion than in the second portion; and f) etching the semiconductive layer to about the depletion region.

Abstract: The rapid thermal oxidation (RTO) and rapid thermal annealing(RTA) were used to improve the photo-current and photoresponsivity of porous silicon photodetector. In addition, we remove the surface oxide of the porous silicon under the metal grid using the same mask, and enhance the photo-current of porous silicon photodetector at zero bias voltage. This invention removes the limitation of application of the porous silicon photodetector.

Abstract: A dielectric capacitor is provided which has a reduced leakage current. The surface of a first electrode (38) of the capacitor is electropolished and a dielectric film (40) and a second electrode (37) are successively laminated on it. The convex parts pointed end (38a) existing on the surface of the first electrode is very finely polished uniformly by dissolving according to electropolishing, a spherical curved surface in which the radius of curvature has been enlarged is formed, and the surface of the first electrode is flattened. Therefore, concentration of electrolysis can be prevented during the operation at the interface of the first electrode and the dielectric film, and the leakage current can be reduced considerably.

Abstract: A P-type silicon substrate (4) and an N-type diffusion layer region (6) are connected to aluminum electrodes (5 and 7), respectively. Respective sections of the P-type silicon substrate (4) and the N-type diffusion layer region (6) are exposed. The aluminum electrode (5) connected to the P-type silicon substrate (4) and a platinum electrode (1) are connected in common to a cathode of a DC power supply (3a) and the aluminum electrode (7) connected to the N-type diffusion layer region (6) is connected to an anode of the DC power supply (3a). A sample for evaluation is thus provided. Of this sample, the exposed sections of the P-type silicon substrate (4) and the N-type diffusion layer region (6) are dipped into a mixture (2) of hydrofluoric acid and alcohol, and a voltage not lower than a critical voltage is applied thereto by the DC power supply (3a). Thus, an evaluation of a form of a diffusion layer region in a semiconductor device is achieved with excellent reproducibility.

Abstract: Charging damage to integrated circuits during ion implantation and plasma processing of integrated circuit die in a semiconductor wafer is reduced by processing scribe lanes during wafer fabrication to facilitate the flow of current to and from the wafer substrate through the scribe lanes during integrated circuit fabrication and reduce current flow through integrated circuit components.

Abstract: A method of bonding two electrically conductive substrates together includes the steps of forming a dielectric layer between the substrates, with the layer being formed from a sol-gel solution. Through the application of a constant voltage an ionic depletion region is created in the dielectric layer. After the step of creating the ionic depletion region, the dielectric layer and substrates are heated such that an oxygen depletion region is created in one of the substrates. The sol-gel solution includes sodium aluminoborosilicate having about 75-90 mol % SiO.sub.2, about 5-20 mol % B.sub.2 O.sub.3, about 1-10 mol % Na.sub.2 O and about 0-5 mol % Al.sub.2 O.sub.3.

Abstract: An improved method of forming insulated gate field effect transistors is described. In accordance with the method, gate electrodes are formed from metal such as aluminum together with wirings electrically connecting the gate electrodes. The gate electrodes are anodic oxidized by dipping them as an anode in an electrolyte to form an oxide of the metal covering them. Since the connecting wirings are covered with a suitable organic film before the anodizing, no aluminum oxide is formed thereon so that it is easy to remove the connecting wiring by usual etching.

Abstract: Copper or a copper alloy is electroplated to fill via/contact holes and/or trenches in a dielectric layer. A barrier layer is initially deposited on the dielectric layer lining the hole/trench. A thin conformal layer of copper or a copper alloy is sputter deposited on the barrier layer outside the hole/trench. Copper or a copper alloy is then electroplated on the conformal copper or copper alloy layer and filling the hole/trench. During electroplating, the barrier layer functions as a seed layer within the hole/trench while the sputter deposited conformal copper or copper alloy layer enhances the flow of electrons from the wafer edge inwardly to provide a favorable deposition rate.

Abstract: The invention encompasses methods of forming individual silicon-on-insulator layers having varying thicknesses within the individual layers. The invention also encompasses methods of forming transistor devices from silicon-on-insulator layers. Additionally, the invention encompasses semiconductor devices and assemblies utilizing silicon-on-insulator layers. The invention includes a method comprising: a) providing a substrate; b) providing an insulator layer over the substrate; c) providing a semiconductive layer over the insulator layer, the semiconductive layer having a first portion and a second portion; d) forming a depletion region within the semiconductive layer and proximate the insulator layer, the depletion region having a different thickness in the first portion than in the second portion; and f) etching the semiconductive layer to about the depletion region.

Abstract: A chalcogenide memory cell with chalcogenide electrodes positioned on both sides of the active chalcogenide region of the memory cell. The chalcogenide memory cell includes upper and lower chalcogenide electrodes with a dielectric layer positioned therebetween. The dielectric layer includes an opening defining a pore. A volume of chalcogenide material formed integral to the upper chalcogenide electrode is contained within the pore. The upper and lower chalcogenide electrodes both have greater cross sectional areas than the pore.

Abstract: A method and device for heating silicon carrier bodies in a deposition reactor are by means of radiated heat. In this method, the carrier bodies are irradiated by means of a heat radiation device which emits radiation having a color temperature of at least 2000.degree. C.

Abstract: A low cost method for forming an integrated resistor capacitor combination using only three masks and three mask exposure steps is described. A layer of resistor material is formed on a substrate and patterned forming a resistor and a first capacitor plate. A photoresist mask is then formed covering the resistor and a contact region of the first capacitor plate. The substrate is then immersed in an anodization solution and that part of the first capacitor plate not covered by the photoresist mask is anodized forming a capacitor dielectric. The photoresist mask is then stripped. A layer of conductor material is then formed and patterned to form contacts to the resistor, a contact to the first capacitor plate, and a second capacitor plate.

Abstract: A method for electroplating a silicon substrate in manufacturing a semiconductive device is provided. Electroplating process chamber contacts or fingers used in positioning a silicon substrate or wafer during an electroplating process are plated with a metal layer to prevent oxidation of the contacts. Oxidation of the contacts may result in increased and varying resistance of the contacts and thus nonuniform plating of the silicon wafer and possibly even deplating of a seed layer. A 20 mA/cm.sup.2 current is applied to the contacts which are immersed in an electrolyte solution before loading a silicon wafer. A silicon wafer is then loaded into the electroplating process chamber containing the electrolyte solution. The preplating of the contacts enables the formation of a uniform metal layer on the silicon substrate. Additionally, voltage then may be applied to the contacts after unloading the silicon wafer to reduce oxidation.

Abstract: Dopant activation in heavily boron doped p.sup.+ --Si is achieved by applying electric current of high density. The p.sup.+ --Si was implanted by a 40 KeV BF.sup.2+ at an ion intensity 5.multidot.10.sup.15 ions per cm.sup.2 and annealed at 900.degree. C. for 30 minutes to obtain a partial boron activation according to conventional processing steps. To obtain additional activation and higher conductivity, current was gradually applied according to the invention to a current density of approximately 5.times.10.sup.6 A/cm.sup.2 was realized. The resistance of the p.sup.+ --Si gradually increases and then decreases with a precipitous drop at a threshold current. The resistance was reduced by factor of 5 to 18 times and was irreversible if an activation current threshold was reached or exceeded. The high-current-density-dopant activation occurs at room temperature.

Abstract: A fabrication method for a chip size semiconductor package includes the steps of bonding conductive wires on bonding pads formed on an upper surface of a semiconductor chip, putting the semiconductor chip including the bonded conductive wires in an electrolyzer containing an electrolytic solution in such a manner that one end of each of the conductive wires is exposed outside of the electrolytic solution, attaching a plating electrode to an inner wall of the electrolyzer, attaching a conductive plate to serve as a common electrode to the exposed one end of each of the conductive wires; and connecting the conductive plate and the outer wall of the electrolyzer to an electric current source.

Abstract: A method for forming field isolation regions in multilayer semiconductor devices comprises the steps of masking active regions of the substrate, forming porous silicon in the exposed field isolation regions, removing the mask and oxidizing the substrate. A light ion impurity implant is used to create pores in the substrate. Substrate oxidation proceeds by rapid thermal annealing because the increased surface area of the pores and the high reactivity of unsaturated bonds on these surfaces provides for enhanced oxidation.

Abstract: The present invention disclose a salicide process with a self-preamorphization step to reduce the sheet resistance of the source/drain region. The salicide process, comprising the steps of performing a pre-amorphization step on the surface of the silicon and simultaneously forming a metal layer, further contains the substeps of applying a back bias to the bottom of the substrate, using ion metal plasma to transform the surface of the substrate into amorphous silicon, forming a metal layer on the surface of the substrate and then using a thermal process having two stages to transform the metal into the salicide.

Abstract: A process for producing a semiconductor substrate is provided which comprises steps of forming a porous layer on a first substrate, forming a nonporous monocrystalline semiconductor layer on the porous layer of the first substrate, bonding the nonporous monocrystalline layer onto a second substrate, separating the bonded substrates at the porous layer, removing the porous layer on the second substrate, and removing the porous layer constituting the first substrate.

Abstract: A method for preparing a semiconductor member comprises process of making a porous Si substrate and then forming a non-porous Si monocrystalline layer on the porous Si substrate; primary bonding process of bonding the porous Si substrate and an insulating substrate via the non-porous Si monocrystalline layer; etching process of etching the porous Si to remove the porous Si by chemical etching after the primary bonding process; and secondary bonding process of strengthening the primary bonding after the etching process.

Abstract: A process for manufacturing a vacuum enclosure for a semiconductor device formed on a substrate with leads extending peripherally. Assembly of the enclosure is compatible with known batch fabrication techniques and is carried out at pressures required for optimal device operation. In a first embodiment, an intrinsic silicon shell is sealed to the substrate via electrostatic or anodic bonding with the leads diffusing into the shell. In a second embodiment, a thin interface layer of silicon or polysilicon is deposited on the substrate prior to electrostatic bonding a glass shell thereon. In a third embodiment, tunnels are formed between a lower peripheral edge of the shell and the substrate, allowing leads to pass thereunder. The tunnels are sealed by a dielectric material applied over the enclosure.

Abstract: A pair of metal lead frames are stacked together with a plurality of solder coated semiconductor chips sandwiched between respective pairs of overlapped portions of the lead frames and the lead frame stack is then disposed within a fixture comprising spaced apart clamping means for clamping together the overlapped portions of the lead frames. Only the clamping means contact the frame stack and in thermally and electrically insulated relation therewith for minimizing heat loss from and electrical shorting of the lead frame stack to the fixture. Electrodes are tightly clamped against exposed ends of the lead stack for passing electrical current through the stack for causing electrical resistance heating of the stack and the soldering of the chips to the lead frames.

Abstract: A semiconductor substrate and a method of fabricating the same, and provides which the active area to be formed the active element is defined by the trench filled with any conductive polycrystal silicon in which any portion of a large number of the epitaxial layer is crystally grown on any conductive silicon substrate, and the multi-aperture silicon oxide layer is formed from the metal line to be used to the passive element or the transmitting line outside the trench, so that the interference between the passive element and the semiconductor substrate is prevented, and to attenuate the transmitting signal prevents to be attenuated in the high frequency band operation. Therefore, the semiconductor substrate for a unit active element and the MMIC to be able to operate the high frequency band is manufactured into the silicon, and thus it is advantageous to reduce the cost and enhance the yield.

Abstract: An anodic oxide containing impurities at a low concentration and thereby improved in film quality, and a process for fabricating the same. The process comprises increasing the current between a metallic thin film and a cathode until a voltage therebetween reaches a predetermined value, and maintaining the voltage at the predetermined value thereafter.

Abstract: A dry etch process for etching a semiconductor substrate having a p-n heterojunction formed by contact between a p-layer and a n-layer requires application of a reverse bias voltage of less than a p-n breakdown voltage across the p-n heterojunction. A plasma containing chemically reactive negative ions is directed against the n-layer, with etching of non-masked regions of the substrate continuing until it is substantially stopped at the reverse biased p-n heterojunction. The semiconductor substrate can be cooled or periodically recoated with erodable protective material to limit sidewall damage to the semiconductor substrate while still allowing downward etching. This dry etch process is well suited for construction of dimensionally accurate microdevices and microelectromechanical systems.

Abstract: A suspended microstructure process assembly includes a first microstructure assembly, with a temporary substrate having a first surface and a first microstructure fabricated on the first surface; a second microstructure assembly, including a final substrate having a second surface and a second microstructure fabricated on the second surface; connecting elements for joining the first microstructure assembly to the second microstructure assembly with a predetermined separation and alignment; and a removable bond temporarily securing the first microstructure assembly to the second microstructure assembly until the temporary substrate is removed. The connecting elements may be electrically conductive contacts or electrically nonconductive spacers. Electrically conductive contacts may be supplied to the first microstructure from a back side of the first microstructure assembly. The first microstructure fabricated on the first surface may incorporate a removable layer to enable multiple level suspended structures.