Abstract: First, a base structure provided with the main parts of a memory cell is prepared, and a lower electrode comprising a polycrystalline silicon film is thereafter formed on the base structure. Next, the surface of the lower electrode is thermally nitrided at a predetermined temperature to form a silicon nitride film. In the thermal nitridation of the lower electrode, the temperature is increased to a predetermined nitriding temperature, after which the temperature is reduced at a rate that is more gradual than usual. Aluminum oxide (Al2O3) or another metal oxide dielectric film is thereafter formed as the capacitive insulating film on the lower electrode, and an upper electrode is formed on the capacitive insulating film.

Abstract: A method is provided capable of universally controlling the proximity gettering structure, the need for which can vary from manufacturer to manufacturer, by arbitrarily controlling an M-shaped distribution in a depth direction of a wafer BMD density after RTA in a nitrogen-containing atmosphere. The heat-treatment method is provided for forming a desired internal defect density distribution by controlling a nitrogen concentration distribution in a depth direction of the silicon wafer for heat-treatment, the method including heat-treating a predetermined silicon wafer used for manufacturing a silicon wafer having a denuded zone in the vicinity of the surface thereof.

Abstract: A method for manufacturing a silicon wafer includes a step of annealing a silicon wafer which is sliced from a silicon single crystal ingot, thereby forming a DZ layer in a first surface and in a second surface of the silicon wafer and a step of removing either a portion of the DZ layer in the first surface or a portion of the DZ layer in the second surface.

Abstract: A method for improving the quality of a SiC layer by effectively reducing or eliminating the carrier trapping centers in the as-grown SiC crystal. The method includes the steps of: (a) carrying out ion implantation of carbon atoms, silicon atoms, hydrogen atoms, or helium atoms into a shallow surface layer of the SiC crystal layer to introduce carbon interstitials into the surface layer, and (b) growing the SiC layer upward from the edge face of the surface layer into which the carbon interstitials have been introduced, and diffusing out the carbon interstitials that have been introduced into the surface layer from the surface layer into the grown layer and combining the carbon interstitials and point defects to make the electrically active point defects in the grown layer inactive.

Abstract: A method for improving the minority lifetime of silicon containing wafer having metallic contaminants therein is described incorporating annealing at 1200° C. or greater and providing a gaseous ambient of oxygen, an inert gas and a chlorine containing gas such as HCl.

Abstract: A method of manufacturing a semiconductor element. A dislocation region is formed between a first layer and a second layer, the dislocation region including a plurality of dislocations. First interstitials in the first layer are at least partially eliminated using the dislocations in the dislocation region. Vacancies are formed in the second layer. Second interstitials in the second layer are at least partially eliminated using the vacancies in the second layer.

Abstract: The present method provides tools for growing conformal metal nitride, metal carbide and metal thin films, and nanolaminate structures incorporating these films, from aggressive chemicals. The amount of corrosive chemical compounds, such as hydrogen halides, is reduced during the deposition of transition metal, transition metal carbide and transition metal nitride thin films on various surfaces, such as metals and oxides. Getter compounds protect surfaces sensitive to hydrogen halides and ammonium halides, such as aluminum, copper, silicon oxide and the layers being deposited, against corrosion. Nanolaminate structures (20) incorporating metal nitrides, such as titanium nitride (30) and tungsten nitride (40), and metal carbides, and methods for forming the same, are also disclosed.

Abstract: Disclosed is an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology.

Abstract: An annealed wafer having enhanced gettering effects for Cu is produced by heating a silicon substrate containing a nitrogen concentration of 5×1014 to 1×1016/cm3, a carbon concentration of 1×1015 to 5×1016/cm3, and an oxygen concentration of 6×1017 to 11×1017/cm3 at a temperature of 650 to 800° C. for a time ?4 hours, and subjecting the heated substrate to argon annealing at a temperature of 1100 to 1250° C., wherein internal stacking fault density after annealing is ?5×108/cm3.

Abstract: A method of processing a semiconductor wafer includes preheating the wafer to a preheating temperature that is less than a peak temperature, heating the wafer from the preheating temperature to the peak temperature at a first ramp rate that averages about 100° C. per second or more, and, immediately after heating the wafer from the preheating temperature to the peak temperature, cooling the wafer at a second ramp rate that averages about ?70° C. per second or more from the peak temperature to the preheating temperature, wherein the peak temperature is about 1,100° C. or more.

Abstract: A method of recycling monitor wafers. The method includes: (a) providing a semiconductor wafer which includes a dopant layer extending from a top surface of the wafer into the wafer a distance less than a thickness of the wafer, the dopant layer containing dopant species; after (a), (b) attaching an adhesive tape to a bottom surface of the wafer; after (b), (c) removing the dopant layer; and after (c), (d) removing the adhesive tape.

Abstract: Sonic radiation is applied to a wafer portion of the planar surface of a rotating, tilted wafer as it is being immersed into a liquid treatment bath. The portion includes the leading outer edge region of the wafer. The area of the wafer portion is significantly less than the total surface area of the planar wafer surface. Power density is minimized. As a result, bubbles are removed from the wafer surface and cavitation in the liquid bath is avoided. In some embodiments, the liquid bath is de-gassed to inhibit bubble formation.

Abstract: A method for forming a shallow junction region in a crystalline semiconductor substrate and method for fabricating a semiconductor device having the shallow junction region includes a defect engineering step in which first ions are introduced into a first region of the substrate and vacancies are generated in the first region. During the generation of substrate vacancies, the first region remains substantially crystalline. Interstitial species are generated in a second region and second ions are introduced into the second region to capture the interstitial species. Laser annealing is used to activate dopant species in the first region and repair implantation damage in the second region. The defect engineering process creates a vacancy-rich surface region in which source and drain extension regions having high dopant activation and low sheet resistance are created in an MOS device.

Abstract: A method of implantation that minimizes surface damage to a workpiece is disclosed. In one embodiment, following a doping implant, a second implant is performed which causes the silicon at the surface of the workpiece to become amorphous. This reduces surface damage and interstitials, which has several benefits. First, inactive dopant clusters may become activated due to the replenishment of silicon. Secondly, the amorphous nature of the silicon makes it bond more easily in subsequent process steps, such as silicidation.

Abstract: A method for producing a silicon wafer for epitaxial substrate which includes a first step of performing thermal oxidization on a silicon wafer containing boron atoms no less than 1E19 atoms/cm3, thereby forming a silicon oxide film on the surface of the silicon wafer, a second step of peeling off the silicon oxide film, and a third step of performing heat treatment on the silicon wafer in a hydrogen atmosphere.

Abstract: The method includes: a first step of colliding ions implanted from a surface of a SIMOX wafer into a silicon layer underneath a BOX layer against crystal defects to destroy the crystal defects; and a second step of heating the wafer obtained in the first step to recrystallize the silicon layer. If the ions to be implanted into the silicon layer are oxygen ions, then the first step initiates ion implantation with the temperature of the SIMOX wafer being 50° C. or lower, and sets an ion dose to 5×1015 atoms/cm2 to 1.5×1016 atoms/cm2 and implantation energy to 150 keV or higher but not higher than 220 keV. Consequently, crystal defects present in the silicon layer underneath the BOX layer of the SIMOX wafer are reduced.

Abstract: Provided is a silicon wafer including: a first denuded zone formed with a predetermined depth from a top surface of the silicon wafer; and a bulk area formed between the first denuded zone and a backside of the silicon wafer, wherein the first denuded zone is formed with a depth ranging from approximately 20 um to approximately 80 um from the top surface, and wherein a concentration of oxygen in the bulk area is uniformly distributed within a variation of 10 % over the bulk area.

Abstract: A method for generating patterned strained regions in a semiconductor device is provided. The method includes directing a light-emitting beam locally onto a surface portion of a semiconductor body; and manipulating a plurality of dislocations located proximate to the surface portion of the semiconductor body utilizing the light-emitting beam, the light-emitting beam being characterized as having a scan speed, so as to produce the patterned strained regions.

Abstract: One aspect of this disclosure relates to a method for creating proximity gettering sites in a silicon on insulator (SOI) wafer. In various embodiments of this method, a relaxed silicon germanium region is formed over an insulator region of the SOI to be proximate to a device region. The relaxed silicon germanium region generates defects to getter impurities from the device region. Other aspects are provided herein.

Abstract: Method of processing a substrate containing at least one semiconductor of the SiXAY type and comprising at least four separate types of light elements, comprising at least the following steps: carrying out a first anneal of the substrate at a temperature T1 corresponding to a thermal activation temperature for a first one of the four types of light elements, carrying out a second anneal of the substrate at a temperature T2 corresponding to a thermal activation temperature for a second one of the four types of light elements, carrying out a third anneal of the substrate at a temperature T3 corresponding to a thermal activation temperature for a third one of the four types of light elements, carrying out a fourth anneal of the substrate at a temperature T4 corresponding to a thermal activation temperature for a fourth one of the four types of light elements, each anneal comprising a holding at the temperature T1, T2, T3 or T4 and the temperatures T1, T2, T3 and T4 being such that T1>T2>T3>T4.

Abstract: Misfit dislocations are redirected from the buffer/Si interface and propagated to the Si substrate due to the formation of bubbles in the substrate. The buffer layer growth process is generally a thermal process that also accomplishes annealing of the Si substrate so that bubbles of the implanted ion species are formed in the Si at an appropriate distance from the buffer/Si interface so that the bubbles will not migrate to the Si surface during annealing, but are close enough to the interface so that a strain field around the bubbles will be sensed by dislocations at the buffer/Si interface and dislocations are attracted by the strain field caused by the bubbles and move into the Si substrate instead of into the buffer epi-layer. Fabrication of improved integrated devices based on GaN and Si, such as continuous wave (CW) lasers and light emitting diodes, at reduced cost is thereby enabled.

Abstract: Silicon wafers wherein slip dislocations and warpages during device production are suppressed, contain BMDs with an octahedral shape, and of BMDs at a depth greater than 50 ?m from the surface of the wafer, the density of BMDs with diagonal size of 10 nm to 50 nm is ?1×1012/cm3, and the density of BSFs is ?1×108/cm3. The present silicon wafers preferably have an interstitial oxygen concentration of 4×1017 atoms/cm3 to 6×1017 atoms/cm3, and a density of BMDs with diagonal size of ?200 nm of not more than 1×107/cm3.

Abstract: In manufacturing a semiconductor device, the first gettering layer is formed on the backside of a wafer, and the second gettering layers are then formed on the backside and side surfaces of a chip, allowing these gettering layers to serve as trapping sites against metallic contamination that generated after backside grinding in assembly processes.

Abstract: The invention relates to a method of purifying a crystalline silicon substrate and to a process for producing a photovoltaic cell. The method of purifying a crystalline silicon substrate according to the invention is of the type that includes a step of extracting impurities by external gettering and which includes, before said step of extracting the impurities by external gettering, at least one step of rapidly annealing the substrate at a temperature of between 750° C. and 1000° C. inclusive for a time of between 1 second and 10 minutes inclusive. The invention is particularly applicable in the photovoltaic cell field.

Abstract: One aspect of this disclosure relates to a method for creating proximity gettering sites in a silicon on insulator (SOI) wafer. In various embodiments of this method, a relaxed silicon germanium region is formed over an insulator region of the SOI to be proximate to a device region. The relaxed silicon germanium region generates defects to getter impurities from the device region. Other aspects are provided herein.

Abstract: This document discloses devices fabricated on a semiconductor substrate and methods of fabricating the same. The devices can be memory cells having a tunnel window that is defined by dry-etching oxide to expose the semiconductor substrate and growing a tunnel oxide layer on the exposed semiconductor substrate. The semiconductor substrate can be decontaminated and/or repaired by exposing the semiconductor substrate to an optical irradiated energy source having a predefined energy that is sufficient to break molecular bonds of the contaminants and exposing the semiconductor substrate to a temperature that is sufficient to recrystallize the crystal lattice of the substrate.

Abstract: This document discloses devices fabricated on a semiconductor substrate and methods of fabricating the same. The devices can be memory cells having a tunnel window that is defined by dry-etching oxide to expose the semiconductor substrate and growing a tunnel oxide layer on the exposed semiconductor substrate. The semiconductor substrate can be decontaminated and/or repaired by exposing the semiconductor substrate to an optical irradiated energy source having a predefined energy that is sufficient to break molecular bonds of the contaminants and exposing the semiconductor substrate to a temperature that is sufficient to recrystallize the crystal lattice of the substrate.

Abstract: There is provided a production method in which the beveling step conducted for preventing the cracking or chipping in a raw wafer during the grinding can be omitted when the raw wafer cut out from a crystalline ingot is processed into a double-side mirror-finished semiconductor wafer and a semiconductor wafer can be obtained cheaply by shortening the whole of the production steps for the semiconductor wafer and decreasing the machining allowance of silicon material in the semiconductor wafer to reduce the kerf loss of the semiconductor material as compared with the conventional method.

Abstract: A wafer processing method for improving gettering capabilities of wafers made therefrom is presented. The method includes the steps of preparing, annealing and ion-implanting. The preparing step involves preparing the wafer from a silicon ingot. The annealing step involves forming first gettering sites in both sides of the wafer by annealing the wafer. The ion-implanting step involves forming second gettering sites in a back side of the wafer in which the first gettering sites are already formed.

Abstract: An embodiment of fabrication of a variable work function gates in a FUSI device is described. The embodiment uses a work function doping implant to dope the polysilicon to achieve a desired work function. Selective epitaxy growth (SEG) is used to form silicon over the source/drain regions. The doped poly-Si gate is fully silicided to form fully silicided gates that have a desired work function. We provide a substrate having a NMOS region and a PMOS region. We form a gate dielectric layer and a gate layer over said substrate. We perform a (gate Vt) gate layer implant process to implant impurities such as P+, As+, B+, BF2+, N+, Sb+, In+, C+, Si+, Ge+ or Ar+ into the gate layer gate in the NMOS gate regions and said PMOS gate regions. We form a cap layer over said gate layer. We pattern said cap layer, said gate layer and said gate dielectric layer to form a NMOS gate and a PMOS gate. Spacers are formed and S/D regions are formed. A metal is deposited over said substrate surface.

Abstract: Methods and apparatus for processing a substrate are provided herein. In some embodiments, a method of processing a substrate may include providing a substrate having at least one of a defect or a contaminant disposed on or near a surface of the substrate; and selectively annealing a portion of the substrate with a laser beam in the presence of a process gas comprising hydrogen. The laser beam may be moved over the substrate or continuously, or in a stepwise fashion. The laser beam may be applied in a continuous wave or pulsed mode. The process gas may further comprise an inert gas, such as, at least one of helium, argon, or nitrogen. A layer of material may be subsequently deposited atop the annealed substrate.

Abstract: This invention is directed to a process for heat-treating a single crystal silicon segment to influence the profile of minority carrier recombination centers in the segment. The segment is subjected to a heat-treatment to form crystal lattice vacancies, the vacancies being formed in the bulk of the silicon. The segment is then cooled at a rate which allows some, but not all, of the crystal lattice vacancies to diffuse to the front surface to produce a segment having the desired vacancy concentration profile. Platinum atoms are then in-diffused into the silicon matrix such that the resulting platinum concentration profile is substantially related to the concentration profile of the crystal lattice vacancies.

Abstract: A semiconductor wafer is produced by irradiating a laser beam to either face of a semiconductor wafer so as to fit a focusing position into a given depth position of the semiconductor wafer to generate a multiphoton absorption process only in a specific portion of the semiconductor wafer at the given depth position to thereby form a gettering sink.

Abstract: The present invention is a method for producing an SOI wafer comprising at least a step of forming an ion-implanted damaged layer by ion-implanting a neutral element electrically inactive in silicon from one surface of the base wafer or the bond wafer, in which ion-implanting in the step of forming the ion-implanted damaged layer is performed at a dosage of 1×1012 atoms/cm2 or more and less than 1×1015 atoms/cm2. As a result, there may be provided a method for producing an SOI wafer having sufficient gettering ability while the suppression of leak failure, degradation of oxide dielectric breakdown voltage or the like is provided.

Abstract: A water processing method for providing a gettering sink effect to a wafer having a plurality of streets which are formed in a lattice pattern on the front surface of a substrate and devices which are formed in a plurality of areas sectioned by the plurality of streets, comprising the steps of removing distortion produced on the rear surface of the substrate of the wafer whose rear surface of the substrate has been ground to a predetermined thickness; forming a gettering sink effect layer by applying a laser beam of a wavelength having permeability for the substrate of the wafer which has undergone the distortion removing step, with its focal point set to the inside of the substrate to form a deteriorated layer in the inside of the substrate; and dividing the wafer which has undergone the gettering sink effect layer forming step, into individual chips along the streets.

Abstract: A device and a device manufacturing process. First, a gettering layer is formed on the bottom surface of a silicon substrate. Gates having a MOS structure are then formed on the principal surface of the silicon substrate, and the gettering layer is removed. According to this manufacturing method, the formation of the gates having a MOS structure is performed such that the gettering layer getters dissolved oxygen present in the silicon substrate. This reduces the concentration of dissolved oxygen in the silicon substrate, resulting in improved device characteristics.

Abstract: The present disclosure relates to methods of treating a silicon substrate with an ultra-fast laser to create a getter material for example in a substantially enclosed MEMS package. In an embodiment, the laser treating comprises irradiating the silicon surface with a plurality of laser pulses adding gettering microstructure to the treated surface. Semiconductor based packaged devices, e.g. MEMS, are given as examples hereof.

Abstract: According to the present invention, an impurity region, to which a rare gas element (also called a rare gas) and one kind or a plurality of kinds of elements selected from the group consisting of H, H2, O, O2, and P are added, are formed in a semiconductor film having a crystalline structure, using a mask, and gettering for segregating a metal element contained in the semiconductor film to the impurity region by heat treatment. Thereafter, pattering is conducted using the mask, whereby a semiconductor layer made of the semiconductor film having a crystalline structure is formed.

Abstract: A method for manufacturing a silicon wafer having a defect-free region in a surface layer, in which at least only a surface layer region to a predetermined depth from a front surface of a silicon wafer to be processed is subjected to heat treatment at a temperature of not less than 1100 degrees C. for not less than 0.01 msec to not more than 1 sec, to thereby make the surface layer defect-free. As a result of this, there is provided a method for manufacturing a silicon wafer, in which a DZ layer without generation of crystal defects from the front surface to a constant depth can be uniformly formed, and oxide precipitates having a steep profile inside the wafer can be secured and controlled with a high degree of accuracy.

Abstract: Dislocation removal from a group III-V film grown on a semiconductor substrate is generally described. In one example, an apparatus includes a semiconductor substrate, a buffer film including a group III-V semiconductor material epitaxially coupled to the semiconductor substrate wherein the buffer film includes material melted by laser pulse irradiation and recrystallized to substantially remove dislocations or defects from the buffer film, and a first semiconductor film epitaxially grown on the buffer film wherein a lattice mismatch exists between the semiconductor substrate and the first semiconductor film.

Abstract: The present invention provides a method for producing a silicon wafer at least including a step of performing RTA heat treatment with respect to a silicon wafer in an atmospheric gas, wherein nitrogen gas is used as the atmospheric gas, which is mixed with oxygen at a concentration of less than 100 ppm so as to perform the heat treatment. Hereby a method for producing a high-quality wafer can be provided, where the RTA heat treatment subject to the silicon wafer can be performed at a low temperature or over a short period of time, so that generation of slip dislocation of the silicon wafer can be suppressed, and at the same time vacancies can be implanted inside the silicon wafer without using NH3.

Abstract: Disclosed herein are devices, methods and systems for implementing gettering layers. Devices including gettering layers can be implemented such that a gettering layer doped with carbon, boron, fluorine or any other appropriate impurity is formed on a semiconductor substrate, a device layer is formed on the gettering layer, and a device region is formed in the device layer having a depth that maintains a distance in the device layer between the gettering layer and the device region.

Abstract: The present invention relates to a method for manufacturing a semiconductor film, including the steps of forming a transparent conductive film, forming a first conductive film over the transparent conductive film, forming a second conductive film over the first conductive film, etching the second conductive film with a gas including chlorine, and etching the first conductive film with a gas including fluorine. During etching of the second conductive film with a gas including chlorine, the transparent conductive film is protected by the first conductive film. During etching of the first conductive film with the gas including fluorine, the transparent conductive film does not react with the gas including fluorine. Therefore, no particle is formed.

Abstract: A method for manufacturing a semiconductor substrate comprises the steps of: forming a gate oxide film as an insulating layer on the surface of a semiconductor substrate; implanting boron ions for inhibiting the migration of a peeling substance in the semiconductor substrate to form an anti-diffusion layer in the semiconductor substrate; activating boron in the anti-diffusion layer by heat treatment; implanting hydrogen ions into the semiconductor substrate to form a peel layer in part of the semiconductor substrate at a side of the anti-diffusion layer opposite to the gate oxide film; bonding a glass substrate to the surface of the semiconductor substrate where the gate oxide film has been formed; and heat-treating the semiconductor substrate to separate part of the semiconductor substrate along the peel layer.

Abstract: A manufacturing method for a SIMOX substrate for obtaining a SIMOX substrate by subjecting a silicon substrate having oxygen ions implanted thereinto by heat treatment at 1300 to 1350° C. in an atmosphere of a gas mixture of argon and oxygen, the method includes: performing a pre-heat-treatment to the silicon substrate for five minutes to four hours within the temperature range of 1000° C. to 1280° C. in an atmosphere of inert gas, reducing gas, or a gas mixture of inert gas and reducing gas, after the oxygen ions are implanted and before the heat treatment is performed.

Abstract: A method embodiment deposits a dielectric layer over a transistor and then implants a gettering agent into the dielectric layer. The insulating layer into which the gettering agent is implanted comprises a single continuous insulating layer and is the insulating layer that borders the next layer of metallization. After this dielectric layer is formed, standard contacts (tungsten) are formed through the insulating layer to the source, drain, gate, etc. of the transistor. Additionally, reactive ion etching of the contacts is performed. The reactive ion etching process can create mobile ions; however, the gettering agent traps the mobile ions and prevents the mobile ions from contaminating the transistor.

Abstract: A method embodiment deposits a first dielectric layer over a transistor and then implants a gettering agent into the first dielectric layer. After this first dielectric layer is formed, the method forms a second (thicker) dielectric layer over the first dielectric layer. After this, the standard contacts are formed through the insulating layer to the source, drain, gate, etc. of the transistor. Additionally, reactive ion etching, chemical mechanical processing, and other back-end-of-line processing are performed. The back-end-of-line processes can introduce mobile ions into the dielectric over a transistor; however, the gettering agent traps the mobile ions and prevents the mobile ions from contaminating the transistor.

Abstract: The present invention is a method for producing a semiconductor wafer, comprising at least steps of, epitaxially growing a Si1-XGeX layer (0<X<1) on an SOI wafer, forming a Si1-YGeY layer (0?Y<X) on the epitaxially grown Si1-XGeX layer, and then enriching Ge in the epitaxially grown Si1-XGeX layer by an oxidation heat treatment so that the Si1-XGeX layer becomes an enriched SiGe layer, wherein, at least, the oxidation heat treatment is initiated from 950° C. or less under an oxidizing atmosphere, and the oxidation is performed so that the formed Si1-YGeY layer remains during a temperature rise to 950° C. Thereby, there can be provided a method for producing a semiconductor wafer by which the lattice relaxation of the SiGe layer in an SGOI wafer can be sufficiently performed by a heat treatment for a short time and its production cost can be reduced.

Abstract: The invention relates to a method of fabricating a release substrate produced from semiconductor materials, the method comprising creating a reversible connection between two substrate release layers characterized in that the reversible connection is formed by a connecting layer produced using a first material as the basis, the connecting layer further comprising a nanoparticle concentrating zone of a second material disposed to facilitate release of the substrate, the first and second materials being selected to maintain the bonding energy of the reversible connection substantially constant even when the substrate is exposed to heat treatment.

Abstract: The present invention provides a semiconductor substrate, which comprises a singlecrystalline Si substrate which includes an active layer having a channel region, a source region, and a drain region, the singlecrystalline Si substrate including at least a part of a device structure not containing a well-structure or a channel stop region; a gate insulating film formed on the singlecrystalline Si substrate; a gate electrode formed on the gate insulating film; a LOCOS oxide film whose thickness is more than a thickness of the gate insulating film, the LOCOS oxide film being formed on the singlecrystalline Si substrate by surrounding the active layer; and an insulating film formed over the gate electrode and the LOCOS oxide film.