Abstract: A method for suppressing the formation of leakage-promoting defects in a crystal lattice following dopant implantation in the lattice. The process provides a compressive layer of atoms, these atoms having a size greater than that of the lattice member atoms. The lattice is then annealed for a time sufficient for interstitial defect atoms to be emitted from the compressive layer, and in that manner energetically stable defects are formed in the lattice at a distance from the compressive layer.

Abstract: A method for minimizing the effects of defects produced in a implantated area of a crystal lattice during dopant implantation in the lattice. The method begins with the step of implanting a trap layer of trap atoms, the trap atoms having a size less than that of the lattice member atoms. After implantation, the lattice is annealed for a time sufficient for interstitial defect atoms to be emitted from the defect area. In that manner, energetically stable pairs are formed between trap atoms and emitted interstitial atoms.

Abstract: A bonded wafer is produced by implanting ions of a light element into a wafer for active layer to a predetermined depth position to form an ion implanted layer, bonding the wafer for active layer to a wafer for support substrate directly or through an insulating film of not more than 50 nm, exfoliating the wafer for active layer at the ion implanted layer and thinning an active layer exposed through the exfoliation to form the active layer having a predetermined thickness, in which the thickness of the active layer before the thinning is not more than 750 nm and an elongation of slip dislocation in a strength test of the wafer for active layer before the bonding is not more than 100 ?m at a predetermined thickness.

Abstract: A method for producing a silicon wafer, comprising performing an activation of metallic impurities by irradiating laser light on the metallic impurities constituting contaminants in the silicon wafer, changing the electric charge of the contaminants, and activating the contaminants to a state such that the contaminants easily react with oxygen precipitation nuclei and are subjected to gettering.

Abstract: One aspect of this disclosure relates to a method for creating proximity gettering sites in a semiconductor wafer. In various embodiments of this method, a relaxed silicon germanium region is formed to be proximate to a device region on the semiconductor wafer. The relaxed silicon germanium region generates defects to getter impurities from the device region. In various embodiments, an ultra high vacuum chemical vapor deposition (UHV CVD) process is performed to epitaxially form the relaxed silicon germanium gettering region. In various embodiments, forming the relaxed silicon germanium gettering region includes implanting germanium ions into a silicon substrate with a desired dose and energy to form a silicon region containing germanium ions and heat treating the substrate to regrow a crystalline silicon layer over a resulting silicon germanium layer using a solid phase epitaxial (SPE) process. Other aspects are provided herein.

Abstract: A method of forming a high thermal conductivity diamond film and its associated structures comprising selectively nucleating a region of a substrate, and forming a diamond film on the substrate such that the diamond film has large grains, which are at least about 20 microns in size. Thus, the larger grained diamond film has greatly improved thermal management capabilities and improves the efficiency and speed of a microelectronic device.

Abstract: In some embodiments of the invention, encapsulated semiconducting nanomaterials are described. In certain embodiments the nanostructures described are semiconducting nanomaterials encapsulated with ordered carbon shells. In some aspects a method for producing encapsulated semiconducting nanomaterials is disclosed. In some embodiments applications of encapsulated semiconducting nanomaterials are described.

Abstract: A semiconductor wafer for semiconductor components and to a method for its production is disclosed. In one embodiment, the semiconductor wafer includes a front side with an adjoining near-surface active zone as basic material for semiconductor component structures. The rear side of the semiconductor wafer is adjoined by a getter zone for gettering impurity atoms in the semiconductor wafer. The getter zone contains oxygen precipitates. In the near-surface active zone, atoms of doping material are located on lattice vacancies. The atoms of doping material have a higher diffusion coefficient that the oxygen atoms.

Abstract: A thin film transistor array substrate and a method for manufacturing the same is disclosed, in which it is possible to prevent mobile ions contained in a substrate from penetrating into a semiconductor layer by the gettering effect or neutralization in case soda lime glass is used for the substrate. The method includes forming a buffer layer on a substrate; doping impurity ions in the buffer layer; and forming a pixel electrode and a thin film transistor including a semiconductor layer on the buffer layer.

Abstract: A method for improving the quality of a SiC layer by effectively reducing or eliminating the carrier trapping centers in the as-grown SiC crystal. The method includes the steps of: (a) carrying out ion implantation of carbon atoms, silicon atoms, hydrogen atoms, or helium atoms into a shallow surface layer of the SiC crystal layer to introduce carbon interstitials into the surface layer, and (b) growing the SiC layer upward from the edge face of the surface layer into which the carbon interstitials have been introduced, and diffusing out the carbon interstitials that have been introduced into the surface layer from the surface layer into the grown layer and combining the carbon interstitials and point defects to make the electrically active point defects in the grown layer inactive.

Abstract: An embodiment of the invention provides a semiconductor fabrication method. The method comprises forming a strained channel region in semiconductor devices. Embodiments include forming a stressor layer over an amorphous portion of the semiconductor device at an intermediate stage of fabrication. The device is masked and strain in a portion of the stressor layer is relaxed. Recrystallizing the amorphous portion of the intermediate device transfers strain from the stressor to the substrate. At least a portion of the strain remains in the substrate through subsequent device fabrication, thereby improving performance of the completed device. In other embodiments, a tensile stressor layer is formed over a first portion of the device, and a compressive stressor layer is formed over a second portion. A tensile stressor layer forms a compressive channel in a PMOS device, and a compressive stressor forms a tensile channel in an NMOS device.

Abstract: In a method of fabricating a semiconductor memory device, a thyristor may be formed in a layer of semiconductor material. Carbon may be implanted and annealed in a base-emitter junction region for the thyristor to affect leakage characteristics. The density of the carbon and/or a bombardment energy and/or an anneal therefore may be selected to establish a low-voltage, leakage characteristic for the junction substantially greater than its leakage absent the carbon. In one embodiment, an anneal of the implanted carbon may be performed in common with an activation for other implant regions the semiconductor device.

Abstract: The present invention relates to a method of fabricating a semiconductor-on-insulator-type heterostructure that includes at least one insulating layer interposed between a receiver substrate of semiconductor material and an active layer derived from a donor substrate of semiconductor material. The method includes the steps of bonding and active layer transfer. Prior to bonding, an atomic species which is identical or isoelectric with the insulating layer material is implanted in the insulating layer. The implantation forms a trapping layer, which can retain gaseous species present in the various interfaces of the heterostructure, thereby limiting formation of defects on the surface of the active layer.

Abstract: The temperature of a bipolar semiconductor element using a wide-gap semiconductor is raised using heating means, such as a heater, to obtain a power semiconductor device being large in controllable current and low in loss. The temperature is set at a temperature higher than the temperature at which the decrement of the steady loss of the wide-gap bipolar semiconductor element corresponding to the decrement of the built-in voltage lowering depending on the temperature rising of the wide-gap bipolar semiconductor element is larger than the increment of the steady loss corresponding to the increment of the ON resistance increasing depending on the temperature rising.

Abstract: The invention provides methods and systems for laser assisted wirebonding. One or more conditioning laser pulses are used to prepare a bonding surface for wirebonding by removing impurities such as residues from manufacturing processes, oxides, or irregularities on the bonding surface. Subsequently, a free air ball is brought into contact with the conditioned bonding surface to form a weld.

Abstract: Embodiments of a silicon-on-insulator (SOI) wafer having an etch stop layer overlying the buried oxide layer, as well as embodiments of a method of making the same, are disclosed. The etch stop layer may comprise silicon nitride, nitrogen-doped silicon dioxide, or silicon oxynitride, as well as some combination of these materials. Other embodiments are described and claimed.

Abstract: This invention relates to a process for adjusting the strain in a strained layer on a substrate. The process steps include identifying one or more regions of the strained layer wherein the strain is to be adjusted; implanting elements into at least one of the regions thus identified in the strained layer; annealing the substrate with the strained layer to a temperature maintained for a sufficiently long time to cure crystalline defects caused by the implantation in the implanted region or regions.

Abstract: There is provided a damage recovery method capable of recovering electrical characteristics of a low dielectric insulating film sufficiently while suppressing oxidation of buried metal and generation of pattern defaults. A damaged functional group generated in a surface of the low dielectric insulating film by a processing is substituted with a hydrophobic functional group (ST. 2). A damaged component present under a dense layer generated in the surface of the low dielectric insulating film by the substitution process is recovered by using an ultraviolet heating process (ST. 3).

Abstract: An object of the present invention is obtaining a semiconductor film with uniform characteristics by improving irradiation variations of the semiconductor film. The irradiation variations are generated due to scanning while irradiating with a linear laser beam of the pulse emission. At a laser crystallization step of irradiating a semiconductor film with a laser light, a continuous light emission excimer laser emission device is used as a laser light source. For example, in a method of fabricating an active matrix type liquid crystal display device, a continuous light emission excimer laser beam is irradiated to a semiconductor film, which is processed to be a linear shape, while scanning in a vertical direction to the linear direction. Therefore, more uniform crystallization can be performed because irradiation marks can be avoided by a conventional pulse laser.

Abstract: Heavy metal contamination in a device process can be efficiently trapped in a substrate. The present invention comprises: a step of implanting oxygen ions into a wafer; a step of performing a first heat treatment to the wafer in a predetermined gas atmosphere at 1300 to 1390° C. to form a buried oxide layer and also form an SOI layer on a wafer front surface, the wafer before the oxygen ion implantation having an oxygen concentration of 8×1017 to 1.8×1018 atoms/cm3 (old ASTM), the buried oxide layer being formed over the entire wafer surface, the present invention being characterized by including: a step of performing a second heat treatment to the wafer subjected to the first heat treatment in a predetermined gas atmosphere at 400 to 900° C.

Abstract: A method for fabricating free standing thickness of materials using one or more semiconductor substrates, e.g., single crystal silicon, polysilicon, silicon germanium, germanium, group III/IV materials, and others. In a specific embodiment, the present method includes providing a semiconductor substrate having a surface region and a thickness. The method includes subjecting the surface region of the semiconductor substrate to a first plurality of high energy particles generated using a linear accelerator to form a region of a plurality of gettering sites within a cleave region, the cleave region being provided beneath the surface region to defined a thickness of material to be detached, the semiconductor substrate being maintained at a first temperature.

Abstract: A method for producing a semiconductor structure that includes at least one useful layer on a substrate.

Abstract: A process for fabricating an MOS device specifically a DRAM device, featuring passivation of defects in regions of a semiconductor substrate wherein defects left unpassivated can deleteriously influence data retention time, has been developed. A high density plasma dry etching procedure used to define the DRAM conductive gate electrode can create unwanted defects in a region near the surface of uncovered portions of the semiconductor substrate during the high density plasma procedure over etch cycle. Implantation of a group V element such as arsenic can be used to passivate the unwanted plasma etch defects, thus reducing the risk of defect related device leakage phenomena.

Abstract: A process for fabricating a semiconductor device having deep trench structures includes forming a first portion of the trench in a semiconductor substrate and a second portion of the trench in a selectively-formed upper layer. After etching the substrate to form the first portion of the trench, a protective layer is deposited over the inner surface of the trench in the semiconductor substrate and the upper layer is selectively formed on a principal surface of the semiconductor substrate. During formation of the upper layer, a wall surface is formed in the upper layer that is continuous with the wall surface of the trench in the semiconductor substrate. By forming a second portion of the trench in the selectively-formed upper layer, a deep trench is produced having a high aspect ratio and well defined geometric characteristics.

Abstract: A method for treating a gate stack in the fabrication of a semiconductor device by providing a substrate containing a gate stack having a dielectric layer formed on the substrate and a metal-containing gate electrode layer formed on the high-k dielectric layer, forming low-energy excited dopant species from a process gas in a plasma, and exposing the gate stack to the excited dopant species to incorporate a dopant into the gate stack. The method can be utilized to tune the workfunction of the gate stack.

Abstract: A water processing method for providing a gettering sink effect to a wafer having a plurality of streets which are formed in a lattice pattern on the front surface of a substrate and devices which are formed in a plurality of areas sectioned by the plurality of streets, comprising the steps of removing distortion produced on the rear surface of the substrate of the wafer whose rear surface of the substrate has been ground to a predetermined thickness; forming a gettering sink effect layer by applying a laser beam of a wavelength having permeability for the substrate of the wafer which has undergone the distortion removing step, with its focal point set to the inside of the substrate to form a deteriorated layer in the inside of the substrate; and dividing the wafer which has undergone the gettering sink effect layer forming step, into individual chips along the streets.

Abstract: A method of manufacturing a semiconductor device, includes the steps of: raising a temperature of a sapphire substrate which is included in the semiconductor device from a room temperature to a preheat temperature of 150° C. to 450° C. and keeping the preheat temperature for a first predetermined time, thereby preheating the semiconductor device; and subsequently raising a temperature of the sapphire substrate from the preheat temperature to a thermal reaction temperature of 500° C. or higher and keeping the thermal reaction temperature for a second predetermined time, thereby performing a thermal reaction treatment of the semiconductor device.

Abstract: A heterostructure device layer is epitaxially grown on a virtual substrate, such as an InP/InGaAs/InP double heterostructure. A device substrate and a handle substrate form the virtual substrate. The device substrate is bonded to the handle substrate and is composed of a material suitable for fabrication of optoelectronic devices. The handle substrate is composed of a material suitable for providing mechanical support. The mechanical strength of the device and handle substrates is improved and the device substrate is thinned to leave a single-crystal film on the virtual substrate such as by exfoliation of a device film from the device substrate. An upper portion of the device film exfoliated from the device substrate is removed to provide a smoother and less defect prone surface for an optoelectronic device. A heterostructure is epitaxially grown on the smoothed surface in which an optoelectronic device may be fabricated.

Abstract: The present method provides tools for growing conformal metal nitride, metal carbide and metal thin films, and nanolaminate structures incorporating these films, from aggressive chemicals. The amount of corrosive chemical compounds, such as hydrogen halides, is reduced during the deposition of transition metal, transition metal carbide and transition metal nitride thin films on various surfaces, such as metals and oxides. Getter compounds protect surfaces sensitive to hydrogen halides and ammonium halides, such as aluminum, copper, silicon oxide and the layers being deposited, against corrosion. Nanolaminate structures (20) incorporating metal nitrides, such as titanium nitride (30) and tungsten nitride (40), and metal carbides, and methods for forming the same, are also disclosed.

Abstract: A method of degassing a thin layer and a method of manufacturing a silicon thin film includes applying microwaves to a silicon thin film deposited on a substrate to induce a resonance of impurities of H2, Ar, He, Xe, O2, and the like present in the silicon thin film so as to remove the impurities from the silicon thin film. A wavelength of the microwaves is equal to a natural frequency of an element of an object to be removed. According to a resonance of impurities induced by microwaves, the impurities can be very effectively removed from the silicon thin film so as to obtain a high quality silicon thin film. In particular, the microwaves are very suitable to be used in the manufacture of silicon thin films at low temperature.

Abstract: The present invention provides methods for forming SOI wafers having internal gettering layers for sequestering metallic impurities. More particularly, in one embodiment of the invention, a plurality of sites for sequestering metallic impurities are formed in a silicon substrate by implanting a selected dose of oxygen ions therein. In one embodiment, an epitaxial layer of crystalline silicon is formed over the substrate, and a buried continuous oxide layer is generated in the epitaxial layer, for example, by employing a SIMOX process.

Abstract: A method of fabricating a thin film is disclosed. The method comprises: implanting ions by bombarding a face of a substrate comprising a semiconductor material to form a concentrated layer of the implanted ions at a predetermined mean depth in the substrate, the concentrated layer and the face of the substrate defining a thin film therebetween; trapping contaminants included in the substrate or the thin film, in the concentrated layer by heat treating the substrate such that the heat treatment does not split the substrate at the concentrated layer; detaching the thin film from the substrate after the trapping by splitting the substrate at the concentrated layer; and withdrawing a zone of the thin film perturbed by the trapping and the detaching.

Abstract: Methods and apparatus are described for irradiating one or more substrate surfaces with accelerated gas clusters including strain-inducing atoms for blanket and/or localized introduction of such atoms into semiconductor substrates, with additional, optional introduction of dopant atoms and/or C. Processes for forming semiconductor films infused into and/or deposited onto the surfaces of semiconductor and/or dielectric substrates are also described. Such films may be doped and/or strained as well.

Abstract: A method for forming a semiconductor substrate that can be dismantled, comprising the following steps: introduction of gaseous species in the substrate according to conditions enabling the constitution of an embrittled layer by the presence in said layer of micro-cavities and/or micro-bubbles, a thin layer of semiconductor material thus being delimited between the embrittled layer and one face of the substrate, thermal treatment of the substrate to increase the brittleness level of the embrittled layer, said thermal treatment being continued until the appearance of local deformations on said face of the substrate in the form of blisters but without generating exfoliations of the thin layer during this step and during the continuation of the method, epitaxy of semiconductor material on said face of the substrate to provide at least one epitaxial layer on said thin film.

Abstract: Semiconductor devices have device regions in which semiconductor properties such as spreading resistivity and its profile are significant. In making a p-type device region on a semiconductor wafer, an initial semiconductor device region is defined by a buried region, and an initial spreading resistivity profile is developed by annealing. After annealing, semiconductor device properties can be enhanced by removing a surface sub-region of the initial device region, and can be further improved by epitaxially growing thereon a monocrystalline film as an improved channel layer for FET devices. Such properties are relevant in MOS as well as bipolar devices.

Abstract: An orientation ratio of a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film is increased, a distortion thereof is suppressed, and a TFT using such a crystalline semiconductor film is provided. At the time of formation of the amorphous semiconductor film (102) or after the formation thereof, a noble gas element, typically, argon is included in the film and crystallization is performed therefor. Thus, an orientation ratio of the semiconductor film (104) can be increased and a distortion present in the semiconductor film (104) after the crystallization is suppressed as compared with that present in the semiconductor film before the crystallization. Then, the noble gas element in the film is removed or reduced by laser light irradiation performed later.

Abstract: A hydrogen (H) exfoliation gettering method is provided for attaching fabricated circuits to receiver substrates. The method comprises: providing a Si substrate; forming a Si active layer overlying the substrate with circuit source/drain (S/D) regions; implanting a p-dopant into the S/D regions; forming gettering regions underling the S/D regions; implanting H in the Si substrate, forming a cleaving plane (peak concentration (Rp) H layer) in the Si substrate about as deep as the gettering regions; bonding the circuit to a receiver substrate; cleaving the Si substrate along the cleaving plane; and binding the implanted H underlying the S/D regions with p-dopant in the gettering regions, as a result of post-bond annealing.

Abstract: A method of detaching a thin film from a source substrate comprises the steps of implanting ions or gaseous species in the source substrate so as to form therein a buried zone weakened by the presence of defects; and splitting in the weakened zone leading to the detachment of the thin film from the source substrate. Two species are implanted of which one is adapted to form defects and the other is adapted to occupy those defects, the detachment being made at a temperature lower than that for which detachment could be obtained with solely the dose of the first species.

Abstract: A method for making a semiconductor device is described. That method includes forming on a substrate a dielectric layer that has a dielectric constant that is greater than the dielectric constant of silicon dioxide. The dielectric layer is modified so that it will be compatible with a gate electrode to be formed on the dielectric layer, and then a gate electrode is formed on the dielectric layer.

Abstract: A manufacturing method of a semiconductor device, the method including implanting impurity ions into a silicon layer and irradiating a pulsed light having a pulse width of 100 milliseconds or less and a rise time of 0.3 milliseconds or more onto the silicon layer thereby activating the impurity ions. The rise time is defined as a time interval of a leading edge between an instant at which the pulsed light starts to rise and an instant at which the pulsed light reaches a peak energy.

Abstract: Disclosed is a method for gettering a transition metal impurity diffused in a silicon crystal at ultra high-speeds to form deep impurity levels therein. The method comprises codoping two kinds of impurities: oxygen and carbon, into silicon, and thermally annealing the impurity-doped silicon to precipitate an impurity complex of an atom of the transition metal impurity, the C and the O, in the silicon crystal, so that the transition metal impurity is confined in the silicon crystal to prevent the ultra high-speed diffusion of the transition metal impurity and electrically deactivate deep impurity levels to be induced by the transition metal impurity.

Abstract: A semiconductor device includes at least one thin film transistor including a semiconductor layer that has a crystalline region including a channel region, a source region and a drain region, a gate insulating film disposed at least on the channel region, the source region and the drain region of the semiconductor layer, and a gate electrode arranged so as to oppose the channel region via the gate insulating film. At least a portion of the semiconductor layer includes a catalyst element capable of promoting crystallization, and the semiconductor layer further includes a gettering region that includes the catalyst element at a higher concentration than in the channel region or the source region and the drain region. The thickness of the gate insulating film on the gettering region is smaller than that on the source region and the drain region, or the gate insulating film is not disposed on the gettering region.

Abstract: Impurity ions contained in a semiconductor layer are diffused downwardly from a gate electrode by irradiating laser light from the back surface of a transparent substrate after source-drain regions are formed. Thus, a GOLD structure is formed. Consequently, the GOLD structure is formed by performing a smaller number of processes. Also, variation in characteristics can be suppressed by preventing occurrence of asymmetry between left and right LDD regions.

Abstract: A method for stably activating pn-successive layers in a semiconductor element in a short time is disclosed. Pulsed beams, each of which has a pulse shape that is approximately rectangular, are projected from respective laser irradiation devices and successively combined into a pulsed beam equivalent to one pulse, with which the doped layer region is irradiated. By successively projecting the pulsed beams onto the doped layer region in this way, an effect is obtained which is the same as that of irradiating the doped layer region with a single pulsed beam having a long full-width at half maximum. A high activation ratio from a shallow region to a deep region of the doped layer region is enabled. This can stably activate the semiconductor element having the pn-successive layers as the doped layer region in a short time, making possible the manufacture of semiconductor elements having superior device characteristics.

Abstract: The present invention is directed to a single crystal Czochralski-type silicon wafer, and a process for the preparation thereof, which has at least a surface layer of high resistivity, the layer having an interstitial oxygen content which renders it incapable of forming thermal donors in an amount sufficient to affect resistivity upon being subjected to a conventional semiconductor device manufacturing process. The present invention further directed to a silicon on insulator structure derived from such a wafer.

Abstract: An optical semiconductor device includes a laminated layer structure, an intermediate film formed on an end surface of the laminated layer structure, and a passivation film formed on the intermediate film. The passivation film has a quantity of ion projection than that of the intermediate film.

Abstract: To provide a method of removing a catalyst element from a crystalline silicon film obtained by solid phase growth using the catalyst element promoting crystallization, phosphorus is implanted selectively to the crystalline silicon film having the catalyst element whereby a portion of the silicon film implanted with phosphorus is made amorphous, and when a thermal annealing treatment is performed and the silicon film is heated, the catalyst element is moved to an amorphous portion implanted with phosphorus having large getting capacity by which the concentration of the catalyst element in the silicon film is lowered and a semiconductor device is fabricated by using the silicon film.

Abstract: The present invention provides a method for generating silicon-on-insulator (SOI) wafers that exhibit a high electrical resistivity. In one embodiment of a method according to the teachings of the invention, a SIMOX process is sandwiched between two Full Oxygen Precipitation (FOP) cycles that sequester interstitial oxygen present in the substrate in the form of oxide precipitates, thereby enhancing the electrical resistivity of the susbtrate.

Abstract: The surface of a semiconductor material, e.g., gallium arsenide, is passivated by irradiating the surface with ultra-short laser pulses, until a stable passive surface is achieved. The passive surface so prepared is devoid of a superficial oxide layer.

Abstract: One aspect of the invention relates to a method of forming P-N junctions within a semiconductor substrate. The method involves providing a temporary impurity species, such as fluorine, within the semiconductor crystal matrix prior to solid source in-diffusion of the primary dopant, such as boron. The impurity atom is a faster diffusing species relative to silicon atoms. During in-diffusion, the temporary impurity species acts to reduce the depth to which the primary dopant diffuses and thereby facilitates the formation of very shallow junctions.