Abstract: A system for improving drift compensation for ion mill applications defines a reference step for purposes of time duration. The reference step is controlled by an end point detector and monitored for use with subsequent process steps. The time duration for a subsequent step is adjusted as a percentage of the reference step. A time scaling factor determines the actual duration of the subsequent step. Rather than directly using times of step duration, the system uses a percentage of the reference step for the latter step. The duration of the reference step varies depending on the tool drift. The overall duration is changed in the same proportion as the duration of the reference step, and thereby compensates for the influence of drift on the end product.

Abstract: The present invention is directed to a process for producing a silicon on insulator (SOI) structure having intrinsic gettering, wherein a silicon substrate is subjected to an ideal precipitating wafer heat treatment which enables the substrate, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process to form an ideal, non-uniform depth distribution of oxygen precipitates, and wherein a dielectric layer is formed beneath the surface of the wafer by implanting oxygen or nitrogen ions, or molecular oxygen, beneath the surface and annealing the wafer. Additionally, the silicon wafer may initially include an epitaxial layer, or an epitaxial layer may be deposited on the substrate during the process of the present invention.

Abstract: A method and apparatus for removal of volatile contaminants from substrate surfaces before the substrate enters a process chamber. Substrate cleaning is achieved by irradiating the substrate with a low-energy electron beam. The interaction of the electrons in the beam with the contaminants present on the surface of the substrate causes evaporation of low vapor pressure species which can be deposited on the surface. A cryoshield pumps the evaporated species. After evaporation and pumping, the substrate passes through a glow discharge chamber wherein the negative surface charge created by the electron beam is neutralized using positive ions. The inventive apparatus can be configured so that no separate vacuum chamber is needed to prepare the substrate.

Abstract: A method of reducing fluorine contamination on a integrated circuit wafer surface is achieved. The method comprises placing an integrated circuit wafer on a cathode stage. The integrated circuit wafer comprises a surface contaminated with fluorine. The integrated circuit wafer is plasma treated with a plasma comprising a reducing gas that forms HF from the fluorine and a bombardment gas that removes the fluorine from the surface. The cathode stage is heated to thereby increase the rate of the fluorine removal.

Abstract: A bonded semiconductor-on-insulator substrate for an integrated circuit. The bonded semiconductor-on-insulator substrate includes a wafer, a handle wafer and an insulating bond layer. The wafer has a first layer of monocrystalline semiconductor material adjacent a first surface of the wafer. The wafer also has a second layer of undamaged by implantation monocrystalline semiconductor material adjacent a second surface of the wafer. The wafer further has a substantially planar intrinsic gettering zone of substantially pure semiconductor material and active gettering sites positioned between the first and second layers formed by implanting ions of the semiconductor material through the first layer of monocrystalline semiconductor material. The insulating bond layer bonds the handle wafer to the first surface of the wafer.

Abstract: A method for forming a plurality of MOSFETs wherein each one of the MOSFET has a unique predetermined threshold voltage. A doped well or tub is formed for each MOSFET. A patterned mask is then used to form a material line proximate each semiconductor well, wherein the width of the line is dependent upon the desired threshold voltage for the MOSFET. A tilted ion implantation is performed at an acute angle with respect to the substrate surface such that the ion beam passes through the material line. Thicker lines have a lower transmission coefficient for the ion beam and thus the intensity of the ion beam reaching the adjacent semiconductor well is reduced. By appropriate selection of the line width the dopant density in the well, and thus the final MOSFET threshold voltage, is controllable.

Abstract: A method of the present invention includes the steps of forming an amorphous semiconductor layer on an insulative surface, adding a catalyst element capable of promoting crystallization to the amorphous semiconductor layer and then performing a first heat treatment so as to crystallize the amorphous semiconductor layer, thereby obtaining a crystalline semiconductor layer, performing a first gettering process to remove the catalyst element from the semiconductor layer, and performing a second gettering process that is different from the first gettering process to remove the catalyst element from the semiconductor layer. The first gettering process includes removing at least large masses of a semiconductor compound of the catalyst element present in the crystalline semiconductor layer.

Abstract: One embodiment of the present invention is an electron beam treatment apparatus that includes: (a) an array of lamps that output radiation; (b) a support mechanism adapted to support a substrate at a treatment position above the lamps; and (c) a lamp heat shield, disposed above the array, having a radiation absorption portion adapted to absorb radiation from at least a portion of the array, and a radiation reflection portion adapted to reflect radiation from at least a portion of the array towards the substrate when disposed at the treatment position.

Abstract: Phosphorus is implanted into a crystalline semiconductor film by an ion dope method. However, a concentration of phosphorus required for gettering is 1×1020/cm3 or higher which hinders recrystallization by later anneal, and thus this becomes a problem. Also, when phosphorus is added at a high concentration, processing time required for doping is increased and throughput in a doping step is reduced, and thus this becomes a problem. The present invention is characterized in that impurity regions to which an element belonging to the group 18 of the periodic table is added are formed in a semiconductor film having a crystalline structure and gettering for segregating in the impurity regions a metal element contained in the semiconductor film is performed by heat treatment. Also, a one conductivity type impurity may be contained in the impurity regions.

Abstract: According to the present invention, an impurity region, to which a rare gas element (also called a rare gas) and one kind or a plurality of kinds of elements selected from the group consisting of H, H2, O, O2, and P are added, are formed in a semiconductor film having a crystalline structure, using a mask, and gettering for segregating a metal element contained in the semiconductor film to the impurity region by heat treatment. Thereafter, pattering is conducted using the mask, whereby a semiconductor layer made of the semiconductor film having a crystalline structure is formed.

Abstract: A method of hydrogenating a poly-silicon layer is disclosed, which is used to improve characteristics of a thin film transistor (TFT) having a poly-silicon thin film. In the method, the poly-silicon layer is first subject to a plasma pre-process and then a hydrogenating process is undertaken thereon where a hydrogen-containing silicon-based compound is deposited over the poly-silicon layer having being pre-processed by the plasma and thermal treated. As such, the hydrogen atoms in the hydrogen-containing silicon-based compound may diffuse into the poly-silicon layer and the hydrogen atoms at a surface of the poly-silicon layer may further diffuse into where need to be filled to promote the hydrogenation effect of the poly-silicon layer, i.e., the hydrogenation may be completed in a shorter time.

Abstract: The invention provides a method for activating impurity element added to a semiconductor and performing gettering process in shirt time, and a thermal treatment equipment enabling to perform such the heat-treating.

Abstract: A regular array and method of forming a substantially regular array of microscopic structures on a surface of a sample is described. A device of the present invention comprises a microscopic layer of at least one first material on a substrate of a second material, wherein the microscopic layer is sufficiently thin that stress fields at the interface of the microscopic layer and the substrate cause formation of separated regions of the first material on the substrate. The microscopic layer on the sample is irradiated by means of a particle beam at an acute angle to influence the direction of alignment of the separated regions and/or the relative position of adjacent the separated regions.

Abstract: The present invention provides a method and apparatus for lift-off of a thin layer from a crystalline substrate, preferably the layer from a silicon wafer to further form a silicon-on-insulator (SOI) sandwich structure, wherein a separation layer is formed inside a donor wafer by trapping hydrogen into a preformed, buried defect-rich layer preferably obtained by implanting a low dose of light ions through a protective layer deeply into this donor wafer. The donor wafer is then bonded to a second wafer and then split at the separation layer using a splicing apparatus. The invention also provides a “Wide Area Ion Source” (WAIS) that performs both implants in a very cost effective manner.

Abstract: A method of manufacturing a semiconductor device on a silicon-on-insulator wafer including a silicon active layer having at least two die pads formed thereon, the at least two die pads separated by at least one scribe lane, including the steps of forming at least one cavity through the silicon active layer in the at least one scribe lane; forming at least one gettering plug in each said cavity, each said gettering plug comprising doped fill material containing a plurality of gettering sites; and subjecting the wafer to conditions to getter at least one impurity into the plurality of gettering sites.

Abstract: A method of forming a varactor includes forming an ion well of a first conductivity type on a substrate and a plurality of isolation structures on the ion well. The isolation structures define at least an active area on the ion well. Following that, ions of the first conductivity type are implanted into the ion well to form a doping region within the active area. A doping layer of a second conductivity type is then formed on the substrate to cover portions of the doping region. A salicide layer is formed on the doping region and the doping layer.

Abstract: Methods for forming a single crystal semiconductor thin film layer from a non-single crystal layer includes directing a light source having a homogenized intensity distribution and a modulated amplitude towards the non-single crystal layer, and relatively moving the light with respect to the layer wherein the amplitude of the conditioned light is preferably increased in the direction of relative motion of the light to the layer. Preferred methods also include multiple light exposures in overlapping series to form ribbon-shaped single crystal regions, and providing a low temperature point in the semiconductor layer to generate a starting location for single crystalization.

Abstract: A process for providing regions of substantially lower fluorine content in a fluorine-containing dielectric comprises exposing the fluorine-containing dielectric to a reactive species to form volatile byproducts.

Abstract: To realize a method for detecting variations in conditions (drift of the exposure and drift of the focus) in exposure equipment at a product wafer level in lithography process, the process is specified in such a way that calculation results of feature quantities such as electron beam images, line profiles, dimensions, etc. under various sets of the exposure and the focus are stored as a library, and an electron beam image of the product wafer is compared with these pieces of data in the library so that detection of drifts of the exposure and the focus a check of the results on the screen can easily be performed.

Abstract: An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.

Abstract: The present invention is directed to a single crystal Czochralski-type silicon wafer, and a process for the preparation thereof, which has at least a surface layer of high resistivity, the layer having an interstitial oxygen content which renders it incapable of forming thermal donors in an amount sufficient to affect resistivity upon being subjected to a conventional semiconductor device manufacturing process. The present invention further directed to a silicon on insulator structure derived from such a wafer.

Abstract: A method of fabricating a silicon-on-insulator structure having a silicon surface layer in a semiconductor workpiece, is carried out by maintaining the workpiece at an elevated temperature and producing an oxygen-containing plasma in the chamber while applying a bias to the workpiece and setting the bias to a level corresponding to an implant depth in the workpiece below the silicon surface layer to which oxygen atoms are to be implanted, whereby to form an oxygen-implanted layer in the workpiece having an oxygen concentration distribution generally centered at the implant depth and having a finite oxygen concentration in the silicon surface layer. The oxygen concentration in the silicon surface layer is then reduced to permit epitaxial silicon deposition.

Abstract: Disclosed is a method of manufacturing a semiconductor wafer. In the present invention, a nucleation site is formed in a region deep into the wafer through low-temperature annealing process, and oxygen or precipitation material, the metallic impurity, or the like is trapped in the nucleation site through rapid thermal annealing process. As a gettering effect is improved using the rapid thermal annealing process, the concentration of the impurity on the surface of the wafer can be lowered and the reliability of the device could be improved. Further, the annealing steps can be reduced than the prior art and the productivity of the device can thus be increased.

Abstract: According to the present invention, an impurity region, to which a rare gas element (also called a rare gas) and one kind or a plurality of kinds of elements selected from the group consisting of H, H2, O, O2, and P are added, are formed in a semiconductor film having a crystalline structure, using a mask, and gettering for segregating a metal element contained in the semiconductor film to the impurity region by heat treatment. Thereafter, pattering is conducted using the mask, whereby a semiconductor layer made of the semiconductor film having a crystalline structure is formed.

Abstract: A method for producing a thin-film transistor by using a crystalline silicon film that has been formed by using nickel as a metal element for accelerating crystallization of silicon. In forming source and drain regions, phosphorus as an element for gettering nickel is introduced therein by ion implantation. Nickel gettering is effected by annealing. For example, in the case of producing a P-channel thin-film transistor, both phosphorus and boron are used. Boron determines a conductivity type, and phosphorus is used as a gettering material.

Abstract: A method is provided for gettering impurities from silicon wafers and devices to improve the quality of the material and the device performance. The wafer or the device is coated on the back-side with a layer of aluminum and is illuminated form the other side with light having a significant portion of energy in the IR region. This process leads to formation of a Si—Al melt on the backside, at temperature below 550° C. Dissolved impurities in the Si diffuse toward the Al melt and are trapped there. At higher illuminations and concomitant higher temperatures, the Al interface serves as a source of point defect injection. This mode of processing causes dissolution of precipitated impurities at greatly reduced temperatures and in short periods of time.

Abstract: A buried bit line and a fabrication method thereof, wherein the device includes a substrate, a shallow doped region disposed in the substrate, a deep doped region disposed in the substrate below a part of the shallow doped region, wherein the shallow doped region and the deep dope region together form a bit line of the memory device.

Abstract: A process for providing regions of substantially lower fluorine content in a fluorine-containing dielectric comprises exposing the fluorine-containing dielectric to a reactive species to form volatile byproducts.

Abstract: A method of bonding a germanium (Ge) wafer to a semiconductor wafer. A Ge wafer having a cleaving plane defined by ion implantation is provided. A surface activation on at least one surface of the Ge wafer is performed. A semiconductor wafer is provided. A surface activation on at least one surface of the semiconductor wafer is performed. The Ge wafer is bonded to the semiconductor wafer to form a bonded wafer pair. A first annealing is performed to the bonded wafer pair. The first annealing occurs at a temperature approximately between 50-100° C. A second annealing is performed to the bonded wafer pair. The second annealing occurs at a temperature approximately between 110-170° C. The second annealing cleaves the Ge wafer at the cleaving plane.

Abstract: An SOI semiconductor device includes at least an SOI substrate including an insulating film and a semiconductor layer formed on the insulating film; and an active semiconductor element formed on the semiconductor layer. The active semiconductor element is formed in an element formation region surrounded by an isolating region for isolating the semiconductor layer in a form of an island. A gettering layer containing a high concentration impurity is formed in a portion of the semiconductor layer excluding the element formation region in which the active semiconductor element is formed, and the gettering layer is not formed in the element formation region in which the active semiconductor element is formed.

Abstract: A process for heat-treating a single crystal silicon segment to influence the profile of minority carrier recombination centers in the segment. The segment has a front surface, a back surface, and a central plane between the front and back surfaces. In the process, the segment is subjected to a heat-treatment to form crystal lattice vacancies, the vacancies being formed in the bulk of the silicon. The segment is then cooled from the temperature of said heat treatment at a rate which allows some, but not all, of the crystal lattice vacancies to diffuse to the front surface to produce a segment having a vacancy concentration profile in which the peak density is at or near the central plane with the concentration generally decreasing in the direction of the front surface of the segment. Platinum atoms are then in-diffused into the silicon matrix such that the resulting platinum concentration profile is substantially related to the concentration profile of the crystal lattice vacancies.

Abstract: In a method of manufacturing a semiconductor device, after a lateral growth region 107 is formed by using a catalytic element for facilitating crystallization of silicon, the catalytic element is gettered into a phosphorus added region 108 by a heat treatment. Thereafter, a gate insulating film 113 is formed to cover active layers 110 to 112 formed, and in this state, a thermal oxidation step is carried out. By this, the characteristics of an interface between the active layers and the gate insulating film can be improved while abnormal growth of a metal oxide is prevented.

Abstract: A mask including a material, which has heat resistance and light absorptivity, is selectively formed on a crystalline silicon film containing a catalytic element. Next, by using the mask, phosphorus is implanted into the silicon film and an implanted portion of the silicon film is transformed into amorphous. Then the silicon film is heated by a rapid thermal annealing (RTA) method, so that the temperature of the portion covered with the mask becomes higher than other portions. As a result, the catalytic element moves from the high temperature portion covered with the mask to the lower temperature amorphous portion in which phosphorus has been implanted and which has a large gettering capacity. Thus, the concentration of the catalytic element in the portion covered with the mask is lowered, and a semiconductor device is manufactured by using the film.

Abstract: The present invention relates to a method of manufacturing a semiconductor device having an excellent gettering effect. In this method, when phosphorus is added to a poly-Si film, which has been crystallized by the addition of a metal, to subject the resultant poly-Si film to the heat treatment to carry out gettering therefor, the device is performed for the shape of the island-like insulating film on the poly-Si film which is employed when implanting phosphorus. Thereby, the area of the boundary surface between the region to which phosphorus has been added and the region to which no phosphorus has been added is increased to enhance gettering efficiency.

Abstract: Disclosed are a non-volatile memory device to protect a floating gate from charge loss and a method for forming the same. At least a pair of floating gate lines are formed on a semiconductor substrate. A portion of the substrate between the floating gate lines is etched to form a trench therein. A gap-fill dielectric layer is formed in the trench and also in the gap between the pair of floating gate lines. The gap-fill dielectric layer is implanted with impurities so that positive mobile ions that may permeate the floating gate through the gap-fill dielectric layer can be trapped in the gap-fill dielectric layer.

Abstract: The present invention is characterized in that gettering is performed such that impurity regions to which a noble gas element is added are formed in a semiconductor film and the metallic element included in the semiconductor film is segregated into the impurity regions by laser annealing. Also, a reflector is provided under a substrate on which a semiconductor film is formed. When laser light transmitted through the semiconductor film substrate is irradiated from the front side of the substrate, the laser beam is reflected by the reflector and thus the laser light can be irradiated to the semiconductor film from the read side thereof. Laser light can be also irradiated to low concentration impurity regions overlapped with a portion the gate electrode. Thus, an effective energy density in the semiconductor film is increased to thereby effect recovery of crystallinity and activation of the impurity element.

Abstract: The invention relates to a method for generating defect profiles in a crystal or crystalline structure of a substrate, preferably a semiconductor, during a thermal treatment in a process chamber. According to the inventive method, a concentration and/or a density distribution of defects is controlled with at least one reactive component each depending on at least two process gases that differ in their composition. At least two of the process gases independently act upon at least two different surfaces of the substrate.

Abstract: A bonded semiconductor-on-insulator substrate for an integrated circuit. The bonded semiconductor-on-insulator substrate includes a wafer, a handle wafer and an insulating bond layer. The wafer has a first layer of monocrystalline semiconductor material adjacent a first surface of the wafer. The wafer also has a second layer of undamaged by implantation monocrystalline semiconductor material adjacent a second surface of the wafer. The wafer further has a substantially planar intrinsic gettering zone of substantially pure semiconductor material and active gettering sites positioned between the first and second layers formed by implanting ions of the semiconductor material through the first layer of monocrystalline semiconductor material. The insulating bond layer bonds the handle wafer to the first surface of the wafer.

Abstract: A regular array and method of forming a substantially regular array of microscopic structures on a surface of a sample is described. A device of the present invention comprises a microscopic layer of at least one first material on a substrate of a second material, wherein the microscopic layer is sufficiently thin that stress fields at the interface of the microscopic layer and the substrate cause formation of separated regions of the first material on the substrate. The microscopic layer on the sample is irradiated by means of a particle beam at an acute angle to influence the direction of alignment of the separated regions and/or the relative position of adjacent the separated regions.

Abstract: A method of fabricating a silicon-on-insulator structure having a silicon surface layer in a semiconductor workpiece, is carried out by maintaining the workpiece at an elevated temperature and producing an oxygen-containing plasma in the chamber while applying a bias to the workpiece and setting the bias to a level corresponding to an implant depth in the workpiece below the silicon surface layer to which oxygen atoms are to be implanted, whereby to form an oxygen-implanted layer in the workpiece having an oxygen concentration distribution generally centered at the implant depth and having a finite oxygen concentration in the silicon surface layer. The oxygen concentration in the silicon surface layer is then reduced to permit epitaxial silicon deposition.

Abstract: A small semiconductor display device of low power consumption and with high definition/high resolution/high image quality is provided. The semiconductor display device according to the present invention comprises a pixel matrix circuit, a data line driver circuit and scanning line driver circuits, and these components are formed on the same substrate using a polycrystalline TFT. The fabricating method of the device which includes a process for promoting crystallization by a catalytic element and a process for gettering the catalytic element provides the semiconductor display device with high definition/high resolution/high image quality while it is small in size.

Abstract: Non-alloyed, low resistivity contacts for semiconductors using Group III-V and Group II-VI compounds and methods of making are disclosed. Co-implantation techniques are disclosed.

Abstract: A process for modifying the surface of a polymeric substrate. The process includes digitally applying a photoreactive material comprising at least one photochemical electron donor to a region of a polymeric substrate and exposing at least a portion of that region to actinic radiation. The modified surface of the polymeric substrate may be bonded to one or more additional substrates, or may be coated with a fluid.

Abstract: The invention relates to a process for the treatment of substrates (1) for microelectronics or optoelectronics comprising a working layer (6) at least partially composed of an oxidizable material on at least one of their faces, this process comprising:

Abstract: White defects caused by a dark-current of a solid-state imaging device is reduced by effectively bringing out gettering capability of a buried getter sink layer. A buried getter sink layer is formed by introducing to the semiconductor substrate a substance of a second element which is a congener of a first element composing a semiconductor substrate, a crystal growth layer is formed by crystal growing a substance of the first element on a surface of the semiconductor substrate, and a solid-state imaging element is formed inside and on the crystal growth layer at a lower temperature than that in the case of forming an extrinsic getter sink layer by introducing a substance of a third element of a different group from the first element on a back surface of the semiconductor substrate.

Abstract: There is disclosed a method of fabricating TFTs using a silicon film crystallized with the aid of nickel. The nickel is removed from the crystallized silicon film. The method starts with maintaining nickel in contact with the surface of an amorphous silicon film. Then, a heat treatment is performed to form a crystalline silicon film. At this time, nickel promotes the crystallization greatly, and nickel diffuses into the film. A mask is formed. A silicon film heavily doped with phosphorus is formed. Thereafter, a heat treatment is performed to move the nickel from the crystalline silicon film into the phosphorus-rich silicon film. This reduces the concentration of nickel in the crystalline silicon film.

Abstract: There are provided a heat-treating method capable of both increasing BMD density and widening DZ layer width, and a silicon wafer having DZ layer width wider compared with a conventional one regardless of high BMD density. In the method, heat treatment (RTA treatment) is performed to a silicon wafer containing interstitial oxygen with a rapid heating-rapid cooling apparatus, thereby atomic vacancies being injected from a surface of the wafer to form a maximum position of an atomic vacancy concentration in a depth direction in the vicinity of the surface of the wafer, and thereafter heat treatment (post annealing) is performed to move the maximum position of the atomic vacancy concentration in the vicinity of the surface of the wafer into the inside of the wafer.

Abstract: The present invention, in one embodiment, relates to a process for fabricating a semiconductor device that is less susceptible to performance degradation caused by hydrogen contamination. The method includes the steps for removing unwanted hydrogen bonds by exposing the hydrogen bonds to ultraviolet radiation sufficient to break the bond and annealing in an atmosphere comprising at least one gas having at least one atom capable of forming bonds that replace the hydrogen bonds.

Abstract: A technique for forming a gettering layer in a wafer made using a controlled cleaving process. The gettering layer can be made by implanting using beam line or plasma immersion ion implantaion, or made by forming a film of material such as polysilicon by way of chemical vapor deposition. A controlled cleaving process is used to form the wafer, which is a multilayered silicon on insulator substrate. The gettering layer removes and/or attracts impurities in the wafer, which can be detrimental to the functionality and reliability of an integrated circuit device made on the wafer.

Abstract: A method of fabricating electronic devices, integrated monolithically in a semiconductor substrate having at least one non-active area contiguous with at least one device active area, which method comprises at least one step of implanting ions of a noble gas, followed by a thermal treatment to form getter microcavities in the semiconductor by evaporation of the noble gas, wherein the implanting step is carried out in the non-active area of the semiconductor.