Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises laterally-spaced memory-block regions. Channel-material strings extend through the first tiers and the second tiers. Material of the first tiers is of different composition from material of the second tiers. Conducting material is formed in one of the first tiers. The conducting material comprises a seam in and longitudinally-along opposing sides of individual of the memory-block regions in the one first tier. The seam is penetrated with a fluid that forms intermediate material in the seam longitudinally-along the opposing sides of the individual memory-block regions in the one first tier and comprises a different composition from that of the conducting material. Other embodiments, including structure independent of method, are disclosed.

Abstract: A source-level sacrificial layer and an alternating stack of insulating layers and spacer material layers are formed over a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack and the source-level sacrificial layer, and memory opening fill structures are formed. A source cavity is formed by removing the source-level sacrificial layer, and exposing an outer sidewall of each vertical semiconductor channel in the memory opening fill structures. A metal-containing layer is deposited on physically exposed surfaces of the vertical semiconductor channel and the vertical semiconductor channel is crystallized using metal-induced lateral crystallization. Alternatively or additionally, cylindrical metal-semiconductor alloy regions can be formed around the vertical semiconductor channels to reduce contact resistance. A source contact layer can be formed in the source cavity.

Abstract: Embodiments herein are directed to methods and devices having a stress memorization layer along a side of a substrate. In some embodiments, a method may include providing a substrate having a first main side opposite a second main side, implanting the second main side of the substrate to form an amorphous implant area, forming a stress liner over the second main side of the substrate, and annealing the stress liner to form a stress memorization layer in the amorphous implant area.

Abstract: In an embodiment, there is provided a display substrate assembly. The display substrate assembly includes: a base substrate; a light-shielding layer on the base substrate, the light-shielding layer having a plurality of light-shielding elements; and a plurality of polysilicon layers respectively on sides of the plurality of light-shielding elements away from the base substrate; wherein the plurality of light-shielding elements have different sizes such that energy lights reflected and/or refracted through the plurality of light-shielding elements of different sizes respectively generate different thermal energy distributions on the plurality of polysilicon layers corresponding to the plurality of light-shielding elements, causing the plurality of polysilicon layers to have different crystal forms. Meanwhile, a method of manufacturing the display substrate assembly and a display apparatus including the aforementioned display substrate assembly are also provided.

Abstract: A metal is formed into an opening that is located in an interlayer dielectric (ILD) material that laterally surrounds a semiconductor fin of a partially fabricated vertical transistor and on a physically exposed topmost surface of the semiconductor fin. A patterned material stack of, and from bottom to top, a membrane and a doped amorphous semiconductor material layer is formed on the metal and a topmost surface of the ILD material. A metal induced layer exchange anneal is then employed in which the metal and doped semiconductor material change places such that the doped semiconductor material is in direct contact with the topmost surface of the semiconductor fin. The exchanged doped semiconductor material, which provides a top source/drain structure of the vertical transistor, may have a different crystalline orientation than the topmost surface of the semiconductor fin.

Abstract: Provided are an array substrate, a manufacturing method thereof, and a display panel. The array substrate includes: a substrate, a first active layer of a first thin film transistor, a first insulating layer, a first metal layer, and a second active layer of a second thin film transistor. The first metal layer includes a first connection portion, which overlaps one of a source contact region or a drain contact region of the first active layer and overlaps one of a source contact region or a drain contact region of the second active layer. The one of the source contact region or the drain contact region of the first active layer and the one of the source contact region or the drain contact region of the second active layer overlap each other, and are electrically connected through a via in the first insulating layer and the first connection portion.

Abstract: A semiconductor structure and fabrication method thereof are provided. The fabrication method includes: providing a base substrate including a substrate and a plurality of fins on the substrate; forming gate structures across the fins, to cover a portion of sidewalls of the fins and a portion of top surfaces of the fins; forming stress layers in the fins on sides of each gate structure; forming barrier layers on sidewalls of the gate structure; and forming doped regions by applying first ion implantation processes to the fins under the stress layers using the barrier layers as a mask.

Abstract: A method of preparing a package structure is provided, which includes providing a carrier plate including a supporting layer, a first release layer, and a first metal layer; forming a first dielectric layer over the first metal layer, the first dielectric layer having a plurality of holes, each of the holes having an end portion substantially coplanar with each other at a same plane; forming a plurality of conductive protrusions filling the holes, each of the conductive protrusions having a first end and a second end opposite thereto; forming a circuit layer structure including at least one circuit layer and at least one second dielectric layer, the circuit layer being connected to the second end, the second dielectric layer being disposed over the circuit layer; removing the carrier plate; and removing a portion of the first dielectric layer to expose the conductive protrusions. A package structure is also provided.

Abstract: A self-capacitance touch screen. In some examples, the touch screen comprises a plurality of display pixels, a first display pixel of the plurality of display pixels including a first touch electrode of a plurality of touch electrodes, and a gate line coupled to the first display pixel, wherein the gate line is configured such that a voltage at the gate line substantially follows a voltage at the first touch electrode. In some examples, the gate line is coupled to a resistor, the resistor being configured to decouple the gate line from ground. In some examples, the gate line is coupled to an AC voltage source.

Abstract: Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate comprising a trap-rich layer with small grain sizes, as well as the resulting SOI substrate. In some embodiments, an amorphous silicon layer is deposited on a high-resistivity substrate. A rapid thermal anneal (RTA) is performed to crystallize the amorphous silicon layer into a trap-rich layer of polysilicon in which a majority of grains are equiaxed. An insulating layer is formed over the trap-rich layer. A device layer is formed over the insulating layer and comprises a semiconductor material. Equiaxed grains are smaller than other grains (e.g., columnar grains). Since a majority of grains in the trap-rich layer are equiaxed, the trap-rich layer has a high grain boundary area and a high density of carrier traps. The high density of carrier traps may, for example, reduce the effects of parasitic surface conduction (PSC).

Abstract: The semiconductor device includes: an epitaxial layer of a first conductivity type formed on a first principal surface of a semiconductor substrate; a first semiconductor region of the first conductivity type formed from an outermost surface to an inner portion of the epitaxial layer; and a third semiconductor region of a second conductivity type formed from a bottom surface of the first semiconductor region to an inner portion of the semiconductor substrate. The method includes: (a) polishing a second principal surface opposite to the first principal surface of the semiconductor substrate above which at least a source region, a drain region, and a gate electrode are formed to thin the substrate; and (b) ion-implanting impurities of the second conductivity type from the second principal surface of the polished semiconductor substrate to form the third semiconductor region.

Abstract: A semiconductor device that includes at least one germanium containing fin structure having a length along a <100> direction and a sidewall orientated along the (100) plane. The semiconductor device also includes at least one germanium free fin structure having a length along a <100> direction and a sidewall orientated along the (100) plane. A gate structure is present on a channel region of each of the germanium containing fin structure and the germanium free fin structure. N-type epitaxial semiconductor material having a square geometry present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium free fin structures. P-type epitaxial semiconductor material having a square geometry is present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium containing fin structures.

Abstract: Methods for controlled microstructure creation utilize seeding of amorphous layers prior to annealing. Seed crystals are formed on an amorphous layer or layers. The material, size, and spacing of the seed crystals may be varied, and multiple seed layers and/or amorphous layers may be utilized. Thereafter, the resulting assembly is annealed to generate a crystalline microstructure. Via use of these methods, devices having desirable microstructural properties are enabled.

Abstract: An array substrate and a fabrication method thereof and a display panel are provided. The array substrate including a first thin film transistor and a second thin film transistor. The fabrication method including: forming an amorphous silicon thin film on a base substrate; forming a laser blocking layer on the amorphous silicon thin, film; irradiating, by laser, the amorphous silicon thin film with the laser blocking layer formed thereon, to transform the amorphous silicon thin film into a crystalline silicon thin film; and patterning the crystalline silicon thin film to form a first active region pattern of the first thin film transistor and a second active region pattern of the second thin film transistor, wherein, as to a same type of carrier, a mobility of the first active region pattern is substantially smaller than a mobility of the second active region pattern.

Abstract: According to one or more embodiments of the present invention, a method for forming a fin structure for a semiconductor device includes forming a fin. The method further includes recessing a first portion of the fin to form a recess in the fin. The method further includes forming a channel region in the first portion of the fin. The method further includes forming an extension region on a second portion of the fin, and wherein defects are collected within the extension regions from the channel region in the first portion of the fin.

Abstract: Methods for controlled microstructure creation utilize seeding of amorphous layers prior to annealing. Seed crystals are formed on an amorphous layer or layers. The material, size, and spacing of the seed crystals may be varied, and multiple seed layers and/or amorphous layers may be utilized. Thereafter, the resulting assembly is annealed to generate a crystalline microstructure. Via use of these methods, devices having desirable microstructural properties are enabled.

Abstract: A method of manufacturing a fractal-edge thin film includes determining an area shape to be covered by the fractal-edge thin film. The method also includes generating a thin-film perimeter based upon the area shape, the thin-film perimeter having a fractal dimension exceeding one. The method also includes determining a photomask perimeter such that a photomask with the photomask perimeter, when used in a photolithography process, yields a fractal-edge thin film with the thin-film perimeter. The method may also include photolithographically etching a thin-film, the thin film having a photoresist layer disposed thereon, the photoresist layer having been exposed through the photomask, wherein the etching results in the fractal-edge thin film.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a first passivation layer over the substrate; a second passivation layer over the first passivation layer; a magnetic layer in the second passivation layer; and an etch stop layer between the magnetic layer and the first passivation layer, wherein the etch stop layer includes at least one acid resistant layer, and the acid resistant layer includes a metal oxide. A method for manufacturing a semiconductor structure is also disclosed.

Abstract: This invention is in the field of physical chemistry and relates to novel hyperuniform and nearly hyperuniform random network materials and methods of making said materials. Methods are described for controlling or altering the band gap of a material, and in particular commercially useful materials such as amorphous silicon. These methods can be exploited in the design of semiconductors, transistors, diodes, solar cells and the like.

Abstract: A method for forming polysilicon on a semiconductor substrate that include providing amorphous silicon on a semiconductor substrate, exposing at least an area of the amorphous silicon to a first laser beam and a second laser beam, characterized in that during exposing the area to the second laser beam no displacement of the laser beam relative to the area occurs. In addition, the use of such method for producing large grain polysilicon. In particular, the use of such method for producing vertical grain polysilicon. Further, the use of such method for producing sensors, MEMS, NEMS, Non Volatile Memory, Volatile memory, NAND Flash, DRAM, Poly Si contacts and interconnects.

Abstract: A semiconductor device includes a second channel layer in a first column and a second channel layer in a second column disposed biased to one side of a first channel layer in a first column and a first channel layer in a second column, respectively. The one side of the first channel layer in the first column and the one side of the first channel layer in the second column face directions opposite to each other.

Abstract: A method and structure for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate and a work-function metal layer is deposited over the gate dielectric layer. Thereafter, a fluorine-based treatment of the work-function metal layer is performed, where the fluorine-based treatment removes an oxidized layer from a top surface of the work-function metal layer to form a treated work-function metal layer. In some embodiments, after performing the fluorine-based treatment, another metal layer is deposited over the treated work-function metal layer.

Abstract: The present invention generally relates to nanoscale wires and tissue engineering. Systems and methods are provided in various embodiments for preparing cell scaffolds that can be used for growing cells or tissues, where the cell scaffolds comprise nanoscale wires. In some cases, the nanoscale wires can be connected to electronic circuits extending externally of the cell scaffold. Such cell scaffolds can be used to grow cells or tissues which can be determined and/or controlled at very high resolutions, due to the presence of the nanoscale wires, and such cell scaffolds will find use in a wide variety of novel applications, including applications in tissue engineering, prosthetics, pacemakers, implants, or the like. This approach thus allows for the creation of fundamentally new types of functionalized cells and tissues, due to the high degree of electronic control offered by the nanoscale wires and electronic circuits.

Abstract: Disclosed is a process for producing silicon nanowires having a diameter or thickness less than 100 nm, comprising: (A) preparing a solid silicon source material in a particulate form having a size from 0.2 ?m to 20 ?m or in a porous structure form having a specific surface area greater than 50 m2/g; (B) depositing a catalytic metal, in the form of nano particles having a size from 0.5 nm to 100 nm or a coating having a thickness from 1 nm to 100 nm, onto surfaces of the silicon source material to form a catalyst metal-coated silicon material; and (C) exposing the catalyst metal-coated silicon material to a high temperature environment, from 300° C. to 2,000° C., for a period of time sufficient to enable a catalytic metal-catalyzed growth of multiple silicon nanowires from the silicon source material.

Abstract: The invention provides a method for forming a surface oxide layer on an amorphous silicon including steps: using a HF acid to clean a surface of the amorphous silicon; using a water to clean the surface of the amorphous silicon being cleaned by the HF acid; drying the surface of the amorphous silicon after being cleaned by the water; using an extreme ultraviolet lithography to form a first oxide layer on the surface of the amorphous silicon after being dried; using an oxidizing solution to clean the surface of the amorphous silicon with the first oxide layer to thereby form a second oxide layer; and drying the surface of the amorphous silicon with the second oxide layer. By using the extreme ultraviolet lithography to form the first oxide layer, the surface of the amorphous silicon is given with strong hydrophilicity and therefore the distribution of water would be uniform.

Abstract: A method of manufacturing a semiconductor device using a metal oxide includes forming a metal oxide layer on a substrate, forming an amorphous semiconductor layer on the metal oxide layer, and forming a polycrystalline semiconductor layer by crystallizing the amorphous semiconductor layer using the metal oxide layer.

Abstract: The present invention relates to a diblock copolymer that may facilitate formation of a finer nano pattern, and be used for manufacture of an electronic device including a nano pattern or a bio sensor, and the like, a method for preparing the same, and a method for forming a nano pattern using the same, The diblock copolymer comprises a hard segment including at least one specific acrylamide-based repeat unit, and a soft segment including at least one (meth)acrylate-based repeat unit.

Abstract: Provided is a method of forming a silicon film in a groove formed on a surface of an object to be processed, which includes: forming a first silicon layer on the surface of the object to be processed to embed the groove; doping impurities near a surface of the first silicon layer; forming a seed layer on the doped first silicon layer; and forming a second silicon layer containing impurities on the seed layer.

Abstract: In various embodiments, a method for processing a carrier is provided. The method for processing a carrier may include: forming a first catalytic metal layer over a carrier; forming a source layer over the first catalytic metal layer; forming a second catalytic metal layer over the source layer, wherein the thickness of the second catalytic metal layer is larger than the thickness of the first catalytic metal layer; and subsequently performing an anneal to enable diffusion of the material of the source layer forming an interface layer adjacent to the surface of the carrier from the diffused material of the source layer.

Abstract: The present invention provides a polysilicon thin-film transistor array substrate and a method for preparing the same, and a display device, wherein the method comprises a step of forming a gate electrode, a gate insulating layer, a semiconductor layer, a source electrode and a drain electrode of the polysilicon thin-film transistor, and a first electrode and a second electrode of a storage capacitor, and a gate line and a data line, wherein, the semiconductor layer and the first electrode of the storage capacitor are formed via a one-time patterning process, and the gate electrode, the gate line and the second electrode of the storage capacitor are formed via a one-time patterning process. By the solution of the invention, the number of mask plates used can be lowered, so that the process can be simplified, and the production cost can be lowered.

Abstract: There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 ?m or more.

Abstract: A phase-change memory device with an improved current characteristic is provided. The phase-change memory device includes a metal word line, a semiconductor layer of a first conductivity type being in contact with the metal word line, and an auxiliary diode layer being in contact with metal word line and the semiconductor layer.

Abstract: Disposable gate structures and a planarization dielectric layer are formed over doped semiconductor material portions on a crystalline insulator layer. Gate cavities are formed by removing the disposable gate structures selective to the planarization dielectric layer. Doped semiconductor material portions are removed from underneath the gate cavities to provide pairs of source and drain regions separated by a gate cavity. Within a first gate cavity, a faceted crystalline dielectric material portion is grown from a physically exposed surface of the crystalline insulator layer, while a second gate is temporarily coated with an amorphous material layer. A contoured semiconductor region is epitaxially grown on the faceted crystalline dielectric material portion in the first gate cavity, while a planar semiconductor region is epitaxially grown in the second gate cavity. The semiconductor regions can provide at least one contoured channel region and at least one planar channel region.

Abstract: A pulsed-laser anneal technique includes performing an implant of a selected region of a semiconductor wafer. A co-constituent implant of the selected region is performed, and the pulsed-laser anneal of the selected region performed. A pre-amorphizing implant of the selected region can also be performed. In one embodiment, the implant of the selected region is performed as an insitu implant. In another embodiment, the co-constituent implant is performed as an insitu non-donor implant. In yet another embodiment, the implant and the co-constituent implant of the selected region are performed as an insitu donor and co-constituent implant.

Abstract: The present disclosure disclosed a method of forming the buffer layer in the LTPS products. The method comprises the following steps: heating the substrate to make the alkali metal ions diffuse to the surface of the glass; washing the substrate by acid to remove the alkali metal ions on the surface of the glass; forming the buffer layer on the glass which has been heated and washed by acid, wherein the material of the buffer layer is SiOx. The method of the present disclosure based on the design of the single buffer layer, it can greatly promote the capacity and can economize the gas. Furthermore, it can avoid the cross contamination of the different layers so as to promote characteristic of the element.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device. The method includes introducing an inert gas and a material gas into a predetermined space, applying a voltage to generate plasma in the space after introducing the inert gas and the material gas so as to form a semiconductor layer on a substrate, introducing an oxidation-reduction gas in the predetermined space after the voltage is applied, and stopping the introduction of the material gas, the inert gas, and the oxidation-reduction gas after the voltage is applied.

Abstract: A method of forming nanowire devices. The method includes forming a stressor layer circumferentially surrounding a semiconductor nanowire. The method is performed such that, due to the stressor layer, the nanowire is subjected to at least one of radial and longitudinal strain to enhance carrier mobility in the nanowire. Radial and longitudinal strain components can be used separately or together and can each be made tensile or compressive, allowing formulation of desired strain characteristics for enhanced conductivity in the nanowire of a given device.

Abstract: An embodiment is a method. A first III-V compound semiconductor is epitaxially grown in a trench on a substrate, and the epitaxial growth is performed in a chamber. The first III-V compound semiconductor has a first surface comprising a facet. After the epitaxial growth, the first surface of the first III-V compound semiconductor is etched to form an altered surface of the first III-V compound semiconductor. Etching the first surface is performed in the chamber in situ. A second III-V compound semiconductor is epitaxially grown on the altered surface of the first III-V compound semiconductor. The epitaxial growth of the first III-V compound semiconductor may be performed in a MOCVD chamber, and the etch may use an HCl gas. Structures resulting from methods are also disclosed.

Abstract: According to one embodiment, a manufacturing method of a semiconductor device includes forming a crystal film on a semiconductor substrate by irradiating the semiconductor substrate with a first microwave, obtained by providing frequency modulation or phase modulation of a first carrier wave which is a sine wave with a first frequency, using a first signal wave which is a sine wave or a pulse wave with a third frequency lower than a first frequency, and irradiating the semiconductor substrate with a second microwave, obtained by providing frequency modulation or phase modulation of a second carrier wave, which is a sine wave with a second frequency higher than the first frequency, using a second signal wave which is a sine wave or a pulse wave with a fourth frequency lower than the second frequency.

Abstract: Collections of laterally crystallized semiconductor islands for use in thin film transistors and systems and methods for making same are described. A display device includes a plurality of thin film transistors (TFTs) on a substrate, such that the TFTs are spaced apart from each other and each include a channel region that has a crystalline microstructure and a direction along which a channel current flows. The channel region of each of the TFTs contains a crystallographic grain that spans the length of that channel region along its channel direction. Each crystallographic grain in the channel region of each of the TFTs is physically disconnected from and crystallographically uncorrelated with each crystallographic grain in the channel region of each adjacent TFT.

Abstract: In one embodiment a method of forming a compressive polycrystalline semiconductive material layer is disclosed. The method comprises forming a polycrystalline semiconductive seed layer over a substrate and forming a silicon layer by depositing silicon directly on the polycrystalline silicon seed layer under amorphous process conditions at a temperature below 600 C.

Abstract: A semiconductor structure includes a substrate and first and second crystalline semiconductor layers. The first crystalline semiconductor layer has a first crystal orientation, and includes a crystallized amorphous region formed on the substrate. The second crystalline semiconductor layer is formed on the substrate, is laterally disposed of the first crystalline semiconductor layer, and has a second crystal orientation different from the first crystal orientation. A method of fabricating the semiconductor structure is also disclosed.

Abstract: In a method, a gate dielectric film is formed on a semiconductor substrate. A gate electrode is formed on the gate dielectric film. Impurities of a first conduction-type are introduced into a drain-layer formation region. The impurities of the first conduction-type in the drain-layer formation region are activated by performing heat treatment. Single crystals of the semiconductor substrate in a source-layer formation region are amorphized by introducing inert impurities into the source-layer formation region. Impurities of a second conduction-type is introduced into the source-layer formation region. At least an amorphous semiconductor in the source-layer formation region is brought into a single crystal semiconductor and the impurities of the second conduction-type in the source-layer formation region is activated by irradiating the semiconductor substrate with microwaves.

Abstract: A method of forming an epitaxial layer includes forming a plurality of first insulation patterns in a substrate, the plurality of first insulation patterns spaced apart from each other, forming first epitaxial patterns on the plurality of first insulation patterns, forming second insulation patterns between the plurality of first insulation patterns to contact the plurality of first insulation patterns, and forming second epitaxial patterns on the second insulation patterns and between the first epitaxial patterns to contact the first epitaxial patterns, the first epitaxial patterns and the second epitaxial patterns forming a single epitaxial layer.

Abstract: A thin-film transistor comprises a semiconductor panel, a dielectric layer, a semiconductor film layer, a conduct layer, a source and a drain. The semiconductor panel comprises a base, an intra-dielectric layer, at least one metal wire layer and at least one via layer. The dielectric layer is stacked on the semiconductor panel. The semiconductor film layer is stacked on the dielectric layer. The conduct layer is formed on the semiconductor film layer. The source is formed on the via of the vias that is adjacent to and connects to the gate via. The drain is formed on another via of the vias that is adjacent to and connects to the gate via. A fabricating method for a thin-film transistor with metal-gates and nano-wires is also disclosed.

Abstract: A semiconductor device using an oxide semiconductor is provided with stable electric characteristics to improve the reliability. In a manufacturing process of a transistor including an oxide semiconductor film, an oxide semiconductor film containing a crystal having a c-axis which is substantially perpendicular to a top surface thereof (also called a first crystalline oxide semiconductor film) is formed; oxygen is added to the oxide semiconductor film to amorphize at least part of the oxide semiconductor film, so that an amorphous oxide semiconductor film containing an excess of oxygen is formed; an aluminum oxide film is formed over the amorphous oxide semiconductor film; and heat treatment is performed thereon to crystallize at least part of the amorphous oxide semiconductor film, so that an oxide semiconductor film containing a crystal having a c-axis which is substantially perpendicular to a top surface thereof (also called a second crystalline oxide semiconductor film) is formed.

Abstract: Method for making thin crystalline or polycrystalline layers. The method includes electrochemically etching a crystalline silicon template to form a porous double layer thereon, the double layer including a highly porous deeper layer and a less porous shallower layer. The shallower layer is irradiated with a short laser pulse selected to recrystallize the shallower layer resulting in a crystalline layer. Silicon is deposited on the recrystallized shallower layer and the silicon is irradiated with a short laser pulse selected to crystalize the silicon leaving a layer of crystallized silicon on the template. Thereafter, the layer of crystallized silicon is separated from the template. The process of the invention can be used to make optoelectronic devices.

Abstract: At least first and second Si1-xGex (0?x?1) layers are formed on an insulating film. At least first and second material layers are formed correspondingly to the at least first and second Si1-xGex (0?x?1) layers. A lattice constant of the first Si1-xGex (0?x?1) layer is matched with a lattice constant of the first material layer. A lattice constant of the second Si1-xGex (0?x?1) layer is matched with a lattice constant of the second material layer.

Abstract: An embodiment of the present invention relates to a low temperature polysilicon thin film and a manufacturing method thereof. The manufacturing method comprises: forming a buffer layer on a substrate (S11); forming a seed layer comprising a plurality of uniformly distributed crystal nuclei on the buffer layer by using a patterning process (S12); forming an amorphous silicon layer on the seed layer (S13); and performing an excimer laser annealing process on the amorphous silicon layer (S14).

Abstract: Methods of fabricating a vertical cell semiconductor device including forming a hole passing through a stacked structure of alternating insulating and sacrificial layers on a substrate, forming an amorphous silicon layer conforming to an inner wall of the hole, forming a silicon region on the amorphous silicon layer, and metal induced crystallizing the amorphous silicon layer via the silicon region to form a single-crystalline channel structure in the hole.