Utilizing Wave Energy (e.g., Laser, Electron Beam, Etc.) Patents (Class 438/487)
  • Patent number: 10573550
    Abstract: A method is provided for preparing a semiconductor-on-insulator structure comprising a silicon oxynitride layer having a gradient oxygen concentration.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: February 25, 2020
    Assignee: GlobalWafers Co., Ltd.
    Inventor: Sasha Joseph Kweskin
  • Patent number: 10522353
    Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Chin Chen, Cheng-Yi Wu, Yu-Hung Cheng, Ren-Hua Guo, Hsiang Liu, Chin-Szu Lee
  • Patent number: 10418586
    Abstract: It is an object to provide a flexible light-emitting device with high reliability in a simple way. Further, it is an object to provide an electronic device or a lighting device each mounted with the light-emitting device. A light-emitting device with high reliability can be obtained with the use of a light-emitting device having the following structure: an element portion including a light-emitting element is interposed between a substrate having flexibility and a light-transmitting property with respect to visible light and a metal substrate; and insulating layers provided over and under the element portion are in contact with each other in the outer periphery of the element portion to seal the element portion. Further, by mounting an electronic device or a lighting device with a light-emitting device having such a structure, an electronic device or a lighting device with high reliability can be obtained.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: September 17, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kaoru Hatano, Masahiro Katayama, Shingo Eguchi, Yoshiaki Oikawa, Ami Nakamura
  • Patent number: 10388875
    Abstract: A method for manufacturing a flexible semiconductor device is disclosed. The method includes: forming a separation layer of a metal over a substrate; treating the separation layer with plasma under an atmosphere containing nitrogen, oxygen, silicon, and hydrogen; forming a layer over the plasma-treated separation layer, the layer being capable of supplying hydrogen and nitrogen to the separation layer; forming a functional layer over the separation layer; performing heat treatment to promote the release of hydrogen and nitrogen from the layer; and separating the substrate at the separation layer. The method allows the formation of an extremely thin oxide layer over the separation layer, which facilitates the separation, reduces the probability that the oxide layer remains under the layer, and contributes to the increase in efficiency of a device included in the functional layer.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: August 20, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Seiji Yasumoto, Masataka Sato, Masafumi Nomura, Toshiyuki Miyamoto
  • Patent number: 10355033
    Abstract: The present disclosure discloses a manufacturing method of a polycrystalline silicon thin film, which includes: forming a first amorphous silicon thin film; crystallizing the first amorphous silicon thin film to form a polycrystalline silicon thin film by applying an excimer laser annealing process; forming a second amorphous silicon thin film on a first surface of the polycrystalline silicon thin film; and etching until the second amorphous silicon thin film is completely removed toward a direction of the polycrystalline silicon thin film from the second amorphous silicon thin film by applying a dry etching process. The present disclosure further discloses a manufacturing method of a thin film transistor array substrate which includes the steps of manufacturing an active layer: forming a layer of a polycrystalline silicon thin film according to the previous polycrystalline silicon thin film; and etching the polycrystalline silicon thin film to form a patterned active layer.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: July 16, 2019
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Leilei Dong
  • Patent number: 10312080
    Abstract: The present invention provides a method for forming an amorphous silicon multiple layer structure, the method comprises the flowing steps: first, a substrate material layer is provided, next, a first amorphous silicon layer is formed on the substrate material layer, wherein the first amorphous silicon layer includes a plurality of hydrogen atoms disposed therein, afterwards, an UV curing process is performed to the first amorphous silicon layer, so as to remove the hydrogen atoms from the first amorphous silicon layer, finally, a second amorphous silicon layer is formed on the first amorphous silicon layer.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: June 4, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Mei-Ling Chen, Wei-Hsin Liu, Yi-Wei Chen, Ching-Hsiang Chang, Jui-Min Lee, Chia-Lung Chang, Tzu-Chin Wu, Shih-Fang Tzou
  • Patent number: 10262873
    Abstract: Preheat processes for a millisecond anneal system are provided. In one example implementation, a heat treatment process can include receiving a substrate on a wafer support in a processing chamber of a millisecond anneal system; heating the substrate to an intermediate temperature; and heating the substrate using a millisecond heating flash. Prior to heating the substrate to the intermediate temperature, the process can include heating the substrate to a pre-bake temperature for a soak period.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: April 16, 2019
    Assignee: Mattson Technology, Inc.
    Inventor: Paul Timans
  • Patent number: 10048579
    Abstract: The disclosure is related to a photo-alignment method, comprising the following steps. A top panel and a bottom panel each with an alignment film are provided; a mask plate for shielding the top panel and the bottom panel is provided, and a transparent section of the mask plate is disposed; an ultraviolet is emitted along a first incident direction by the mask plate for exposing the alignment film of the top panel and the bottom panel; the transparent section of the mask plate is adjusted, an ultraviolet is emitted along a second incident direction by the mask plate for exposing the alignment film of the top panel and the bottom panel. The manufacture of the alignment film in the whole liquid crystal display device can be accomplished by a mask plate undergoing exposure twice, so that the exposure times decrease and the process is simplified.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: August 14, 2018
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Jie Sun
  • Patent number: 9893077
    Abstract: A memory device, including a first memory region including a first substrate, a plurality of first semiconductor devices on the first substrate, and a first interlayer insulating layer covering the plurality of first semiconductor devices; and a second memory region including a second substrate on the first interlayer insulating layer and a plurality of second semiconductor devices on the second substrate, the second substrate including a first region in a plurality of grooves in the first interlayer insulating layer and a second region including grains extending from the first region, the second region being on an upper surface of the first interlayer insulating layer.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: February 13, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Phil Ouk Nam, Yong Hoon Son, Kyung Hyun Kim, Byeong Ju Kim, Kwang Chul Park, Yeon Sil Sohn, Jin I Lee, Jong Heun Lim, Won Bong Jung
  • Patent number: 9735040
    Abstract: A method of dividing a single-crystal substrate along a plurality of preset division lines, includes a shield tunnel forming step of applying a pulsed laser beam having such a wavelength that permeates through the substrate along the division lines to form shield tunnels, each including a fine hole and an amorphous region shielding the fine hole, a protective member adhering step of adhering a protective member to the substrate before or after the shield tunnel forming step, and a grinding step of holding the protective member on the substrate, to which the shield tunnel forming step and the protective member adhering step are performed, on a chuck table of a grinding apparatus, grinding a reverse surface of the substrate to bring the substrate to a predetermined thickness, and dividing the substrate along the division lines along which the shield tunnels have been formed.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: August 15, 2017
    Assignee: Disco Corporation
    Inventors: Hiroshi Morikazu, Noboru Takeda, Takumi Shotokuji
  • Patent number: 9644270
    Abstract: An oxide semiconductor depositing apparatus includes a heating chamber which is configured to heat and plasma-treat a first substrate including an insulation layer, and includes a chamber body, a heater disposed in the chamber body which is configured to heat the first substrate, and a cathode plate spaced apart from the heater, a high frequency voltage applied to the cathode plate, and a first process chamber which is configured to provide an oxide semiconductor layer on the insulation layer of the first substrate.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: May 9, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Katsushi Kishimoto, Yeon-Keon Moon, Sang-Woo Sohn, Takayuki Fukasawa, Sang-Won Shin
  • Patent number: 9466754
    Abstract: A solar cell can include a silicon layer formed over a silicon substrate. The silicon layer can have a P-type doped region and an N-type doped region. Portions of the silicon layer can have a grain size larger than other portions of the silicon layer. For example, larger grains of the silicon layer formed within a depletion region between P-type and N-type doped regions can minimize recombination loss at the P-type and N-type doped region boundaries and improve solar cell efficiency.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: October 11, 2016
    Assignee: SunPower Corporation
    Inventor: Taeseok Kim
  • Patent number: 9337342
    Abstract: In a semiconductor device including an oxide semiconductor, the amount of oxygen vacancies is reduced. Moreover, electrical characteristics of a semiconductor device including an oxide semiconductor are improved. The semiconductor device includes a transistor including a gate electrode over a substrate, a gate insulating film covering the gate electrode, an oxide semiconductor film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the oxide semiconductor film; and over the transistor, a first insulating film covering the gate insulating film, the oxide semiconductor film, and the pair of electrodes; and a second insulating film covering the first insulating film. An etching rate of the first insulating film is lower than or equal to 10 nm/min and lower than an etching rate of the second insulating film when etching is performed at 25° C. with 0.5 weight % of hydrofluoric acid.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 10, 2016
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kenichi Okazaki, Toshiyuki Miyamoto, Masafumi Nomura, Takashi Hamochi, Shunpei Yamazaki, Toshinari Sasaki
  • Patent number: 9245757
    Abstract: Provided is a laser annealing treatment including a laser light source that outputs pulse laser light, an optical system that shapes the pulse laser light, and leads the shaped pulse laser light to a semiconductor film subject to treatment, and a stage that carries the semiconductor film to be irradiated by the pulse laser light, wherein the pulse laser light irradiating the semiconductor film presents a rising time equal to or less than 35 nanoseconds from 10% of the maximum height to the maximum height in the pulse energy density, and a falling time equal to or more than 80 nanoseconds from the maximum height to 10% of the maximum height, thereby increasing, while an energy density suitable for crystallization and the like is not particularly increased, a margin quantity thereof, and carrying out high quality annealing treatment without decreasing a throughput.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: January 26, 2016
    Assignee: The Japan Steel Works, Ltd
    Inventors: Junichi Shida, Suk-Hwan Chung, Masashi Machida
  • Patent number: 9239484
    Abstract: A thin film transistor substrate (20a) includes an insulating substrate (10a), a semiconductor layer (13a) provided on the insulating substrate (10a) and having a channel region (C), and a channel protection layer (25) provided in the channel region (C). The channel protection layer (25) is made of a multilayer film in which first insulating films and second insulating films are alternately layered. A relationship between a refractive index Ra of the first insulating film and a refractive index Rb of the second insulating film is Rb/Ra?1.3.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: January 19, 2016
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Tokuaki Kuniyoshi
  • Patent number: 9224783
    Abstract: Defects in hydrogenated amorphous silicon are reduced by low-energy ion treatments and optional annealing. The treatments leave strongly-bonded hydrogen and other passivants in place, but increase the mobility of loosely-bonded and interstitially trapped hydrogen that would otherwise form unwanted two-level systems (TLS). The mobilized hydrogen atoms may be attracted to unused passivation sites or recombined into H2 gas and diffuse out of the deposited layer. The treatments also increase the density of the material. The optional anneal may partially crystallize the layer, further densify the layer, or both. The reduced number of defects and the increased crystallinity reduce the loss tangent of amorphous silicon dielectrics for superconducting microwave devices.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: December 29, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Frank Greer, Andy Steinbach, Wenxian Zhu
  • Patent number: 9214409
    Abstract: Provided is a semiconductor device. The semiconductor device includes a conductive pattern disposed on a semiconductor substrate. First and second conductive lines disposed on the conductive pattern and located at the same level as each other, are provided. An isolation pattern is disposed between the first and second conductive lines. A first vertical structure passing through the first conductive line and conductive pattern is provided. A second vertical structure passing through the second conductive line and conductive patterns is provided. An auxiliary pattern passing through the conductive pattern and in contact with the isolation pattern is provided.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: December 15, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Hyuk Yoo, Dae-Hyun Jang, Yoo-Chul Kong, Kyoung-Sub Shin
  • Patent number: 9159866
    Abstract: A photo sensor, a method of manufacturing the photo sensor, and a display apparatus, the photo sensor including a substrate; a light receiving unit on the substrate, the light receiving unit including an amorphous semiconductor material; a first adjacent unit and a second adjacent unit formed as one body with the light receiving unit, the first adjacent unit and the second adjacent unit being separated from each other by the light receiving unit; a first photo sensor electrode electrically connected to the first adjacent unit; and a second photo sensor electrode electrically connected to the second adjacent unit, wherein at least one of the first adjacent unit and the second adjacent unit includes a crystalline semiconductor material.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: October 13, 2015
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Won-Kyu Lee, Jae-Hwan Oh, Seong-Hyun Jin, Young-Jin Chang, Jae-Beom Choi
  • Patent number: 9086375
    Abstract: A laser source (10) for emitting an output beam (12) along an output axis (12A) includes (i) a first laser module (16) that generates a first beam (16A); (ii) a second laser module (18) that generates a second beam (18A); (iii) a beam selector assembly (32); (iv) a first director assembly (24) that directs the first beam (16A) at the beam selector assembly (32); (v) a second director assembly (26) that directs the second beam (18A) at the beam selector assembly (32); and (vii) a control system (34) that directs power to the modules (16), (18). The beam selector assembly (32) moves between a first position in which the first beam (16A) is directed along the output axis (12A), and a second position in which the second beam (18A) is directed along the output axis (12A).
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: July 21, 2015
    Assignee: DAYLIGHT SOLUTIONS, INC.
    Inventors: J. Allen Priest, Santino Marrone, David Caffey, David Arnone, Michael Pushkarsky
  • Patent number: 9040345
    Abstract: A method of laser ablation for electrical contact to a buried electrically conducting layer in diamond comprising polishing a single crystal diamond substrate having a first carbon surface, implanting the diamond with a beam of 180 KeV followed by 150 KeV C+ ions at fluencies of 4×1015 ions/cm2 and 5×1015 ions/cm2 respectively, forming an electrically conducting carbon layer beneath the first carbon surface, and ablating the single crystal diamond which lies between the electrically conducting layer and the first carbon surface.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: May 26, 2015
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Bradford B. Pate, Matthew P. Ray, Jeffrey W. Baldwin
  • Publication number: 20150137133
    Abstract: A method of forming a heavily-doped silicon layer on a more lightly-doped silicon substrate including the steps of depositing a heavily-doped amorphous silicon layer; depositing a silicon nitride layer; and heating the amorphous silicon layer to a temperature higher than or equal to the melting temperature of silicon.
    Type: Application
    Filed: November 11, 2014
    Publication date: May 21, 2015
    Applicants: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Michel Marty, Francois Roy
  • Publication number: 20150140794
    Abstract: According to one embodiment, provided is a polycrystallization method for polycrystallizing an amorphous semiconductor film that has a natural oxide film on the surface . The polycrystallization method includes a step of cleaning the natural oxide film while leaving the natural oxide film on the surface of the amorphous semiconductor film, and a step of polycrystallizing the amorphous semiconductor film in the state where the natural oxide film is left.
    Type: Application
    Filed: November 13, 2014
    Publication date: May 21, 2015
    Applicant: Japan Display Inc.
    Inventors: Naoya ITO, Toshihide Jinnai, Hirofumi Mizukoshi
  • Patent number: 9029247
    Abstract: According to one embodiment, a manufacturing method of a semiconductor device includes forming a crystal film on a semiconductor substrate by irradiating the semiconductor substrate with a first microwave, obtained by providing frequency modulation or phase modulation of a first carrier wave which is a sine wave with a first frequency, using a first signal wave which is a sine wave or a pulse wave with a third frequency lower than a first frequency, and irradiating the semiconductor substrate with a second microwave, obtained by providing frequency modulation or phase modulation of a second carrier wave, which is a sine wave with a second frequency higher than the first frequency, using a second signal wave which is a sine wave or a pulse wave with a fourth frequency lower than the second frequency.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: May 12, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kyoichi Suguro
  • Patent number: 9012295
    Abstract: In one embodiment a method of forming a compressive polycrystalline semiconductive material layer is disclosed. The method comprises forming a polycrystalline semiconductive seed layer over a substrate and forming a silicon layer by depositing silicon directly on the polycrystalline silicon seed layer under amorphous process conditions at a temperature below 600 C.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: April 21, 2015
    Assignee: Infineon Technologies AG
    Inventors: Wolfgang Lehnert, Stefan Pompl, Markus Meyer
  • Patent number: 9012309
    Abstract: Collections of laterally crystallized semiconductor islands for use in thin film transistors and systems and methods for making same are described. A display device includes a plurality of thin film transistors (TFTs) on a substrate, such that the TFTs are spaced apart from each other and each include a channel region that has a crystalline microstructure and a direction along which a channel current flows. The channel region of each of the TFTs contains a crystallographic grain that spans the length of that channel region along its channel direction. Each crystallographic grain in the channel region of each of the TFTs is physically disconnected from and crystallographically uncorrelated with each crystallographic grain in the channel region of each adjacent TFT.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: April 21, 2015
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: James S. Im, Ui-Jin Chung
  • Patent number: 9006865
    Abstract: In heteroepitaxially growing a group-III nitride semiconductor on a Si single crystal substrate, the occurrence of cracks initiating in the wafer edge portion can be suppressed. Region A is an outermost peripheral portion outside the principal surface, being a bevel portion tapered. Regions B and C are on the same plane (the principal surface), region B (mirror-surface portion) being the center portion of the principal surface, and region C a region in the principal surface edge portion surrounding region B. The principal surface has a plane orientation, and in region B, is mirror-surface-finished. Region B occupies most of the principal surface of this Si single crystal substrate, and a semiconductor device is manufactured therein. Region C (surface-roughened portion) has a plane orientation as with region B, however, region B is mirror-surface-finished, whereas region C is surface-roughened.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: April 14, 2015
    Assignee: Dowa Electronics Materials Co., Ltd.
    Inventors: Tetsuya Ikuta, Daisuke Hino, Tomohiko Shibata
  • Patent number: 9006799
    Abstract: Radio frequency and microwave devices and methods of use are provided herein. According to some embodiments, the present technology may comprise an ohmic layer for use in a field effect transistor that includes a plurality of strips disposed on a substrate, the plurality of strips comprising alternating source strips and drain strips, with adjacent strips being spaced apart from one another to form a series of channels, a gate finger segment disposed in each of the series of channels, and a plurality of gate finger pads disposed in an alternating pattern around a periphery of the plurality of strips such that each gate finger segment is associated with two gate finger pads.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: April 14, 2015
    Assignee: Sarda Technologies, Inc.
    Inventor: James L. Vorhaus
  • Patent number: 8999823
    Abstract: A semiconductor device according to the present invention includes a thin-film transistor and a thin-film diode. The respective semiconductor layers and of the thin-film transistor and the thin-film diode are crystalline semiconductor layers that have been formed by crystallizing the same crystalline semiconductor film. Ridges have been formed on the surface of the semiconductor layer of the thin-film diode. And the semiconductor layer of the thin-film diode has a greater surface roughness than the semiconductor layer of the thin-film transistor.
    Type: Grant
    Filed: October 20, 2009
    Date of Patent: April 7, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Naoki Makita, Hiroshi Nakatsuji
  • Patent number: 8993372
    Abstract: Exemplary embodiments of a method for producing a semiconductor component having a polycrystalline semiconductor body region are disclosed, wherein the polycrystalline semiconductor body region is produced between the first and second surfaces of the semiconductor body in a semiconductor component section, wherein an electromagnetic radiation having a wavelength of at least 1064 nm is introduced into the semiconductor body in a manner focused onto a position in the semiconductor component section of the semiconductor body and wherein the power density of the radiation at the position is less than 1×108 W/cm2.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: March 31, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Manfred Schneegans, Carsten Ahrens, Adolf Koller, Gerald Lackner, Anton Mauder, Hans-Joachim Schulze
  • Patent number: 8993461
    Abstract: A method for curing defects associated with the implantation of atomic species into a semiconductor layer transferred onto a receiver substrate, wherein the semiconductor layer is thermally insulated from the receiver substrate by a low thermal conductivity layer having thermal conductivity that is lower than that of the transferred semiconductor layer. The method includes applying a selective electromagnetic irradiation to the semiconductor layer to heat that layer to a temperature lower than its temperature of fusion to cure defects without causing an increase in the temperature of the receiver substrate beyond 500° C.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: March 31, 2015
    Assignee: Soitec
    Inventors: Ionut Radu, Christophe Gourdel, Christelle Vetizou
  • Patent number: 8993421
    Abstract: In the present invention, each laser light emitted from a plurality of lasers is divided, and laser light including at least one laser light that is emitted from a different laser and that has different energy distribution is synthesized with another such laser light, or laser light including at least one laser light that has different energy distribution is synthesized with another such laser light through a convex lens that is set at an angle to the direction each laser light travels, to form laser light having excellent uniformity in energy distribution.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: March 31, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koichiro Tanaka, Tomoaki Moriwaka
  • Patent number: 8987120
    Abstract: The present invention relates to a flat panel display device comprising a polysilicon thin film transistor and a method of manufacturing the same. Grain sizes of polysilicon grains formed in active channel regions of thin film transistors of a driving circuit portion and a pixel portion of the flat panel display device are different from each other. Further, the flat panel display device comprising P-type and N-type thin film transistors having different particle shapes from each other.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: March 24, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ji-Yong Park, Jae-Bon Koo, Hye-Hyang Park, Ki-Yong Lee, Ul-Ho Lee
  • Patent number: 8969183
    Abstract: Method for making thin crystalline or polycrystalline layers. The method includes electrochemically etching a crystalline silicon template to form a porous double layer thereon, the double layer including a highly porous deeper layer and a less porous shallower layer. The shallower layer is irradiated with a short laser pulse selected to recrystallize the shallower layer resulting in a crystalline layer. Silicon is deposited on the recrystallized shallower layer and the silicon is irradiated with a short laser pulse selected to crystalize the silicon leaving a layer of crystallized silicon on the template. Thereafter, the layer of crystallized silicon is separated from the template. The process of the invention can be used to make optoelectronic devices.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: March 3, 2015
    Assignees: President and Fellows of Harvard College, Massachusetts Institute of Technology
    Inventors: Mark T. Winkler, Tonio Buonassisi, Riley E. Brandt, Michael J. Aziz, Austin Joseph Akey
  • Patent number: 8951851
    Abstract: A method of manufacturing a low temperature polysilicon film comprises: providing a substrate on a platform; forming a buffer layer on said substrate; forming an amorphous silicon layer on said buffer layer; and heating and annealing said amorphous silicon layer to allow said amorphous silicon layer to form a polycrystalline silicon layer; wherein a thermal insulating layer is formed on a bottom surface of said substrate or a top surface of the platform, before said buffer layer is formed on said substrate.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: February 10, 2015
    Assignee: Boe Technology Group Co., Ltd.
    Inventors: Xueyan Tian, Chunping Long
  • Patent number: 8946678
    Abstract: Room temperature IR and UV photodetectors are provided by electrochemical self-assembly of nanowires. The detectivity of such IR detectors is up to ten times better than the state of the art. Broad peaks are observed in the room temperature absorption spectra of 10-nm diameter nanowires of CdSe and ZnS at photon energies close to the bandgap energy, indicating that the detectors are frequency selective and preferably detect light of specific frequencies. Provided is a photodetector comprising: an aluminum substrate; a layer of insulator disposed on the aluminum substrate and comprising an array of columnar pores; a plurality of semiconductor nanowires disposed within the pores and standing vertically relative to the aluminum substrate; a layer of nickel disposed in operable communication with one or more of the semiconductor nanowires; and wire leads in operable communication with the aluminum substrate and the layer of nickel for connection with an electrical circuit.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: February 3, 2015
    Assignee: Virginia Commonwealth University
    Inventors: Supriyo Bandyopadhyay, Saumil Bandyopadhyay, Pratik Agnihotri
  • Patent number: 8946098
    Abstract: A device is intended for a laser lift-off method to sever at least one layer from a carrier. The device includes a laser that generates pulsed laser radiation and at least one beam splitter. The laser radiation is divided into at least two partial beams by the at least one beam splitter. The partial beams are superimposed in an irradiation plane, the irradiation plane being provided such that a major side of the carrier remote from the layer is arranged therein. At the irradiation plane, an angle (?) between the at least two partial beams is at least 1.0°.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: February 3, 2015
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventor: Ralph Wagner
  • Patent number: 8940625
    Abstract: An embodiment of the present invention relates to a low temperature polysilicon thin film and a manufacturing method thereof. The manufacturing method comprises: forming a buffer layer on a substrate (S11); forming a seed layer comprising a plurality of uniformly distributed crystal nuclei on the buffer layer by using a patterning process (S12); forming an amorphous silicon layer on the seed layer (S13); and performing an excimer laser annealing process on the amorphous silicon layer (S14).
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: January 27, 2015
    Assignee: Boe Technology Group Co., Ltd.
    Inventors: Xueyan Tian, Chunping Long, Jiangfeng Yao
  • Patent number: 8927199
    Abstract: A mask includes: a substrate that includes a central area and a peripheral area disposed around the central area; and lenses disposed in rows and columns, in the central area and the peripheral area. The lenses of opposing sides of the peripheral area may be disposed in different rows or columns. For a given amount of input light, the lenses of the peripheral area may focus less light on a substrate than the lenses of the central area. The mask may be disposed over the substrate in different positions, and then the substrate may be irradiated through the mask, while the mask is in each of the positions. The peripheral portion of the mask may be disposed over the same area of the substrate, while the mask is in different ones of the positions.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: January 6, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Soo-Wan Yoon, Yeong-Keun Kwon, Chong-Chul Chai
  • Patent number: 8921783
    Abstract: A method of using electron diffraction to obtain PDFs from crystalline, nanocrystalline, and amorphous inorganic, organic, and organometallic compound.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: December 30, 2014
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Simon Billinge, Christopher Farrow, Tatiana E. Gorelik, Mercouri Kanatzidis, Martin U. Schmidt
  • Patent number: 8912054
    Abstract: A method of manufacturing a thin-film semiconductor device according to the present disclosure includes: preparing a substrate; forming a gate electrode above the substrate; forming a first insulating film on the gate electrode; forming a semiconductor thin film that is to be a channel layer, on the first insulating film; forming a second insulating film on the semiconductor thin film; irradiating the second insulating film with a beam so as to increase a transmittance of the second insulating film; and forming a source electrode and a drain electrode above the channel layer.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: December 16, 2014
    Assignees: Panasonic Corporation, Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Hiroshi Hayashi, Takahiro Kawashima, Genshiro Kawashi
  • Patent number: 8912102
    Abstract: A system for and method of processing an article such as a semiconductor wafer is disclosed. The wafer includes first and second surfaces which are segmented into a plurality of first and second zones. The first surface of the wafer, for example, on which devices or ICs are formed is processed by, for example, laser annealing while the second surface is heated with a backside heating source. Corresponding, or at least substantially corresponding, zones on the first and second surfaces are processed synchronously to reduce variations of post laser anneal thermal budget across the wafer.
    Type: Grant
    Filed: March 2, 2009
    Date of Patent: December 16, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Chyiu Hyia Poon, Alex K H See, Meisheng Zhou
  • Publication number: 20140357066
    Abstract: A method of crystallising a thin film (220) including the steps of: depositing a thin film (220) on a substrate (210; and exposing the thin film (220) as deposited on the substrate (210) and the substrate (210) to a plasma for a time period of greater than 5 minutes, wherein: the thin film (220) is one of an amorphous magneto optic material, an amorphous electro optic material or a nitride material; a gas (130) is excited with a radio frequency (RF) field to form the plasma; the thin film (220) and the substrate (210) are, in the course of being exposed to the plasma, heated to temperatures of between 400° C. and 550° C. by the plasma; and the thin film (220) is at least partially crystallised by the plasma.
    Type: Application
    Filed: September 6, 2012
    Publication date: December 4, 2014
    Applicant: Panorama Synergy, Ltd.
    Inventor: Roger Dunstan Jeffery
  • Publication number: 20140357065
    Abstract: The embodiments described herein generally relate to methods for forming an amorphous silicon structure that may be used in thin film transistor devices. In embodiments disclosed herein, the amorphous silicon layer is deposited using a silicon-based gas with an activation gas comprising a high concentration of inert gas and a low concentration of hydrogen-based gas. The activation gas combination allows for a good deposition profile of the amorphous silicon layer from the edge of the shadow frame which is translated to the polycrystalline silicon layer post-annealing.
    Type: Application
    Filed: May 19, 2014
    Publication date: December 4, 2014
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Qunhua WANG, Lai ZHAO, Soo Young CHOI
  • Patent number: 8896034
    Abstract: Radio frequency and microwave devices and methods of use are provided herein. According to some embodiments, the present technology may comprise an ohmic layer for use in a field effect transistor that includes a plurality of strips disposed on a substrate, the plurality of strips comprising alternating source strips and drain strips, with adjacent strips being spaced apart from one another to form a series of channels, a gate finger segment disposed in each of the series of channels, and a plurality of gate finger pads disposed in an alternating pattern around a periphery of the plurality of strips such that each gate finger segment is associated with two gate finger pads.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: November 25, 2014
    Assignee: Sarda Technologies, Inc.
    Inventor: James L. Vorhaus
  • Patent number: 8895416
    Abstract: Systems and methods for semiconductor device PN junction fabrication are provided. In one embodiment, a method for fabricating an electrical device having a P-N junction comprises: depositing a layer of amorphous semiconductor material onto a crystalline semiconductor base, wherein the crystalline semiconductor base comprises a crystalline phase of a same semiconductor as the amorphous layer; and growing the layer of amorphous semiconductor material into a layer of crystalline semiconductor material that is epitaxially matched to the lattice structure of the crystalline semiconductor base by applying an optical energy that penetrates at least the amorphous semiconductor material.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: November 25, 2014
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: Bhushan Sopori, Anikara Rangappan
  • Patent number: 8889519
    Abstract: The present invention discloses a semiconductor device, comprising: a substrate, a gate stack structure on the substrate, source and drain regions in the substrate on both sides of the gate stack structure, and a channel region between the source and drain regions in the substrate, characterized in that at least one of the source and drain regions comprises a GeSn alloy. In accordance with the semiconductor device and method for manufacturing the same of the present invention, GeSn stressed source and drain regions with high concentration of Sn is formed by implanting precursors and performing a laser rapid annealing, thus the device carrier mobility of the channel region is effectively enhanced and the device drive capability is further improved.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: November 18, 2014
    Assignee: The institute of Microelectronics Chinese Academy of Science
    Inventors: Xiaolong Ma, Huaxiang Yin, Zuozhen Fu
  • Patent number: 8890170
    Abstract: There is provided a silicon carbide substrate composed of silicon carbide, including encapsulated regions inside, which form incoherent boundaries between the silicon carbide and the encapsulated regions, wherein propagation of stacking faults in the silicon carbide is blocked.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: November 18, 2014
    Assignee: Hoya Corporation
    Inventors: Hiroyuki Nagasawa, Takamitsu Kawahara, Kuniaki Yagi, Naoki Hatta
  • Patent number: 8883266
    Abstract: A method of fabricating quantum confinements is provided. The method includes depositing, using a deposition apparatus, a material layer on a substrate, where the depositing includes irradiating the layer, before a cycle, during a cycle, and/or after a cycle of the deposition to alter nucleation of quantum confinements in the material layer to control a size and/or a shape of the quantum confinements. The quantum confinements can include quantum wells, nanowires, or quantum dots. The irradiation can be in-situ or ex-situ with respect to the deposition apparatus. The irradiation can include irradiation by photons, electrons, or ions. The deposition is can include atomic layer deposition, chemical vapor deposition, MOCVD, molecular beam epitaxy, evaporation, sputtering, or pulsed-laser deposition.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: November 11, 2014
    Assignees: The Board of Trustees of the Leland Stanford Junior University, Honda Patents & Technologies North America, LLC
    Inventors: Timothy P. Holme, Andrei Iancu, Hee Joon Jung, Michael C Langston, Munekazu Motoyama, Friedrich B. Prinz, Takane Usui, Hitoshi Iwadate, Neil Dasgupta, Cheng-Chieh Chao
  • Patent number: 8883656
    Abstract: High throughput systems and processes for recrystallizing thin film semiconductors that have been deposited at low temperatures on a substrate are provided. A thin film semiconductor workpiece is irradiated with a laser beam to melt and recrystallize target areas of the surface exposed to the laser beam. The laser beam is shaped into one or more beamlets using patterning masks. The mask patterns have suitable dimensions and orientations to pattern the laser beam radiation so that the areas targeted by the beamlets have dimensions and orientations that are conducive to semiconductor recrystallization. The workpiece is mechanically translated along linear paths relative to the laser beam to process the entire surface of the work piece at high speeds. Position sensitive triggering of a laser can be used to generate laser beam pulses to melt and recrystallize semiconductor material at precise locations on the surface of the workpiece while it is translated on a motorized stage.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: November 11, 2014
    Assignee: The Trustees of Columbia University in the City of New York
    Inventor: James S. Im
  • Publication number: 20140319468
    Abstract: Systems including and methods for forming a backplane for an electronic display are presented. The backplane includes interlaced crystallized regions, and the interlaced crystallized regions include at least a left column of crystallized regions and a right column of crystallized regions. The left and right columns include rows of crystallized regions with gaps disposed between each of the rows. Furthermore, each crystallized region in the left column extends into a corresponding gap in the right column, and each crystallized region in the right column extends into a corresponding gap in the left column.
    Type: Application
    Filed: April 25, 2013
    Publication date: October 30, 2014
    Applicant: APPLE INC.
    Inventors: Yu Cheng Chen, Hiroshi Osawa, Shih Chang Chang