And Subsequent Crystallization Patents (Class 438/486)
-
Patent number: 6964831Abstract: A method of fabricating a polysilicon film by an excimer laser crystallization process is disclosed. First, a substrate with a first region, a second region surrounding the first region, and a third region is provided. An amorphous silicon film is formed on the substrate. A photo-etching process is performed to remove parts of amorphous silicon film in the third region to form an alignment mark. Then, a mask layer is formed on the amorphous silicon film and a second photo-etching process is performed to remove the mask layer in the first region to expose the amorphous silicon film in the first region. After that, an excimer laser irradiation process is performed so that the amorphous silicon film in the first region is crystallized and becomes a polysilicon film.Type: GrantFiled: July 25, 2003Date of Patent: November 15, 2005Assignee: AU Optronics Corp.Inventor: Kun-chih Lin
-
Patent number: 6963692Abstract: A method involves increasing a temperature of a workpiece over a first time period to an intermediate temperature, and heating a surface of the workpiece to a desired temperature greater than the intermediate temperature, the heating commencing within less time following the first time period than the first time period. Another method involves pre-heating the workpiece from an initial temperature to an intermediate temperature, and heating a surface of the workpiece to a desired temperature greater than the intermediate temperature by an amount less than or equal to about one-fifth of a difference between the intermediate and initial temperatures. Another method involves irradiating a first side of the workpiece to pre-heat the workpiece to an intermediate temperature, and irradiating a second side of the workpiece to heat the second side to a desired temperature greater than the intermediate temperature.Type: GrantFiled: April 30, 2003Date of Patent: November 8, 2005Assignee: Vortek Industries Ltd.Inventors: David Malcolm Camm, J. Kiefer Elliot
-
Patent number: 6962884Abstract: A method for processing integrated circuit devices. The method includes providing a monitor wafer, which comprising a silicon material. The method introduces a plurality of particles within a depth of the silicon material. The plurality of particles have a reduced activation energy within the silicon material. The method subjects the monitor wafer including the plurality of particles into a rapid thermal anneal process. The method includes applying the rapid thermal anneal process at a first state including a first temperature. The first temperature is within a range defined as a low temperature range, which is less than 650 Degrees Celsius. The method includes removing the monitor wafer and measuring a sheet resistivity of the monitor wafer. The method also determines the first temperature within a tolerance of less than 2 percent across the monitor wafer.Type: GrantFiled: December 19, 2003Date of Patent: November 8, 2005Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Jingang Wu, Amy Liu, Tony Wang, Dennis Huang
-
Patent number: 6959029Abstract: A wide-slit lateral growth projection mask, projection system, and corresponding crystallization process are provided. The mask includes an opaque region with at least one a transparent slit in the opaque region. The slit has a width in the range of 10X to 50X micrometers, with respect to a X:1 demagnification system, and a triangular-shaped slit end. The triangular-shaped slit end has a triangle height and an aspect ratio in the range of 0.5 to 5. The aspect ratio is defined as triangle height/slit width. In some aspects, the triangular-shaped slit end includes one or more opaque blocking features. In another aspect, the triangular-shaped slit end has stepped-shaped sides. The overall effect of the mask is to promote uniformly oriented grain boundaries, even in the film areas annealed under the slit ends.Type: GrantFiled: July 22, 2004Date of Patent: October 25, 2005Assignee: Sharp Laboratories of America, Inc.Inventors: Apostolos T. Voutsas, Mark A. Crowder, Yasuhiro Mitani
-
Patent number: 6953717Abstract: A grain size of a crystal grain in a crystalline semiconductor film obtained by a thermal crystallization method using a metallic element is reduced. Thus, the number of crystal grains in active regions of a device is made uniform. The thermal crystallization method using a metallic element is performed for a semiconductor film formed on an insulating film formed at a lower temperature than that at formation of the semiconductor film and that at crystallization of the semiconductor film. By thermal treatment in a step of crystallizing the semiconductor film, stress of the insulating film is applied to the semiconductor film, thus causing distortion in the semiconductor film. When the distortion is caused, surface energy and a chemical potential of the semiconductor film are changed to promote the generation of a natural nucleus. Therefore, since a generation density of the crystal nucleus is increased, a grain size of a crystal grain can be reduced.Type: GrantFiled: October 7, 2004Date of Patent: October 11, 2005Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yasuyuki Arai, Shinji Maekawa
-
Patent number: 6953716Abstract: A metal induced lateral crystallization (MILC) poly-silicon material is produced by depositing a metal in a predefined pattern on amorphous silicon, and heat treating the silicon at a first temperature to form a MILC poly-Si material. The MILC poly-Si material is further heat treated at a second temperature higher than the first temperature to induce recrystallization. The second high temperature recrystallization step significantly enhances the material structure, and in particular the grain structure, of the poly-Si material with substantial benefits to the performance of semiconductor devices made therefrom.Type: GrantFiled: December 22, 2003Date of Patent: October 11, 2005Assignee: The Hong Kong University of Science and TechnologyInventors: Man Wong, Hoi Sing Kwok, Zhiguo Meng, Mingxiang Wang
-
Patent number: 6951996Abstract: Pulsed processing methods and systems for heating objects such as semiconductor substrates feature process control for multi-pulse processing of a single substrate, or single or multi-pulse processing of different substrates having different physical properties. Heat is applied a controllable way to the object during a background heating mode, thereby selectively heating the object to at least generally produce a temperature rise throughout the object during background heating. A first surface of the object is heated in a pulsed heating mode by subjecting it to at least a first pulse of energy. Background heating is controlled in timed relation to the first pulse. A first temperature response of the object to the first energy pulse may be sensed and used to establish at least a second set of pulse parameters for at least a second energy pulse to at least partially produce a target condition.Type: GrantFiled: December 29, 2003Date of Patent: October 4, 2005Assignee: Mattson Technology, Inc.Inventors: Paul J. Timans, Narasimha Acharya
-
Patent number: 6951802Abstract: A spin addition method for catalyst elements is simple and very important technique, because the minimum amount of a catalyst element necessary for crystallization can be easily added by controlling the catalyst element concentration within a catalyst element solution, but there is a problem in that uniformity in the amount of added catalyst element within a substrate is poor. The non-uniformity in the amount of added catalyst element within the substrate is thought to influence fluctuation in crystallinity of a crystalline semiconductor film that has undergone thermal crystallization, and exert a bad influence on the electrical characteristics of TFTs finally structured by the crystalline semiconductor film. The present invention solves this problem with the aforementioned conventional technique.Type: GrantFiled: April 13, 2004Date of Patent: October 4, 2005Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki KaishaInventors: Misako Nakazawa, Toshiji Hamatani, Naoki Makita
-
Patent number: 6949422Abstract: Sequential lateral solidification (SLS) crystallization of amorphous silicon uses a mask having light transmitting portions. A method of crystallizing an amorphous silicon film using the mask includes forming an amorphous silicon layer over a substrate; forming a metal layer on the amorphous silicon layer; patterning the metal layer to expose a portion of the amorphous silicon layer in a TFT area where a thin film transistor is formed; disposing the mask over the portion of the amorphous silicon layer exposed by the metal layer; and irradiating the portion of the amorphous silicon layer exposed by the metal layer using a laser beam that passes through the light transmitting portions of the mask such that the portion of the amorphous silicon layer is crystallized and laterally growing grains are formed in grain regions.Type: GrantFiled: December 23, 2003Date of Patent: September 27, 2005Assignee: LG Philips LCD Co., Ltd.Inventor: Young-Joo Kim
-
Patent number: 6946367Abstract: Methods for forming a single crystal semiconductor thin film layer from a non-single crystal layer includes directing a light source having a homogenized intensity distribution and a modulated amplitude towards the non-single crystal layer, and relatively moving the light with respect to the layer wherein the amplitude of the conditioned light is preferably increased in the direction of relative motion of the light to the layer. Preferred methods also include multiple light exposures in overlapping series to form ribbon-shaped single crystal regions, and providing a low temperature point in the semiconductor layer to generate a starting location for single crystalization.Type: GrantFiled: February 13, 2003Date of Patent: September 20, 2005Assignee: Kabushiki Kaisha Ekisho Sentan Gijutsu Kaihatsu CenterInventors: Masakiyo Matsumura, Mikihiko Nishitani, Yoshinobu Kimura, Masayuki Jyumonji, Yukio Taniguchi, Masato Hiramatsu, Fumiki Nakano
-
Patent number: 6943085Abstract: A method of manufacturing a MOS transistor is provided. A substrate having a gate structure thereon is provided. A first spacer is formed on the sidewall of the gate structure. A pre-amorphization implantation is carried out to amorphize a portion of the substrate. A doped source/drain extension region is formed in the substrate on each side of the first spacer. A second spacer is formed on the sidewall of the first spacer. A doped source/drain region is formed in the substrate on each side of the second spacer and then a pre-annealing operation is performed. Thereafter, a solid phase epitaxial process is carried out to re-crystallize the amorphized portion of the substrate and activate the doped source/drain extension region and the doped source/drain region to form a source/drain terminal. Finally, a post-annealing operation is performed.Type: GrantFiled: September 17, 2003Date of Patent: September 13, 2005Assignee: United Microelectronics Corp.Inventors: Yu-Ren Wang, Chin-Cheng Chien, Hsiang-Ying Wang, Neng-Hui Yang
-
Patent number: 6939754Abstract: A high-quality isotropic polycrystalline silicon (poly-Si) and a method for fabricating high quality isotropic poly-Si film are provided. The method includes forming a film of amorphous silicon (a-Si) and using a MISPC process to form poly-Si film in a first area of the a-Si film. The method then anneals a second area, included in the first area, using a Laser-Induced Lateral Growth (LILaC) process. In some aspects, a 2N-shot laser irradiation process is used as the LILaC process. In some aspects, a directional solidification process is used as the LILaC process. In response to using the MISPC film as a precursor film, the method forms low angle grain boundaries in poly-Si in the second area.Type: GrantFiled: August 13, 2003Date of Patent: September 6, 2005Assignee: Sharp Laboratories of America, Inc.Inventors: Masao Moriguchi, Apostolos T. Voutsas, Mark A. Crowder
-
Patent number: 6933182Abstract: A method of manufacturing a semiconductor device, comprises the steps of: forming an amorphous silicon film on a substrate having an insulating surface; processing said amorphous silicon film by plasma of a gas that mainly contains hydrogen or helium; and giving an energy to said amorphous silicon film.Type: GrantFiled: March 1, 1999Date of Patent: August 23, 2005Inventors: Shunpei Yamazaki, Satoshi Teramoto, Naoto Kusumoto, Hideto Ohnuma
-
Patent number: 6930025Abstract: In a process for forming on a substrate a transparent conductive film having crystallizability, the process comprises a first step of forming a film at a first film formation rate and a second step of forming a film at a second film formation rate, and the relationship between film formation rates in the respective steps satisfies: 2?(second film formation rate)/(first film formation rate)?100; which provides a process for producing a transparent conductive film by a deposition process advantageous for cost reduction, which can form in a short time a transparent conductive film having an uneven surface profile with a high light-confining effect, and can bring about an improvement in photovoltaic performance and enjoy a high mass productivity when applied to the formation of multi-layer structure of photovoltaic devices.Type: GrantFiled: January 31, 2002Date of Patent: August 16, 2005Assignee: Canon Kabushiki KaishaInventors: Akiya Nakayama, Hiroshi Echizen, Yasuyoshi Takai, Naoto Okada, Shigeo Kiso
-
Patent number: 6930015Abstract: Methods of forming a roughened surface through diffusion-enhanced crystallization of an amorphous material are disclosed. In one aspect, conductive hemispherical grain silicon can be formed through dopant diffusion-enhanced crystallization of one or more layers of amorphous silicon. To further enhance uniformity in the formation of the hemispherical grain silicon, the exposed surface of the amorphous silicon can be seeded before crystallization to further enhance uniformity of the surface structures formed in the hemispherical grain silicon.Type: GrantFiled: December 16, 2002Date of Patent: August 16, 2005Assignee: Micron Technology, Inc.Inventors: Er-Xuan Ping, Randhir Thakur
-
Patent number: 6930326Abstract: According to the invention, a plurality of semiconductor devices which are required to have conformance are formed from crystalline semiconductor films having uniform crystallinity on the same line, and a semiconductor circuit in which variation between semiconductor devices is small can be provided, and a semiconductor integrated circuit having high conformance can be provided. The invention is characterized in that, in a part or whole of thin film transistors which configure an analog circuit such as a current mirror circuit, a differential amplifier circuit, or an operational amplifier, in which high conformance is required for semiconductor devices included therein, channel forming regions have crystalline semiconductor films on the same line. High conformance can be expected for an analog circuit which has the crystalline semiconductor films on the same line formed using the invention as the channel forming regions of the thin film transistors.Type: GrantFiled: March 25, 2003Date of Patent: August 16, 2005Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kiyoshi Kato, Tomoaki Atsumi, Atsuo Isobe
-
Patent number: 6924216Abstract: A method of forming the active regions of field effect transistors is proposed. According to the proposed method, shallow implanting profiles for both the halo structures and the source and drain regions can be obtained by carrying out a two-step damaging and amorphizing implantation process. During a first step, the substrate is damaged during a first light ion implantation step and subsequently substantially fully amorphized during a second heavy ion implantation step.Type: GrantFiled: May 19, 2003Date of Patent: August 2, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Thomas Feudel, Manfred Horstmann, Rolf Stephan
-
Patent number: 6919237Abstract: A process for fabricating a semiconductor device including the steps of introducing into an amorphous silicon film, a metallic element which accelerates the crystallization of the amorphous silicon film, applying heat treatment to the amorphous silicon film to obtain a crystalline silicon film, irradiating a laser beam or an intense light to the crystalline silicon film, and heat treating the crystalline silicon film irradiated with a laser beam or an intense light.Type: GrantFiled: July 2, 2003Date of Patent: July 19, 2005Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hisashi Ohtani, Takeshi Fukunaga, Akiharu Miyanaga
-
Patent number: 6908797Abstract: The present invention provides a manufacturing method of a semiconductor device, which is able to improve on-current and mobility of a polycrystal TFT without disturbing a high integration level, and also provide a semiconductor device obtained in accordance with the manufacturing method.Type: GrantFiled: July 8, 2003Date of Patent: June 21, 2005Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Tamae Takano
-
Patent number: 6905920Abstract: A method for the fabrication of a field-effect transistor wherein after forming a semiconductor layer serving as an active layer on a substrate, the substrate temperature is set at no higher than 100° C., a gate insulating film is formed on the semiconductor layer. Then, the gate insulating film is heat treated in an atmosphere containing water. By heat treating in the atmosphere containing water, OH bonds in the vicinity of the insulating film interface are reduced and, therefore, the CV characteristic thereof is improved.Type: GrantFiled: August 31, 2001Date of Patent: June 14, 2005Assignee: Seiko Epson CorporationInventors: Seiichiro Higashi, Daisuke Abe
-
Patent number: 6906346Abstract: This invention concerns with a semiconductor device which is characterized in that the device is provided with a thin film transistor 40 having a polycrystalline semiconductor layer 11, the semiconductor layer 11 including a channel area 22, highly doped drain areas 24, 17 positioned on both sides of the channel area 22 and LDD areas 18a, 18b positioned between the channel area 22 and the highly doped drain areas 24, 17 and lower in dopant density than the highly doped drain areas 24, 17, wherein any diameter of the crystal 14 at least partly existing in the LDD area 18b is larger than the size of other crystals 15.Type: GrantFiled: July 24, 2001Date of Patent: June 14, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hikaru Nishitani, Makoto Yamamoto, Yoshinao Taketomi
-
Patent number: 6892432Abstract: A method for manufacturing a nanotube cartridge including the steps of: adhering numerous nanotubes to a surface of a holder, disposing a knife edge at an inclination to the surface of the holder so that the knife edge is raised with its tip end being in contact with the surface of the holder, and collecting the nanotubes to near the tip end of the knife edge by moving the knife edge in a direction opposite from the tip end with the tip end being kept in contact with the surface, thus allowing the nanotubes to be arranged on the tip end of the knife edge with the nanotubes protruding from the tip end. When adhering the nanotubes to the holder surface, nanotubes are merely put in a vessel, the holder is placed in the vessel, and then the vessel is vibrated.Type: GrantFiled: December 7, 2001Date of Patent: May 17, 2005Assignees: Daiken Chemical Co., Ltd.Inventors: Yoshikazu Nakayama, Seiji Akita, Takayoshi Kishida, Akio Harada
-
Patent number: 6890805Abstract: When a crystalline semiconductor thin film formed by using a catalytic element for facilitating crystallization is subjected to a heat treatment in an atmosphere containing a halogen element at a temperature exceeding 700° C., a crystal structure in which crystal grain boundaries do not substantially exist can be obtained. In the present invention, the foregoing crystalline semiconductor thin film is formed on a crystallized glass substrate which is inexpensive and has high heat resistance, so that an inexpensive semiconductor device can be provided.Type: GrantFiled: April 25, 2003Date of Patent: May 10, 2005Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hisashi Ohtani
-
Patent number: 6884698Abstract: A process for manufacturing a semiconductor device, particularly a thin film transistor, by using a crystalline silicon film having excellent characteristics. The process comprises forming a silicon nitride film and an amorphous silicon film in contact thereto, introducing a catalyst element capable of promoting the crystallization of the amorphous silicon film by heating the amorphous silicon film, thereby crystallizing at least a part of the amorphous silicon film, and accelerating the crystallization by irradiating the silicon film with a laser beam or intense light equivalent thereto.Type: GrantFiled: February 27, 1997Date of Patent: April 26, 2005Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hisashi Ohtani, Akiharu Miyanaga, Hongyong Zhang, Naoaki Yamaguchi
-
Patent number: 6884665Abstract: Prior to converting a non-single crystal material of a semiconductor film into a single crystal material through the use of a laser beam, at least one dopant is introduced into whole of the semiconductor film. Then, the non-single crystal semiconductor film is irradiated with a laser beam to crystallize the semiconductor film. In this case, a ratio between quasi-fermi level of the single crystal material within one of transistor formation regions used to form transistors of different conductivity types and quasi-fermi level of the single crystal material within the other thereof is made to be between 0.5:1 and 2.0:1. Thus, transistors of different conductivity types are formed in the crystallized semiconductor film.Type: GrantFiled: July 11, 2003Date of Patent: April 26, 2005Assignee: NEC LCD Technologies, Ltd.Inventor: Mitsuasa Takahashi
-
Patent number: 6881686Abstract: A process of lateral crystallization comprises providing a silicon film on a substrate surface, exposing a localized substrate region at the substrate surface to a laser heating source, and annealing a portion of the silicon film in thermal contact with the localized substrate region by exposing the silicon film to a low-fluence optical annealing source.Type: GrantFiled: March 19, 2004Date of Patent: April 19, 2005Assignee: Sharp Laboratories of America, Inc.Inventors: Robert S. Sposili, Mark A. Crowder, Apostolos T. Voutsas
-
Patent number: 6881601Abstract: A nitride compound semiconductor light-emitting device having a stack of layers including an active layer for a light emitting device and a method of manufacturing the device is disclosed. The method includes the steps of growing a first layer on a substrate at a first temperature to obtain an incomplete crystalline structure including both indium and aluminum and having the composition expressed as InXAlYGa1-X-YN(0?X?1, 0?Y?1). The method grows a cap layer on the first layer to cover the first layer, with growth of the cap layer proceeding at a second temperature substantially equal to or below the first temperature. The first layer is heat treated at a third temperature above the first temperature to cause the incomplete crystalline structure to crystallize and to create areas of differing compositions, thus changing the first layer to an active layer. The material of the cap layer is selected to be heat stable during the heat-treating step.Type: GrantFiled: January 30, 2003Date of Patent: April 19, 2005Assignee: Kabushiki Kaisha ToshibaInventor: Hideto Sugawara
-
Patent number: 6881652Abstract: A thin film transistor using an intrinsic polycrystalline silicon film, the thin film transistor fabricated by forming an insulation layer on a substrate, forming a first amorphous silicon layer on the insulation layer, forming silicon nucleation sites on the first amorphous silicon layer; converting the first amorphous silicon layer into hemispherical grained silicon, forming a second amorphous silicon layer covering the hemispherical grained silicon, annealing the second amorphous silicon layer to convert the second amorphous silicon layer into a grained silicon film, patterning an oxide layer into a transistor gate oxide and leaving uncovered sections of the grained silicon on opposing sides of the transistor gate oxide, conductively doping the uncovered sections of the grained silicon and forming a patterned metal gate on the transistor gate oxide.Type: GrantFiled: February 13, 2004Date of Patent: April 19, 2005Assignee: Micron Technology, Inc.Inventor: Er-Xuan Ping
-
Patent number: 6875628Abstract: Nickel is introduced to a predetermined region of a peripheral circuit section, other than a picture element section, on an amorphous silicon film to crystallize from that region. After forming gate electrodes and others, sources, drains and channels are formed by doping impurities, and laser is irradiated to improve the crystallization. After that, electrodes/wires are formed. Thereby an active matrix type liquid crystal display whose thin film transistors (TFT) in the peripheral circuit section are composed of the crystalline silicon film whose crystal is grown in the direction parallel to the flow of carriers and whose TFTs in the picture element section are composed of the amorphous silicon film can be obtained.Type: GrantFiled: March 6, 1997Date of Patent: April 5, 2005Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hongyong Zhang, Toru Takayama, Yasuhiko Takemura, Akiharu Miyanaga
-
Patent number: 6861338Abstract: A metal element typified by Ni has an adverse effect on device properties of a TFT, and consequently, a step for removing the elements (hereinafter referred to as a gettering step) has been carried out. However, gettering steps as described above have the disadvantage of high cost due to an increase in the number of steps. Accordingly, a manufacturing method of a crystalline semiconductor film, which does not require a gettering step, has been in demand. A TFT of the present invention is characterized by reducing the concentration of the metal element, typically Ni, in the crystalline semiconductor film to less than 4×1016 atoms/cm3, more specifically, 5×1015 atoms/cm3 to 3×1016 atoms/cm3, preferably, 7×1015 atoms/cm3 to 3×1016 atoms/cm3. And the present invention enables crystallization even by the metal element with a low concentration and an omission of a gettering step.Type: GrantFiled: August 14, 2003Date of Patent: March 1, 2005Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shinji Maekawa
-
Patent number: 6858480Abstract: According to the present invention, an impurity region, to which a rare gas element (also called a rare gas) and one kind or a plurality of kinds of elements selected from the group consisting of H, H2, O, O2, and P are added, are formed in a semiconductor film having a crystalline structure, using a mask, and gettering for segregating a metal element contained in the semiconductor film to the impurity region by heat treatment. Thereafter, pattering is conducted using the mask, whereby a semiconductor layer made of the semiconductor film having a crystalline structure is formed.Type: GrantFiled: January 17, 2002Date of Patent: February 22, 2005Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Osamu Nakamura, Shunpei Yamazaki, Koji Dairiki, Masayuki Kajiwara, Junichi Koezuka, Satoshi Murakami
-
Patent number: 6858512Abstract: An a-Si film (12) formed on an insulating substrate (10) is irradiated with a laser so that the a-Si film (12) is fused and recrystallized to form a p-Si film (13). Projections (100) generated on the p-Si film (13) at this stage are eliminated by irradiation of ion beams at the incident angle of 60° to 90° using an ion milling method to planarize the surface of the p-Si film (13), thereby creating sufficient insulation between the p-Si film (13) and gate electrodes (15).Type: GrantFiled: March 28, 2001Date of Patent: February 22, 2005Assignee: Sanyo Electric Co., Ltd.Inventors: Yoshihiro Morimoto, Kiyoshi Yoneda
-
Patent number: 6849831Abstract: Pulsed processing methods and systems for heating objects such as semiconductor substrates feature process control for multi-pulse processing of a single substrate, or single or multi-pulse processing of different substrates having different physical properties. Heat is applied a controllable way to the object during a background heating mode, thereby selectively heating the object to at least generally produce a temperature rise throughout the object during background heating. A first surface of the object is heated in a pulsed heating mode by subjecting it to at least a first pulse of energy. Background heating is controlled in timed relation to the first pulse. A first temperature response of the object to the first energy pulse may be sensed and used to establish at least a second set of pulse parameters for at least a second energy pulse to at least partially produce a target condition.Type: GrantFiled: July 30, 2002Date of Patent: February 1, 2005Assignee: Mattson Technology, Inc.Inventors: Paul J. Timans, Narasimha Acharya
-
Patent number: 6849525Abstract: A method of forming a polycrystalline silicon layer includes: forming an amorphous silicon layer on a substrate; depositing a catalyst metal on the amorphous silicon layer; disposing first and second electrodes contacting the amorphous silicon layer along a first direction; heating the amorphous silicon layer under a first temperature and simultaneously applying a first voltage to the first and second electrodes to form a first crystallized amorphous silicon layer; disposing third and fourth electrodes contacting the first crystallized amorphous silicon layer along a second direction, the second direction being different from the first direction; and heating the first crystallized amorphous silicon layer under a second temperature and simultaneously applying a second voltage to the third and fourth electrodes to form a secondly crystallized amorphous silicon layer.Type: GrantFiled: June 20, 2003Date of Patent: February 1, 2005Assignee: LG.Philips LCD Co., Ltd.Inventors: Binn Kim, Hae-Yeol Kim, Jong-Uk Bae
-
Patent number: 6849498Abstract: Disclosed herein is a method of manufacturing a semiconductor capacitor. In the semiconductor capacitor manufacturing method, an amorphous film composed of non-doped silicon is formed. The amorphous film is changed to a lower film having projections and depressions defined in the surface thereof by heat treatment. An amorphous film composed of impurity-doped silicon is formed over the surface of the lower film. Further, the amorphous film composed of the impurity-doped silicon is changed to an upper film having projections and depressions defined in the surface thereof by heat treatment with the projections and depressions provided over the surface of the lower film as a basis. The semiconductor capacitor is equipped with an electrode having the lower film and the upper film.Type: GrantFiled: August 7, 2002Date of Patent: February 1, 2005Assignee: Oki Electric Industry Co., Ltd.Inventor: Hiroki Kuroki
-
Patent number: 6844248Abstract: A low temperature process for forming a metal doped silicon layer in which a silicon layer is deposited onto a substrate at low temperatures, with a metal doping layer then deposited upon the silicon layer. This structure is then annealed at low temperatures to form a metal doped semiconductor having greater than about 1×1020 dopant atoms per cm3 of silicon.Type: GrantFiled: July 14, 2003Date of Patent: January 18, 2005Assignee: The Trustees of the University of ArkansasInventors: Hameed A. Naseem, M. Shahidul Haque, William D. Brown
-
Patent number: 6844249Abstract: The invention relates to a method for manufacturing a semiconductor device, and it is an object of the invention to form a semiconductor area formed in island-like patterns as a single crystal or an area which can be regarded as a single crystal, and to simultaneously achieve a laminated structure by which various characteristics of TFTs can be stabilized, wherein an insulation film is formed on a glass substrate, and island-like semiconductor layer is formed thereon. A laser beam passed through a cylindrical lens is made into a linear laser beam and irradiated onto the island-like semiconductor layer by an optical system.Type: GrantFiled: August 27, 2003Date of Patent: January 18, 2005Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Ritsuko Kawasaki, Kenji Kasahara, Shunpei Yamazaki
-
Patent number: 6841433Abstract: A method of forming a polycrystalline silicon active layer for use in a thin film transistor is provide. The method includes forming a buffer layer over a substrate, forming an amorphous silicon layer over the buffer layer, applying a catalytic metal to a surface of the amorphous silicon layer, crystallizing the amorphous silicon layer having the catalytic metal thereon into a polycrystalline silicon layer, forming an island pattern on the polycrystalline silicon layer, thereby defining an active region underneath in the polycrystalline silicon layer, applying n-type ions to the polycrystalline silicon layer and then heat-treating the polycrystalline silicon layer to remove the catalytic metal from the active region underneath the island pattern, and patterning the polycrystalline silicon layer using the island pattern as a mask to form an active layer.Type: GrantFiled: December 6, 2002Date of Patent: January 11, 2005Assignee: LG.Philips LCD Co., Ltd.Inventors: Hyun-Sik Seo, Binn Kim, Jong-Uk Bae
-
Patent number: 6838322Abstract: A method for forming a polysilicon FinFET (10) or other thin film transistor structure includes forming an insulative layer (12) over a semiconductor substrate (14). An amorphous silicon layer (32) forms over the insulative layer (12). A silicon germanium seed layer (44) forms in association with the amorphous silicon layer (32) for controlling silicon grain growth. The polysilicon layer arises from annealing the amorphous silicon layer (32). During the annealing step, silicon germanium seed layer (44), together with silicon germanium layer (34), catalyzes silicon recrystallization to promote growing larger crystalline grains, as well as fewer grain boundaries within the resulting polysilicon layer. Source (16), drain (18), and channel (20) regions are formed within the polysilicon layer. A double-gated region (24) forms in association with source (16), drain (18), and channel (20) to produce polysilicon FinFET (10).Type: GrantFiled: May 1, 2003Date of Patent: January 4, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Daniel T. Pham, Alexander L. Barr, Leo Mathew, Bich-Yen Nguyen, Anne M. Vandooren, Ted R. White
-
Publication number: 20040266079Abstract: When the laser light having the harmonic is used for crystallizing the semiconductor film, there is a problem that the energy conversion efficiency from the fundamental wave to the harmonic is low. And since the laser light converted into the harmonic has lower energy than the fundamental wave, it is difficult to enhance the throughput by enlarging the area of the beam spot. The present invention provides a laser irradiation apparatus emitting the fundamental wave simultaneously with the wavelength not longer than that of the fundamental wave, typically the harmonic converted from the fundamental wave, wherein the laser light emitted from one resonator having the fundamental wave and the wavelength not longer than that of the fundamental wave are irradiated without being separated.Type: ApplicationFiled: June 21, 2004Publication date: December 30, 2004Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Akihisa Shimomura, Hironobu Shoji
-
Publication number: 20040266146Abstract: A laser crystallizing device including a mask divided into two regions, having open parts of the same shape at complementary positions; and a light-shielding pattern selectively leaving one region of the mask open and masking the other regionType: ApplicationFiled: June 23, 2004Publication date: December 30, 2004Inventor: Yun Ho Jung
-
Publication number: 20040266078Abstract: A crystallization method of an amorphous semiconductor layer includes providing an amorphous semiconductor layer having a first thickness, crystallizing the amorphous semiconductor layer in a first direction, partially reducing the crystallized semiconductor layer to a second thickness less than the first thickness and crystallizing the etched semiconductor layer in a second direction.Type: ApplicationFiled: September 15, 2003Publication date: December 30, 2004Applicant: LG.Philips LCD Co., Ltd.Inventor: Sang Hyun Kim
-
Publication number: 20040253797Abstract: The present invention relates to a heating plate crystallization method used in the crystallization process for the poly-silicon thin-film transistor, and more particularly, the present invention relates to a heating plate crystallization method by using a pulsed rapid thermal annealing process (PRTP) By means of the characteristic provided by the present invention, namely, the heating plate area has a better absorption rate to the infrared rays and has a high thermal stability. The heating plate area is used for absorbing the infrared rays, and after the heating, the energy is indirectly transferred to the amorphous layer via a thermal conduction method so that the amorphous layer will be rapidly crystallized to form the poly-silicon. Furthermore, the present invention uses the pulsed rapid thermal annealing process (PRTP) using the infrared rays to instantly heat, to selectively heat the materials by taking the advantage that different materials have different absorption rates to the infrared rays.Type: ApplicationFiled: August 27, 2003Publication date: December 16, 2004Applicant: Industrial Technology Research InstituteInventors: Shun-Fa Huang, Chi-Lin Chen, Chiung-Wei Lin
-
Publication number: 20040253840Abstract: A method of crystallizing silicon including preparing a substrate having an amorphous silicon film formed thereon, aligning a mask having a first energy region and a second energy region over a first region of the amorphous silicon film formed on the substrate, irradiating a laser beam through the first and second energy regions of the mask onto the first region of the amorphous silicon film, crystallizing the first region of the amorphous silicon film by irradiating the laser beam through the first energy region of the mask, and activating the crystallized first region by irradiating the laser beam through the second energy region.Type: ApplicationFiled: May 18, 2004Publication date: December 16, 2004Applicant: LG.PHILIPS LCD CO., LTD.Inventor: JaeSung You
-
Patent number: 6831017Abstract: Nanowire devices may be provided that are based on carbon nanotubes or single-crystal semiconductor nanowires. The nanowire devices may be formed on a substrate. Catalyst sites may be formed on the substrate. The catalyst sites may be formed using lithography, thin metal layers that form individual catalyst sites when heated, collapsible porous catalyst-filled microscopic spheres, microscopic spheres that serve as masks for catalyst deposition, electrochemical deposition techniques, and catalyst inks. Nanowires may be grown from the catalyst sites.Type: GrantFiled: April 5, 2002Date of Patent: December 14, 2004Assignee: Integrated Nanosystems, Inc.Inventors: Jun Li, Alan M. Cassell, Jie Han
-
Patent number: 6830994Abstract: The number of grains in active regions of devices can be made uniform by making the grains of crystalline semiconductor films, obtained by thermal crystallization using a metal element, smaller. The present invention is characterized in that a semiconductor film is exposed within an atmosphere in which a gas, having as its main constituent one or a plurality of members from the group consisting of inert gas elements, nitrogen, and ammonia, is processed into a plasma, and then thermal crystallization using a metal element is performed. The concentration of crystal nuclei1 generated is thus increased, making the grain size smaller, by performing these processes. Heat treatment may also be performed, of course, after exposing the semiconductor film, to which the metal element is added, to an atmosphere in which a gas, having as its main constituent one or a plurality of members from the group consisting of inert gas elements, nitrogen, and ammonia, is processed into a plasma.Type: GrantFiled: March 6, 2002Date of Patent: December 14, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Toru Mitsuki, Takeshi Shichi, Shinji Maekawa, Hiroshi Shibata, Akiharu Miyanaga
-
Patent number: 6830965Abstract: A metal induced crystallization process is provided which employs an amorphous silicon film precursor deposited by physical vapor deposition, wherein the precursor film does not readily undergo crystallization by partial solid phase crystallization. Using this physical vapor deposition amorphous silicon precursor film, the amorphous silicon film is transformed to polysilicon by metal induced crystallization wherein the crystalline growth occurs fastest at regions that have been augmented with a metal catalyst and proceeds extremely slowly, practically zero, at regions which bear no metal catalyst. Accordingly, by use of the physical vapor deposition amorphous silicon precursor film in the process of the present invention, the metal induced crystallization process may take place at higher annealing temperatures and shorter annealing times without solid phase crystallization taking place.Type: GrantFiled: October 25, 2000Date of Patent: December 14, 2004Assignee: Sharp Laboratories of America, Inc.Inventors: Apostolos Voutsas, Yukihiko Nakata, Takeshi Hosoda
-
Patent number: 6828179Abstract: An object is to enhance the orientation ratio of a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film while using as a substrate a less-heat-resistive material such as glass thereby providing a semiconductor device using a crystalline semiconductor film with high quality equivalent to a single crystal. A first crystalline semiconductor film and a second crystalline semiconductor film are formed overlying a substrate, which integrally structure a crystalline semiconductor layer. The first and second crystalline semiconductor films are polycrystalline bodies aggregated with a plurality of crystal grains. However, the crystal grains are aligned toward a (101)-plane orientation at a ratio of 30 percent or greater, preferably 80 percent or greater.Type: GrantFiled: July 9, 2002Date of Patent: December 7, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Toru Mitsuki, Kenji Kasahara
-
Patent number: 6829328Abstract: A method for making a quantitative analysis of nickel that includes the steps of providing an amorphous silicon layer, forming an insulating film on the amorphous silicon layer, depositing nickel on the insulating film, etching a defined portion of the nickel with an etchant to create a specimen, drying the specimen on an AP1 film and subjecting the dried specimen to energy dispersive X-ray fluorescence analysis.Type: GrantFiled: December 4, 2002Date of Patent: December 7, 2004Assignee: LG. Philips LCD Co., Ltd.Inventors: Binn Kim, Hyun Ja Kwon, Kyu Ho Park
-
Patent number: 6825102Abstract: A method in which a defective semiconductor crystal material is subjected to an amorphization step followed by a thermal treatment step is provided. The amorphization step amorphizes, partially or completely, a region, including the surface region, of a defective semiconductor crystal material. A thermal treatment step is next performed so as to recrystallize the amorphized region of the defective semiconductor crystal material. The recrystallization is achieved in the present invention by solid-phase crystal regrowth from the non-amorphized region of the defective semiconductor crystal material.Type: GrantFiled: September 18, 2003Date of Patent: November 30, 2004Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Keith E. Fogel, Shreesh Narasimha, Devendra K. Sadana