Abstract: The invention relates to a method for integrating semiconductor device epilayers with arbitrary host substrates, where an indium gallium arsenide etch-stop layer (34) is deposited on an indium phosphide growth substrate (32) and device epilayers (36, 38) are grown on the etch-stop layer in inverse order from their final orientation. The device epilayers are then joined to an aluminum nitride host substrate (42) by inverting the growth substrate and device epilayers. The epilayers are bonded to the host substrate using mono-molecular layer forming bonding material and the growth substrate is selectively etched away from the device epilayers. As a result of the inverse epilayer growth, the epilayers are not removed from the growth substrate prior to bonding to the host substrate, thus protecting the device epilayers and reducing processing steps. Additionally, by mono-molecular bonding, sturdy semiconductor devices are formed with low thermal impedance.

Abstract: A semiconductor component comprises a pn junction in which both the p-conducting and the n-conducting layers of the pn junction are doped silicon carbide layers and the edge of at least one of the conducting layers of the pn junction exhibits a stepwise or uniformly decreasing total charge or effective surface charge density from the initial value at the defined working junction to a zero or almost zero total charge at the outermost edge of the junction following a radial direction from the central part of the junction towards its outermost edge.

Abstract: An integrated circuit fabrication process is provided in which a transistor having an ultra short channel length is formed by multiple etchings of a gate conductor layer. After formation of the gate conductor using a photolithographic process, the lateral length of the gate conductor is reduced by forming a masking layer upon the gate conductor such that only a portion of the gate conductor is covered by the masking layer. The unmasked portion of the gate conductor is then removed to reduce the lateral length of the gate conductor. In this manner, a gate conductor having a lateral length that is significantly less than a lateral length attainable using a photolithographic process may be obtained.

Abstract: The present invention provides a method for making semiconductor nanometer-scale wire. The method comprises the steps of: forming a nitride film on a semiconductor substrate by implanting a nitrogen ions at a high temperature; forming a nitride film pattern with several nanometer line width and spaced by several nanometer therebetween by using an Atomic Force Microscope; forming a silicon oxide film by selectively thermal-oxidizing an exposed portion of the semiconductor substrate; removing the nitride film pattern by using the Atomic Force Microscope; forming a semiconductor layer by using Molecular Beam Epitaxy method on the surface of the silicon oxide film and on the surface of the semiconductor substrate exposed by removing the nitride film pattern; and selectively removing the silicon oxide film and the semiconductor layer on the surface of the silicon oxide film through thermal treatment.

Abstract: Ultra-small three terminal semiconductor devices and a method of fabrication including patterning the planar surface of a substrate and a control layer to form a first and second pattern edge and consecutively forming a plurality of layers of semiconductor material in overlying relationship to the pattern edges so that a discontinuity is produced in the layers and a first layer on one side of the pattern edge is aligned with and in electrical contact with a different layer on the other side of the pattern edge.