Abstract: An inspection pattern for a semiconductor device includes at least one inspection pattern groove and a dummy interconnection. The inspection pattern groove is formed in an interlevel insulating film or lower interconnection covering a surface of a semiconductor substrate. The dummy interconnection is formed to intersect the inspection pattern groove by burying a metal material in the inspection pattern groove. The dummy interconnection has a side wall which is exposed in the groove-like opening portion and which is inspected whether a void is present therein. An inspection method for a semiconductor device is also disclosed.

Abstract: In a semiconductor device manufacturing system including a plurality of semiconductor device manufacturing equipment, a control circuit is connected to the semiconductor device manufacturing equipment. Also, a lot status memory for storing status of lots of semiconductor wafers, a branch content memory for storing branch information of the lots of semiconductor wafers, and a determination level memory for storing determination levels of the lots of semiconductor wafers are connected to the control circuit.

Abstract: It is intended to provide a ferroelectric that exhibits superior ferroelectricity. A ferroelectric provided is an oxide having a layered crystal structure that is composed of Bi, a first element Me, a second element R, and O. The first element Me is at least one element selected from the group consisting of Na, K, Ca, Ba, Sr, Pb, and Bi. The second element R is at least one element selected from the group consisting of Fe, Ti, Nb, Ta, and W. Ninety-eight percent or more of the entire body of the ferroelectric exhibits ferroelectricity. After an oxide having a layered crystal structure has been grown by a vapor-phase method (crystal growth step), electrodes are attached to the oxide having a layered crystal structure and a voltage is applied thereto (voltage application step).

Abstract: A system and method for deprocessing a semiconductor die is disclosed. The semiconductor dies has an active area and at least one feature in the active area. The method and system include tuning an ablation laser. The method and system further include ablating a first portion of the semiconductor die using a tuned ablation laser to mark a location of the feature. The first portion is distinct from the active area and has a center. The center of the first portion is substantially above the feature. The method and system also include deprocessing a second portion of the semiconductor die using the first portion as a guide.

Abstract: Multichip and single chip modules are presented as well as a chips first fabrication of such modules. The multichip module comprises a plurality of chips affixed in a planar array by a structural material which surrounds the sides of the chips such that the upper surfaces of the chips and an upper surface of the structural material are co-planar and the lower surface of at least one chip and a lower surface of the structural material are co-planar. A photo-patternable dielectric is disposed directly on the upper surfaces of the chips. The photo-patternable dielectric includes vias to at least some contact pads at the upper surfaces of the chips and the module further comprises an intrachip metallization layer on the photo-patternable dielectric layer. Subsequent processing provides a multi-layer chip interconnect structure over the intrachip metallization layer and photo-patternable dielectric.

Abstract: A method of making circuit edit structures through the backside of a flip-chip packaged integrated circuit die. In one embodiment, a circuit edit is achieved by exposing first and second circuit edit connection targets through a semiconductor substrate of the integrated circuit die from the backside. Next, a polyimide layer is vapor deposited over the first and second circuit edit connection targets and the exposed semiconductor substrate. Next, the circuit edit connection targets are re-exposed through the polyimide layer and a conductor is deposited over the re-exposed circuit edit connection targets and the deposited polyimide layer from the backside of the integrated circuit to couple together the circuit edit connection targets. The polyimide layer may act as both an insulation layer and an anti-reflective coating layer.

Abstract: A method and an apparatus for editing an integrated circuit. In one embodiment, an integrated circuit substrate is placed into a laser chemical vapor deposition (LCVD) tool and a conductive metal film is deposited onto the integrated circuit substrate over an area of interest. The integrated circuit substrate is subsequently placed into a focused ion beam (FIB) tool where an optional FIB cleaning step is performed on the conductive element deposited by the LCVD tool to help ensure that a good electrical contact can be made. The FIB tool is also used to introduce any desired cuts into signal lines of the integrated circuit to complete edits. The FIB is also used to remove passivation over integrated circuit nodes of interest to expose buried metal lines for subsequent coupling to the conductive element deposited with the LCVD tool.

Abstract: A method and an apparatus providing a circuit edit structure to an integrated circuit enabling circuit edits to be performed through the back side of an integrated circuit die. In one embodiment, a passive diffusion is disposed in the substrate of a flip-chip packaged integrated circuit die. A plurality of contacts couple the passive diffusion to a signal line disposed in a dielectric isolation layer of the integrated circuit die. In another embodiment, the signal line includes an uninterrupted length of approximately 3.0 microns beneath a field oxide region in the integrated circuit die, which provides a circuit edit cut location. The passive diffusion and circuit edit cut locations may be accessed through the back side of the flip-chip packaged integrated circuit, which enable circuit edits to be performed on the flip-chip packaged integrated circuit.

Abstract: A method for recycling monitoring control wafers includes cleaning the wafers after performing a sheet resistance (Rs) measurement on a bare silicon monitoring control wafer of an ion implanter, and then converting the wafer into a recyclable control wafer. A recyclable control wafer for a thermal wave (TW) measurement of destruction can be obtained by forming a screen layer on the wafer, performing a TW measurement, performing ion implantation by the monitoring recipe, performing TW measurement again, performing ion drive-in to drive implanted ions into the deeper areas of the substrate, removing the screen layer, and then forming another screen layer on the wafer to put the wafer into the recycling process of a TW measurement.

Abstract: Methods of forming a film on a substrate using chemical vapor deposition techniques and pyrazolyl complexes. The complexes and methods are particularly suitable for the preparation of semiconductor structures.

Abstract: Aspects for removing device packaging from an FBGA (fine pitch ball grid array) package are described. In an exemplary method aspect, the method includes recessing a predetermined area of the FBGA package, and exposing an integrated circuit die covered by the FBGA package. Device analysis is then performed on the exposed die. The step of recessing further includes milling the predetermined area, while the step of exposing includes chemically etching the FBGA package.

Abstract: A method for removing deposits from a probing feature of a probe card. The method includes the step of exposing the probing feature of a probe card to a composition that chemically reacts with the deposits on the probing feature to remove the deposits from the probing feature while not substantially effecting the material comprising the probing feature.

Abstract: The present invention provides a method for identifying failure sites on a defective IC chip by utilizing a glass substrate equipped with a heating device and then coating a liquid crystal material layer on top. The liquid crystal device can be positioned in contact, or immediately adjacent to a surface of an IC device to be detected. After the liquid crystal temperature is raised to just below its transition temperature, a voltage signal can be fed into the IC device to trigger an overheating at a short or leakage to raise the liquid crystal material immediately adjacent to the short or leakage to a temperature above its transition temperature. Hot spots are thus produced to appear as bright spots for easy identification under an optical microscope.

Abstract: Aspects for device and package separation of a multi-layer integrated circuit device attached at a frontside to an integrated circuit package are described. In an exemplary method aspect, the method includes slicing through material coupling the multi-layer integrated circuit to the integrated circuit package with a high power water stream. The slicing further includes cutting through solder bump material. Additionally, the multi-layer integrated circuit device is utilized for device analysis from a frontside following separation from the integrated circuit package by the step of slicing.

Abstract: A method for nondestructive layer defect detection includes projecting radiation such as a laser beam on a surface of the layer. The surface of the layer is heated by the projected radiation so as to melt at least a portion of the layer. An impurity contained in a defect is heated by the projected radiation so as to increase the pressure of the material within the defect sufficiently to cause the impurity to emerge from the defect through the surface of the layer. The layer is then scanned for a visible defect created by the emergence of the impurity from the defect. A wafer scanning system for nondestructive layer defect detection includes a radiation source such as a laser and a wafer support system that supports a semiconductor wafer with a layer formed thereon in alignment with the radiation source.

Abstract: A method and structure for customizing or repairing integrated circuits using passivated tungsten fuses and low-power energy beams to select which tungsten fuses are to be removed. The tungsten fuses are formed in an array to connect possible connection points of the device. A low-power energy source then selects undesired connection points, and a conventional etch removes the selected tungsten fuses, thereby customizing or repairing the integrated circuit. Because neither precision custom masks nor high energy laser sources are required, the problems associated with conventional methods are reduced or eliminated.

Abstract: A method for repairing defects in a surface layer of a substrate. The method comprises the redeposition, in a solvent environment, of a fill material into the defects of the surface layer. The fill material is provided by the surface layer itself or from a separate source comprising a different material from that of the surface layer.

Abstract: Improved thin film transistors to reduce defects in the devices incorporating the transistors, including active matrix displays. A first improvement is accomplished by forming a dual insulator layer over the bottom metal layer, which can be the gate line and also the row line in an active matrix display. The first insulator layer is formed by anodizing the metal layer and the second insulator layer is deposited onto the first layer. The dual insulator structure layer can be reanodized to eliminate the effect of pinholes. A second improvement includes providing an interdigitated transistor structure to increase the channel width, minimize internal shorting and minimize the drain capacitance. The interdigitated structure includes at least one source or drain finger formed between at least two drain or source fingers, respectively. A shorted source finger can be disconnected to maintain an operative transistor.

Abstract: A device repair process that includes removing a passivation polyimide layer. The passivation polyimide layer is removed using a first-half ash followed by a second-half ash. The device is rotated during the second-half ash. The device is then cleaned using sodium hydroxide (NaOH) and a subsequent light ash step is implemented. After the passivation polyimide layer is removed, a seed layer is deposited on the device. A photoresist is formed on the seed layer and bond sites are formed in the photoresist. Repair metallurgy is plated through the bond sites. The bond sites are plated by coupling the device to a fixture and applying the current for plating to the fixture. The contact between the device and the fixture is made though bottom surface metallurgy. After plating, the residual seed layer is removed and a laser delete process is implemented to disconnect and isolate the nets of the device.

Abstract: A die is unpackaged from a Chip on Tape by grinding off molding compound from an upper surface of the COT until the COT's leads are evenly exposed across the upper surface, selectively etching out the leads using the remaining molding compound as a mask, removing an underlying layer of gold plating, and then removing the remaining molding compound. The unpacked die can then be reframed with new leads and molding compound for failure analysis and electrical failure verification.

Abstract: A semiconductor with dedicated wire bond sites that are routed and via'd only to a top surface of a semiconductor package to flush mount pads where they are probed during debug, thus reducing the overall inductance and capacitance of the path from the wire bond site to the debug probing site over conventional debug testing by means of dedicated pins on the semiconductor package. This design permits higher performance debug data capture, while at the same time decreasing the number of pads and pins that are necessary for debug.

Abstract: A semiconductor memory chip has fuses and a redundancy memory cell which can replace a normal memory cell that is found defective by cutting off the fuses. If the normal memory cell is defective, the fuses are cut off thereby to connect the redundancy memory cell instead of the normal memory cell which is defective. The entire surface of the semiconductor memory chip is coated with a resist layer. The coated the resist layer is exposed at regions of the fuses to an energy beam, and then developed form a resist pattern. The semiconductor memory chip is etched at the regions using the resist pattern as a mask for thereby cutting off the fuses. The fuses may be spaced at intervals of 2 .mu.m or smaller, and can be cut off without causing damage to a layer beneath the fuses.

Abstract: A method for regenerating a used wafer or substrate by removing a functional coating film formed on the used wafer or substrate, comprising the steps of:(a) a step for sorting the used wafer or substrate according to the quality, structure or thickness of the functional coating film;(b) a step for removing the functional coating film, while in a state of holding the used wafer or substrate, (i) by lapping the objective face of the used wafer or substrate with a hard metal-bonded whetstone while applying an electrochemical in-process dressing, (ii) by polishing the objective face while dropping a fine-particle polishing slurry between a polishing plate provided with a pad and the functional coating film, or (iii) by electrolyzing the functional coating film on the objective face placed opposite to an electrode face in an electrolyte solution at a predetermined voltage;(c) a step for mechanically removing the functional coating film adhered to the end face at an adequate stage; and(d) a step for washing and dry

Abstract: Device leads on a packaged integrated circuit are protected during a decapsulation process. A composite material such as wax is applied to coat the leads. At least a portion of a package containing the integrated circuit is then removed while the composite material is coating the leads, the coated leads being protected from fumes associated with the decapsulation process and less susceptible to deformation during handling. The composite material is then removed from the leads after the portion of the package is removed from the packaged device.

Abstract: A method of repairing severed or damaged data transmission lines of an imager provides a shunt path around the electrical defect in the data transmission line by means of a diode common transmission line. The repair shunt includes a first scan line segment, a common electrode segment, and a second scan line segment, which segments are fused together and to the data line having the electrical defect to bypass the electrical defect. The respective conductive lines are fused together with spot welds formed with the application of a laser. A repaired imager has a data line having an open circuit defect, with respective first and second portions of said data line being coupled to a repair shunt comprising an associated pixel scan line segment and a common electrode segment. In one embodiment of the present invention, a plurality of spot welds are provided in the imager array, each in its unwelded state but capable of being welded by the application of heat.

Abstract: A process for partially repairing defective Multi-Chip Module (MCM) Thin-Film (TF) wiring nets. The process comprises the steps of locating a short circuit between any two nets of the MCM, identifying a site to cut in one of the two nets, and deleting an internal portion of one of the two nets at the identified site.

Abstract: A method of manufacturing a semiconductor memory device includes a first step of forming a plurality of memory cells with a redundancy portion through fine patterning, a second step of searching a defect in masks used in the fine patterning and a third step of forming offset via holes so as to interconnect the redundancy portion instead of a defective portion identified by an inspection in non-fine patterning conducted after the fine patterning.

Abstract: A method for patterning a layer of photoresist includes the steps of 1) exposing the photoresist through a standard precision mask to define all possible cut points, 2) etching all possible cut points in a dielectric layer, 3) selectively exposing a second layer of photoresist with a non-precision targeting energy beam or mask to select the desired cut points. Consequently, no custom precision masks are required to pattern the various layers of photoresist during the fabrication of application specific integrated circuits (ASICs), thereby reducing both the lead-time and costs for manufacturing ASICS.

Abstract: A Process for graphically assisting the partial repair of defective MCM TF wiring nets. The process comprises the steps of inserting the wiring layer of the thin-film device in a tester, scanning the wiring layer of the thin-film device with the tester, identifying defects in the wiring nets, prioritizing the defects based on a function of each of the defective wiring nets, and repairing the defects based on priority.

Abstract: The specification describes a technique for repairing wafer fractures that occur during wafer fabrication. The fractured pieces are joined edge-to-edge at the fracture line and bonded with epoxy adhesive. The method succeeds because the dimensions of the fracture line after bonding is within the reregistration tolerance of commercial step-and-repeat cameras and the reregistration capability of the camera allows normal exposure of sites that do not intersect the fracture line.

Abstract: A method of removing thin film layers of a semiconductor component suitable for exposing a defective thin film layer for failure analysis. A focused ion beam is used instead of conventional mechanical polishing in non-selectively etching the thin film layers above a defective thin film layer in a semiconductor component. The focused ion beam has a better control over the etching thickness, so that a higher sample point success rate is obtained from a test specimen. Processing time is saved using the focused ion beam, which requires only a few minutes compared with hours needed by the conventional mechanical polishing method. The focused ion beam performs localized etching only, so that the thin film layers of other sample points in the test specimen will be unaffected. Therefore, a number of sample points can be prepared on the same test specimen at the same time.

Abstract: This invention provides a CMP (Chemical-Mechanical Polishing) method for controlling the polishing rate using ionized water and a CMP apparatus which employs the CMP method. A polishing pad is attached to a polishing disc. A semiconductor wafer is held by a wafer carrier placed above the polishing disc, and is pressed by the wafer carrier against the polishing pad which rotates together with the polishing disc. As a result, the semiconductor wafer is polished. The polishing is performed while a polishing slurry containing polishing particles is supplied to the polishing pad from a polishing slurry tank through a polishing-slurry supply pipe, and ionized water is supplied thereto through an ionized-water supply pipe. In the case of using alkaline ionized water as the ionized water, the polishing rate can be increased in a stable manner by increasing the pH value of alkaline ionized water, and can be reduced in a stable manner by reducing the pH value of alkaline ionized water.

Abstract: A method is disclosed for recovering surface-ready silicon carbide substrates from heteroepitaxial structures of Group III nitrides on silicon carbide substrates. The method comprises subjecting a Group III nitride epitaxial layer on a silicon carbide substrate to a stress that sufficiently increases the number of dislocations in the epitaxial layer to make the epitaxial layer subject to attack and dissolution in a mineral acid, but that otherwise does not affect the silicon carbide substrate, and thereafter contacting the epitaxial layer with a mineral acid to remove the Group III nitride while leaving the silicon carbide substrate unaffected.

Abstract: A process applicable to the restoration of defective or rejected semiconductor wafers to a defect-free form uses etchants and a variation of the Smart-Cut.RTM. process. Because of the use of the variation on the Smart-Cut.RTM. process, diffusion regions are removed without significantly affecting the specifications of the semiconductor wafer. Therefore, a defective or rejected wafer can be restored to near original condition for use in semiconductor manufacturing.

Abstract: A method and an apparatus for performing circuit edits through the back side of a flip-chip packaged integrated circuit die. In one embodiment, a circuit edit is achieved by exposing first and second circuit edit connection targets through a semiconductor substrate of the integrated circuit die from the back side. Next, an insulating layer is deposited over the first and second circuit edit connection targets and the exposed semiconductor substrate. Next, the circuit edit connection targets are re-exposed through the insulating layer and a conductor is deposited over the re-exposed circuit edit connection targets and the deposited insulating layer from the back side of the integrated circuit to couple together the circuit edit connection targets.

Abstract: A method for reproducing a PCB strip for semiconductor packages, wherein a poor quality PCB unit included in the PCB strip is replaced with a normal quality one, thereby achieving a reduction in the amount of package materials used and an improvement in the process efficiency. The invention also provides a method for fabricating semiconductor packages using the PCB strip reproduction method. A desired portion of a poor quality PCB unit included in a PCB strip is cut out in such a manner that a cutting opening having a peripheral edge extending along the singulation line of the poor quality PCB unit or along a region defined between the singulation line and anti-bending slots of the poor quality PCB unit. In the cutting opening, a separate good quality PCB unit member having the same shape and size as the cutting opening is then fitted. Thus, it is possible to simply and efficiently replace PCB units determined to be of poor quality with separate good quality PCB unit members, respectively.

Abstract: An integrated circuit chip package having an electrical contact configurable for either signal or power/ground and a method for constructing the integrated circuit chip package are disclosed. The integrated circuit chip package includes a substrate for supporting an integrated circuit chip and a dedicated conductor for supplying voltage to the integrated circuit chip. A configurable contact is attached to a surface of the substrate. The integrated circuit chip package further includes a signal connection for electrically connecting a signal connector of an integrated circuit chip and the configurable contact. A removable connector electrically connects the configurable contact and the dedicated conductor, thereby enabling the configurable contact to be configured as either a signal or power/ground contact depending upon the absence or presence of the electrical connection between the configurable contact and the dedicated conductor provided by the removable connector.

Abstract: An electronic device includes at least one chip connected to a circuit board. The chip includes a die and an encapsulant which is applied in a liquid phase and dries to a solid phase. A shell may be positioned over the chip and in some embodiments of the invention extends over the entire device. A dam is connected to the circuit board adjacent the die in at least one direction so as to restrain flow of the encapsulant toward the dam when the encapsulant is in the liquid phase. The dam may include an upper end at an elevation higher than the uppermost portion of the chip (which would usually be encapsulated), the dam acting as a standoff between the shell and the chip. The upper end of the dam may be constantly in contact with the shell or, alternatively, the upper end of the dam may be ordinarily not in contact with the shell, but comes into contact with the shell if the shell is compressed or flexed toward the chip. A single dam may surround the die (and chip structure after the encapsulant dries).

Abstract: The process described requires the formation of floating-gate non-volatile memory cells entirely similar in structure to those produced by known processes. The process comprises an annealing treatment at relatively low temperature (430.degree. C.) to repair damage due to plasma treatments. To obtain threshold voltage values for the cells close to the theoretical values, especially for cells with particularly extended interconnections, the cells are subjected to ultraviolet radiation before the annealing treatment, in order to neutralize any electrical charges present in the floating-gate electrodes of the cells.

Abstract: In forming an element isolating region in a silicon semiconductor layer of an SOI substrate, a silicon nitride film of a predetermined thickness is deposited over an oxide film formed on a SOI layer. The silicon nitride film is patterned in a design size of active regions, and side walls of a silicon nitride film are formed on the side surfaces of the patterned silicon nitride film. A first LOCOS process is carried out using the nitride film as an oxidation mask. A LOCOS film formed by the first LOCOS process is removed to form narrower concavities under the side walls. Then, another silicon nitride film is deposited, and is removed leaving portions thereof forming the concavities. Then, a second LOCOS process is carried out to form a LOCOS film as an element isolating region. The second LOCOS process uses the oxidation mask having the narrow cavities, so that stress at the boundary of the active region and the element isolation region is reduced, and the growth of bird's beaks can be suppressed.

Abstract: A method of removing a component bonded to a substrate utilizes a fixture having a bore therethrough which is aligned with a bore in the substrate. A screw is advanced in the bore in the fixture to cause a push pin to contact the component and force the component away from the substrate.

Abstract: A method of repairing an open circuit defect in a damaged address line in a thin film electronic imager array is provided that includes the steps of forming a repair area exposing the open circuit defect and portions of the damaged address line adjoining the defect, with a first protective layer disposed over the array surrounding the repair area; depositing a layer of conductive repair material over the array so that a portion of the conductive repair material is disposed in the repair area to form a repair shunt electrically connecting the portions of the address line adjoining the defect; forming a planarized second protective layer over the array; removing portions of the second protective layer to form a planarized surface on the array on which the conductive repair material is exposed except for the repair shunt underlying a plug portion of the second protective layer disposed over the repair area; removing the conductive repair material from the array surface except for the portion underlying the plug

Abstract: Described are methods of manufacturing large substrate capacitors for multi-chip module applications and the like using procedures compatible with common semiconductor fabrication procedures. A capacitor is formed where the top electrode thereof is divided into a plurality of segmented pads which are initially electrically isolated from one another. Each segmented pad forms a capacitor with the underlying dielectric layer and bottom capacitor electrode. Each segmented capacitor is electrically tested, and defective ones are identified. A conductive layer is thereafter formed over the segmented pads such that the conductive layer is electrically isolated from the pads of defective capacitors. The conductive layer electrically couples the good capacitors in parallel to form a high-value bypass capacitor which has low parasitic inductance. Large embedded MCM bypass capacitors can thereby be fabricated with minimal impact to the overall manufacturing yield.

Abstract: A process for manufacturing semiconductor memories which includes a method of quickly and effectively identifying which faulty memory cells are to be replaced by redundant memory structures. Redundant rows and columns are assigned to replace rows and columns with faulty cells in an iterative process. At each pass, one row or column is identified for replacement. A row or column is selected for replacement based on priorities assigned to the faulty cells within the rows and columns. The highest priority cell for a row is the one in a column with the fewest other faulty cells. Where multiple cells have the same highest row priority, the cell in a row with the most faulty cells is given a higher priority. A similar dual measure is used for assigning column priorities to cells. Once a highest priority row and column are identified, the single element with the highest priority is identified.

Abstract: A motor vehicle clutch has a friction wheel which includes a support disc, on which friction liners are attached by adhesive bonding to selected zones of the opposed faces of the support disc. These zones are prepared for application of the adhesive by subjecting them to selective scouring in which a liquid scouring agent is applied locally at selected points on each zone.

Abstract: A simplified crack stop formation compatible with shallow fuse etch processes which are utilized for modern low-cost redundancy designs using upper level metal fuses. A modified last level metallization (LLM) etch according to the invention allows a high-productivity single step bondpad/fuse/crack stop etch. The stack of metal films formed at the edge of the dicing channel is readily removed with a modified LLM etch prior to dicing causing the insulator films covering the dicing channel to be physically separated from the insulators coating the electrically active chip areas. The separation prevents cracks that could propagate through the insulators of the dicing channel in to the active chip.

Abstract: A direct chip attach to heatsink structure is shown and described which implements rework when the chip must be removed and replaced. A laminated heatsink includes a metal heatsink with a foil layer adhered to the chip attachment surface with the assembly secured to a carrier at a cutout opening therein that defines the chip attach site. The adhesive, either a dry film adhesive or a pressure sensitive adhesive, secures foil layer to heatsink and provides the interface of separation when a chip must be removed and replaced. By peeling the foil away from the heatsink, the foil, chip and non-reworkable die attach adhesive are removed as a unit, leaving no chip attach adhesive residue at the attachment site to be scraped or abraded away. The replacement chip can be installed either by directly installing with new die attach adhesive or by first restoring the foil layer prior to chip installation.

Abstract: A fast economical method for modification or repair of micro-circuit wiring patterns covered by a dielectric using a conducting bridge and focused ion beam technology. A conducting bridge is formed on the dielectric between selected points of the wiring pattern using a mask formed by assembling selectively shaped pieces of a transparent mask material such as plastic. The conducting bridge is formed from a material such as gold, copper, or platinum and has sufficient conductivity for long distances. A focused ion beam is then used to form contact holes in the dielectric thereby exposing selected regions of the wiring pattern for connection to the conducting bridge. Connecting material is then selectively deposited using focussed ion beam assisted chemical vapor deposition to connect the conducting bridge to the appropriate points of the wiring pattern. The length of the connecting material does not exceed about 200 micrometers and thus has adequate conductivity.

Abstract: A thin film electronic imager device has a repaired area between an upper conductive layer and an underlying component in the array in which portions of the upper conductive layer and a dielectric layer have been removed such that the upper conductive layer is electrically isolated from the underlying component. The repaired area has a bottom level having a surface comprising material of the underlying component and an intermediate step level having a surface comprising the dielectric layer material that extends around the periphery of the repaired area. The lateral dimension of the intermediate step level is greater than the lateral dimension of the bottom level such that the width of the intermediate level step surface is in the range between about 1 .mu.m and 3 .mu.m. Formation of the structure in the repair area is done by removing material by laser ablation to set back the upper conductive layer from the sidewall of the dielectric material in the region in which the defect was excised.

Abstract: Improved thin film transistors to reduce defects in the devices incorporating the transistors, including active matrix displays. A first improvement is accomplished by forming a dual insulator layer over the bottom metal layer, which can be the gate line and also the row line in an active matrix display. The first insulator layer is formed by anodizing the metal layer and the second insulator layer is deposited onto the first layer. The dual insulator structure layer can be reanodized to eliminate the effect of pinholes. A second improvement includes providing an interdigitated transistor structure to increase the channel width, minimize internal shorting and minimize the drain capacitance. The interdigitated structure includes at least one source or drain finger formed between at least two drain or source fingers, respectively. A shorted source finger can be disconnected to maintain an operative transistor.