Abstract: In order to prevent a decrease of yield due to a discontinuity of a wire or a short between upper and lower metal wires in production of a TFT matrix panel having pixel capacitors and TFTs and produce the TFT panel in a good yield without decrease of an aperture rate of the pixel capacitor portions even with increase in the size of the panel and with micronization of the pixel pattern, ends of bias lines on the opposite side to connection to a common electrode driver for application of bias are electrically connected to each other by a redundant wire.

Abstract: A test method provides a sample of wafer level defects most likely to cause yield loss on a semiconductor wafer subdivided into a plurality of integrated circuits (IC's). Defect size and location data from an inspection tool is manipulated in an algorithm based on defect sizes and geometry parameters. The defects are classified by defect size to form size based populations. The contribution of each size range of defect population to yield loss is calculated and random samples for review are selected from each defect size population. The number of samples from each size defect population is proportional to the predicted yield impact of each sample. The method is rapid and permits on-line process modification to reduce yield losses.

Abstract: A method includes removing at least a piece of a deposition chamber liner from a deposition chamber by passing it through a passageway to the deposition chamber through which semiconductor substrates pass into and out of the chamber for deposition processing. A replacement for the removed deposition chamber liner piece is provided into the chamber by passing the replacement through said passageway. A liner apparatus includes a plurality of pieces which when assembled within a selected semiconductor substrate deposition processor chamber are configured to restrict at least a majority portion of all internal wall surfaces which define said semiconductor substrate deposition processor chamber from exposure to deposition material within the chamber. At least some of the pieces are sized for passing completely through a substrates passageway to the chamber through which semiconductor substrates pass into and out of the chamber for deposition processing.

Abstract: A method for repairing an isolation dielectric damaged during a semiconductor fabrication process is disclosed in which a hard mask material is used to pattern a first material, the first material having openings therein exposing isolation regions comprising a first isolation dielectric layer. The method includes etching the hard mask material from the first material, wherein the etch creates gouges in the first isolation dielectric layer, and depositing a second layer of isolation dielectric over the first material, wherein the second isolation dielectric layer fills the gouges in the first isolation dielectric layer. The method further includes polishing on the second layer of isolation dielectric to remove the second layer of isolation dielectric from the first material.

Abstract: A wafer level packaging process for making flip-chips and integrated circuits formed are proposed. The process comprises in turn, providing a wafer, forming a protective material, bumping the wafer, removing the protective material, probing the wafer, laser repairing, and dicing the wafer. The laser repairing step is after bumping step. The protective material such as photoresist or metal layer is filled into the depression portions above the fuses for temporary protection of the fuses during bumping.

Abstract: A method for reducing microsteps on an epitaxial layer deposited on a polished semiconductor wafer substrate by post-epitaxial thermal oxidation. The method produces very smooth semiconductor wafers by performing the steps of depositing an epitaxial layer on a wafer substrate, oxidizing a top portion of the expitaxial layer, and removing the oxidized top portion. As a result, the wafer's surface presents little or no microsteps thereon.

Abstract: The invention includes a method of treating a predominantly inorganic dielectric material on a semiconductor wafer. A laser is utilized to generate activated oxygen species. Such activated oxygen species react with a component of the dielectric material to increase an oxygen content of the dielectric material. The invention also includes a method of forming a capacitor construction. A first capacitor electrode is formed to be supported by a semiconductor substrate. A dielectric material is formed over the first capacitor electrode. A precursor is provided at a location proximate the dielectric material, and a laser beam is focused at such location. The laser beam generates an activated oxygen species from the precursor. The activated oxygen species contacts the dielectric material. Subsequently, a second capacitor electrode is formed over the dielectric material.

Abstract: The invention includes a method of treating a predominantly inorganic dielectric material on a semiconductor wafer. A laser is utilized to generate activated oxygen species. Such activated oxygen species react with a component of the dielectric material to increase an oxygen content of the dielectric material. The invention also includes a method of forming a capacitor construction. A first capacitor electrode is formed to be supported by a semiconductor substrate. A dielectric material is formed over the first capacitor electrode. A precursor is provided at a location proximate the dielectric material, and a laser beam is focused at such location. The laser beam generates an activated oxygen species from the precursor. The activated oxygen species contacts the dielectric material. Subsequently, a second capacitor electrode is formed over the dielectric material.

Abstract: Provided is a method of fabricating and repairing ceramic components for semiconductor fabrication, through which erosion and polymer deposition occurring on ceramic components for semiconductor fabrication are decreased by modifying the dielectric surface of a component having an electrical insulation characteristic so that the ceramic components can be repaired after being used. The method includes activating a surface layer of a component, which is manufactured by sintering a ceramic, and depositing a dielectric coating layer on the surface layer of the ceramic component using a plasma spray process; when the dielectric coating layer is damaged as the ceramic component is used for semiconductor fabrication, removing the dielectric coating layer; and repairing the ceramic component by depositing a dielectric coating layer on the surface layer of the ceramic component from which the damaged dielectric coating layer has been removed.

Abstract: A system and method for repairing defects in semiconductor wafers utilizing a repair tool including a device for applying energy to obliterate defects at locations on the wafer, the method being a graphical approach implementing a graphical user interface (GUI) comprising a pixel screen display and comprising the steps of: via the interface, identifying a wafer defect to repair and enclosing the defect within a polygonal repair outline drawn using a default line thickness; graphically adjusting the line thickness to modify the enclosed polygonal repair outline area; automatically detecting one or more areas within an interior region of the modified polygonal repair outline area; and, scanning the modified polygonal repair outline, and for each pixel location inside the one or more detected areas, applying energy to the wafer coordinated to the pixel location for repairing the defect, whereby the identification of said pixel location is accomplished using standard graphical tools with minimal operator interven

Abstract: A method for re-forming a semiconductor layer of a thin film transistor-liquid crystal display device, including the steps of forming a gate electrode on a substrate, and forming a first gate insulation film on the gate electrode and the substrate; forming a semiconductor layer on the first gate insulation film; etching the semiconductor layer to remove the semiconductor layer if the formed semiconductor layer is defective; etching an upper portion of the first gate insulation film to a certain thickness damaged as the interface is exposed to the air by the etching of the semiconductor layer; forming a second gate insulation film on the remaining first gate insulation film; and forming a semiconductor layer on the second gate insulation film.

Abstract: The present invention includes methods to pre-erase non-volatile memory cells using an electrical erase signal prior to dividing a wafer into dies. Particular aspects of the present invention are described in the claims, specification and drawings.

Abstract: A system and method for repairing defects in semiconductor wafers utilizing a repair tool including a device for applying energy to obliterate defects at locations on the wafer, the method being a graphical approach implementing a graphical user interface (GUI) comprising a pixel screen display and comprising the steps of: via the interface, identifying a wafer defect to repair and enclosing the defect within a polygonal repair outline drawn using a default line thickness; graphically adjusting the line thickness to modify the enclosed polygonal repair outline area; automatically detecting one or more areas within an interior region of the modified polygonal repair outline area; and, scanning the modified polygonal repair outline, and for each pixel location inside the one or more detected areas, applying energy to the wafer coordinated to the pixel location for repairing the defect, whereby the identification of said pixel location is accomplished using standard graphical tools with minimal operator interven

Abstract: Substrate removal from a semiconductor chip having silicon-on-oxide (SOI) structure is enhanced via a method and system that provide a control for the removal process. According to an example embodiment of the present invention, a portion of substrate is removed from the back side of a semiconductor chip having a SOI structure and a backside opposite a circuit side. As the substrate is removed, secondary ions are sputtered from the back side. The sputtered ions are detected, and the substrate removal is controlled as a function of detected ions. In this manner, the portion of the substrate being removed can be detected and used to enhance the control of the substrate removal process, such as by detecting sputtered ions from the insulating portion of the SOI and using the insulating portion as an endpoint of the substrate removal process.

Abstract: A method of processing a semiconductor substrate to increase fracture strength and a semiconductor substrate formed by that method. In a preferred embodiment, the semiconductor substrate is utilized in a printhead. The semiconductor substrate has a feature such as an ink feed channel machined therein, and following machining the die is processed to remove material adjacent the machined feature to reduce micro-cracks or other defects that may have been created during the feature machining process. The crack containing material may be removed by several procedures. A preferred procedure is etching with a solution containing TMAH.

Abstract: Disclosed herein is a method for manufacturing semiconductor device and a method and apparatus for processing detected defect data, making it possible to quickly infer or determine a process and related manufacturing equipment that causes defects in a fabrication line of semiconductor devices, take remedy action, and achieve a constant and high yield. The method of the invention comprises quantitatively evaluating similarity of a defects distribution on a wafer that suffered abnormal occurrence of defects to inspection results for wafers inspected in the past, analyzing cyclicity of data sequence of evaluated similarity, evaluating relationship between the cyclicity of defects obtained from the analysis and the process method according to each manufacturing equipment in the fabrication line, and inferring or determining a causal process and equipment that caused the defects.

Abstract: An alignment apparatus which detects the position of an alignment mark on a wafer has a low-magnification sensing system including the first imaging optical system and a photoelectric conversion element, and a high-magnification sensing system including the second imaging optical system and a photoelectric conversion element. Detection light from an alignment mark is branched, thereby sensing the alignment mark simultaneously by the low- and high-magnification sensing systems. The positions of the alignment mark are respectively calculated on the basis of the obtained low- and high-magnification images. If the mark position calculated on the basis of the low-magnification image falls within a predetermined range, the mark position calculated on the basis of the high-magnification image is determined to be valid and adopted as the proper alignment mark position.

Abstract: A method for reworking integrated circuit (IC) wafers having copper-metallized bond pads exposed in protective overcoat openings and one or more bondable metal layers deposited onto the bond pads by a technology which may produce some parts with off-spec or missing depositions. After identifying the wafer with off-spec metal layers, a layer of glass buffer is deposited over those wafers, which also fill any missing depositions at least partially. The glass-covered surface is then chemically-mechanically polished until the off-spec metal layers and at least a portion of the protective overcoat are removed, without damaging the copper metallization. Finally, a fresh layer of protective overcoat is deposited, selectively opened to expose the bond pads, and provided anew with one or more bondable metal layers.

Abstract: A method for heat treatment of a silicon wafer in a reducing atmosphere through use of a rapid thermal annealer (RTA) is provided. In the method, the silicon wafer is heat-treated at a temperature of 1150° C. to 1300° C. for 1 sec to 60 sec in a mixture gas atmosphere of hydrogen and argon. Hydrogen is present in the mixture gas atmosphere in an amount of 10% to 80% by volume. Hydrogen is preferably present in the mixture gas atmosphere in an amount of 20% to 40% by volume. The method decreases COP density on the surface of the silicon wafer to thereby improve electrical characteristics, such as TZDB and TDDB, of the silicon wafer, suppresses the generation of slip dislocation to thereby prevent wafer breakage, and utilizes intrinsic advantages of the RTA, such as improvement in productivity and reduction in hydrogen gas usage.

Abstract: Method of forming a metal pattern on a dielectric substrate A method of reproducibly manufacturing circuit carriers with very fine circuit structures, more specifically with structure widths of 50 &mgr;m and less, is described in which a substrate provided with a base metal surface is provided, a layer of varnish is applied onto the substrate by an electrophoretic method, the layer of varnish is ablated in at least parts of the regions that do not correspond to the metal pattern to be formed, the base metal surface being laid bare, the bare base metal surface is etched, the layer of varnish being ablated by means of ultraviolet irradiation, more specifically with an ultraviolet laser beam.

Abstract: A method of manufacturing a flash memory device with a controllable amount of gate edge lifting including etching the ends of the tunnel oxide forming a cavity at each end of the tunnel oxide and anisotropically depositing and etching an oxide to form spacers on the sides of the gate stack. The spacers have a predetermined thickness that controls the amount of gate edge lifting. The predetermined thickness is determined during a characterization procedure that can be a computer modeling procedure or it can be determined empirically.

Abstract: A method for testing a semiconductor device comprises executing a function test on the semiconductor device, executing a DC characteristic test on the semiconductor device, executing a remedy determination process of the semiconductor device, and executing a remedy process on the semiconductor device. The remedy determination process is performed in parallel to the DC test.

Abstract: The present invention offers a mend method for breakage dielectric film, applied to the reworking of a substrate with a conductive layer and a first dielectric layer in which an in-film particle has been embedded. In the subsequent planarization, the particle causes the formation of a hole defect. The method features the steps of: forming a second dielectric layer on the first dielectric layer to cover the hole defect; forming an SOG layer on the second dielectric layer to repair the hole defect; partially etching back to level the SOG layer; and forming a third dielectric layer on the SOG layer. The present invention thus reworks the damaged dielectric layer by the SOG process.

Abstract: A method and apparatus for maintaining the state of a MEMS device in the event of a power failure are disclosed. The apparatus and method may be used with a MEMS device generally having one or more MEMS elements moveably coupled to a substrate that uses electrostatic clamping force to sustain the state of the MEMS element. According to the method, a capacitive or other charge-storing circuit is coupled between a clamping surface and an electrical ground. During normal operation, a clamping voltage is applied between the clamping surface and at least one MEMS element to retain the at least one MEMS element against the clamping surface. In the event of a power failure, the source of the clamping voltage and other circuit paths to ground are isolated from the clamping surface. The charge-storing circuit maintains an electric charge on the clamping surface.

Abstract: On a wafer that includes multiple distinct designs in each die region, a memory is included in each die region. The memory stores information specific to the design implemented in the same die region. Such stored information may include a circuit design identifier or a proprietary technology identifier. Such identifiers minimize IC confusion and aid in tracking usage of proprietary technology.

Abstract: Disclosed is a system and method for handling post epitaxial thermal oxidation. The method produces semiconductor wafers by performing the steps of forming a wafer substrate, depositing an epilayer on the substrate, oxidizing a top portion of the epilayer, and removing the oxidized top portion. As a result, the wafer's surface is very smooth, with little or no micro-steps thereon.

Abstract: A semiconductor memory chip has fuses and a redundancy memory cell which can replace a normal memory cell that is found defective by cutting off the fuses. If the normal memory cell is defective, the fuses are cut off thereby to connect the redundancy memory cell instead of the normal memory cell which is defective. The entire surface of the semiconductor memory chip is coated with a resist layer. The coated the resist layer is exposed at regions of the fuses to an energy beam, and then developed form a resist pattern. The semiconductor memory chip is etched at the regions using the resist pattern as a mask for thereby cutting off the fuses. The fuses may be spaced at intervals of 2 &mgr;m or smaller, and can be cut off without causing damage to a layer beneath the fuses.

Abstract: A method for reducing microsteps on an epitaxial layer deposited on a polished semiconductor wafer substrate by post-epitaxial thermal oxidation. The method produces very smooth semiconductor wafers by performing the steps of depositing an epitaxial layer on a wafer substrate, oxidizing a top portion of the epitaxial layer, and removing the oxidized top portion. As a result, the wafer's surface presents little or no microsteps thereon.

Abstract: A circuit assembly is formed with a polyimide coated lower SRAM die and an upper die resin bonded to the SRAM die. The repair access opening in the polyimide coating on the upper surface of the SRAM die is filled with polyimide for protection before attaching the upper die to the SRAM die. Embodiments of the present invention including positioning a solid piece of polyimide within the repair access opening or spraying a thin coating of polyimide over the opening and on the first polyimide coating.

Abstract: A particular portion of a damaged layer within a semiconductor substrate, which is likely to affect the performance of resulting semiconductor devices, is distinguished from the other negligible portions thereof and the depth of that non-negligible portion is detected. An Si substrate is placed on a stage, and a mercury electrode, which forms a Schottky barrier with the Si substrate, is brought into contact with the surface of the Si substrate. When a constant current is supplied from a constant current source between the mercury electrode and the Si substrate, charges are trapped at the trap centers in the damaged layer within the Si substrate. As a result, a potential on the conduction band rises near the surface of the Si substrate. And if the voltage between the electrode and the substrate is increased along with the potential rise, a constant current flows.

Abstract: A method of manufacturing an electronic component includes forming first, second, and third capacitors (260, 270, 280) and electrically testing the first, second, and third capacitors to characterize an etch process for a sacrificial layer. Each of the first, second, and third capacitors has different amounts of first and second electrically insulative materials.

Abstract: Methods for forming multiple dielectric layers at low temperatures include forming a number of metallic layers on a substrate and oxidizing the metallic layers to different dielectric oxides. Oxidation is performed one layer at a time, or all layers together. Dielectric layers thus formed have multiple different oxides in layers, reducing defects, providing high capacitance, and low leakage currents.

Abstract: A method for providing a low carbon and/or low oxygen containing conductive material includes providing a substrate assembly having a surface and providing a stream of a precursor containing conductive material to a region proximate the surface of the substrate assembly where the conductive material is to be deposited. A stream of reaction gas is also provided to the region proximate the surface of the substrate assembly where the conductive material is to be deposited. The reaction gas is one of an oxygen or hydrogen containing gas. A focused beam is scanned over the surface of the substrate assembly in the presence of the stream of precursor containing conductive material and the stream of the reaction gas to deposit the conductive material on the surface. The stream of the precursor containing conductive material may include a stream of a precursor containing one of platinum, palladium, rhodium, ruthenium, chromium, silver, and iridium; preferably platinum.

Abstract: A device repair process that includes removing a passivation polyimide layer. The passivation polyimide layer is removed using a first-half ash followed by a second-half ash. The device is rotated during the second-half ash. The device is then cleaned using sodium hydroxide (NaOH) and a subsequent light ash step is implemented. After the passivation polyimide layer is removed, a seed layer is deposited on the device. A photoresist is formed on the seed layer and bond sites are formed in the photoresist. Repair metallurgy is plated through the bond sites. The bond sites are plated by coupling the device to a fixture and applying the current for plating to the fixture. The contact between the device and the fixture is made though bottom surface metallurgy. After plating, the residual seed layer is removed and a laser delete process is implemented to disconnect and isolate the nets of the device.

Abstract: Within a method for electrical test testing a series of microelectronic fabrication die fabricated within a microelectronic fabrication substrate, there is first electrical probe tested the series of microelectronic fabrication die to determine at least one sub-series of electrically unacceptable microelectronic fabrication die. Each electrically unacceptable microelectronic fabrication die within the series of electrically unacceptable microelectronic fabrication die is then electrical probe retested after having repositioned an electrical probe head with respect to the electrically unacceptable microelectronic fabrication die.

Abstract: A method and apparatus for reducing plasma-induced charging damage in a semiconducting device are provided. The method includes exposing an article having a dielectric material susceptible to plasma-induced charging, to vacuum-ultraviolet (VUV) radiation of an energy greater than the bandgap energy of the dielectric material during or after plasma processing of the device. The plasma-induced charge is conducted from, or recombined at, the charging site.

Abstract: In a CVD method using a CVD system in which the inside of the vacuum container of the said CVD system is separated into a plasma generating space and a film forming space by a conductive partition wall having plural penetration holes, exciting radicals produced in the plasma generating space are introduced into the film forming space only through the said penetration holes, supplying material gas from outside into an inner space of the said partition wall, which is separated from the plasma generating space and communicating with the film forming space through plural diffusion holes, and introducing the said material gas into the film forming space through the said diffusion holes, and a film is formed on the substrate by the exciting radicals and material gas thus introduced into the film forming space, the invention is intended to provide a CVD method suited to mass production of oxide films, mainly to mass production of oxide films for gate having excellent characteristics.

Abstract: Method and apparatus are disclosed for protection of a circuit against process-induced electrical discharge. The method includes forming a diode in close proximity to a charge collector structure capable of exhibiting the antenna effect, and connecting the diode to the charge collector structure by means of local interconnect techniques during intermediate processing steps. Additionally, the diode may be formed beneath a connecting pad to reduce or eliminate antenna effect problems without significant loss of die area.

Abstract: An ion generator generates ions above a semiconductor wafer and the ions are directed towards a surface of a semiconductor wafer. The ions combine with static charges on the semiconductor wafer to thereby discharge the surface of the semiconductor wafer.

Abstract: Fiducial mark bodies are provided for use in CPB microlithography apparatus and methods. Such bodies are especially useful for attachment to the wafer stage of such apparatus, for measuring a distance between a reference position of the CPB-optical system of the apparatus and a reference position of an optical-based alignment sensor of the apparatus. The mark bodies provide improved accuracy of these and other positional measurements. A typical mark body is made of a substrate plate (e.g., quartz or quartz-ceramic) having a low coefficient of thermal expansion. Mark elements are defined on the substrate plate by a layer of heavy metal (e.g. are Ta, W, or Pt). The mark body includes a surficial or interior layer of an electrically conductive light metal that prevents electrostatic charging of the mark body and can be connected to ground.

Abstract: A process to remove a semiconductor die from a plastic package and then to reassemble the die in a high reliability hermetic package. The process is used to remove an already existing die using a unique disassembly and etching process and make the removed die more reliable by reattaching the die and rebonding all new die wires into either a hermetic package or a different type of package with a “bond-on-top-of-bond” technique. The original bondfoot on the removed die may be first preconditioned by a novel bond-flattening tool, which can be attached to the bond-head chuck of any wirebonder. Also, the die can be used in other applications with different pin-outs or configurations.

Abstract: A method of modifying a chip assembly substrate comprising the steps of:

Abstract: Damaged low-density silicon oxide-based films having an Si—O backbone are repaired using a method for driving a self-limiting healing process. According to an example embodiment of the present invention, a deposition precursor and an oxidizer are introduced to a damaged side wall region of a low-density silicon oxide-based film. The unstable damaged portion of the film reacts with the deposition precursor and a thin repair film is grown within the interfacial layer of the damaged film. The repair film provides a strengthened interface, protects the underlying sensitive material from further chemical damage, and can improve the ability to integrate the film.

Abstract: The present invention is directed to a process for reclaiming for reuse a single crystal silicon wafer removed from an aborted semiconductor device fabrication process. The process includes (a) subjecting the wafer to an oxide growth step to form an oxide layer having a thickness greater than 2 nanometers, (b) thinning the wafer by removing material from substantially the entire front surface to provide a thinned wafer having a thinned precipitate free zone, and (c) polishing the front surface of the thinned wafer to a specular finish.

Abstract: A manufacturing method of a semiconductor device to perform processing, including pre-processing and post-processing, on a semiconductor substrate, a characteristic of the processed semiconductor substrate is inspected, whether the semiconductor substrate complies with a predetermined standard is judged, and a semiconductor substrate not complying with the standard is re-processed so that the semiconductor substrate complies with the standard.

Abstract: A process capable of reclaiming used semiconductor wafers with a reduced metallic contamination level on wafer surfaces. The process comprises the steps of removing one or more surface layers of the substrate by chemical etching; scraping off one surface of the substrate in small amount by mechanical machining; removing a damage layer, which has occurred due to the mechanical machining, by chemical etching; and polishing the other surface of the substrate into a mirror finish.

Abstract: The present invention provides a method for identifying failure sites on a defective IC chip by utilizing a glass substrate equipped with a heating device and then coating a liquid crystal material layer on top. The liquid crystal device can be positioned in contact, or immediately adjacent to a surface of an IC device to be detected. After the liquid crystal temperature is raised to just below its transition temperature, a voltage signal can be fed into the IC device to trigger an overheating at a short or leakage to raise the liquid crystal material immediately adjacent to the short or leakage to a temperature above its transition temperature. Hot spots are thus produced to appear as bright spots for easy identification under an optical microscope.

Abstract: This marking method is carried out with an object to form a mark of high visibility on a surface of a metallic layer of such as a cover plate of a semiconductor device or the like without generating metallic debris or the like. According to this method, on a marking area of a metallic layer with a matte surface (Rmax: 0.5 to 5 &mgr;m), a laser beam is illuminated, thereby the metallic layer is melted, then re-solidified, thereby minute unevenness on the surface of the metallic layer is averaged and erased to be smooth. Thus formed marking portion reflects light specularly and is different in light reflectivity from an underlying portion which scatters light (diffuse reflection). Due to the difference of reflectivity, the marking portion can be visually discerned with excellency.

Abstract: Provided is a semiconductor structure that comprises a substrate; a conductor; and insulating layer separating the conductor from the substrate; and a removable conductive strap coupled to the conductor and the substrate for maintaining a common voltage between the conductor and substrate during ion beam and/or plasma processing; and a method for fabricating.

Abstract: Semiconductor processing methods and defect detection methods are described. In one embodiment, a semiconductor wafer in process is provided and a material is formed or deposited over the wafer. The material is discernably deposited over defective wafer surface areas and not appreciably deposited over non-defective wafer surface areas. Subsequently, the wafer surface areas are inspected to identify defective areas. In another embodiment, a substrate is provided having an exposed region containing surface defects. A defect-highlighting material is substantially selectively deposited over surface defects and not appreciably over other exposed regions. The substrate is subsequently inspected for the deposited defect-highlighting material. In yet another embodiment, a dielectric layer is formed over a substrate outer surface and the substrate is processed in a manner which can give rise to a plurality of randomly-distributed dielectric layer features.