Abstract: A multi-chip module (MCM) that fails testing after its assembly is repaired by generating a wire-bonding solution for a repair die during testing, storing the repair solution in a computer system in association with a unique ID code read from the MCM, and then using the repair solution at a wire-bonding station to correctly bond out a repair die for the MCM. The use of a stored repair solution at the wire-bonding station eliminates the need for a human operator to manually select the repair solution, and thus reduces the opportunity for error while shortening the length of time it takes to complete the repair process.

Abstract: The invention includes a semiconductor processing method of forming a die package. An insulative substrate is provided. Circuitry is over a topside of the substrate, and a slit extends through the substrate. A semiconductive-material-comprising die is provided beneath the substrate, and has a surface exposed through the slit in the substrate. The die has an edge. There is a gap between the die and an underside of the substrate. A radiation-curable material is injected through this slit and into the gap. Radiation is directed from over the edge to the gap to cure at least a portion of the radiation-curable material within the gap and thus form a dam which impedes non-cured radiation-curable material from flowing beyond the edge.

Abstract: A process to remove a semiconductor die from a plastic package and then to reassemble the die in a high reliability hermetic package. The process is used to remove an already existing die using a unique disassembly and etching process and make the removed die more reliable by reattaching the die and rebonding all new die wires into either a hermetic package or a different type of package with a “bond-on-top-of-bond” technique. The original bondfoot on the removed die may be first preconditioned by a novel bond-flattening tool, which can be attached to the bond-head chuck of any wirebonder. Also, the die can be used in other applications with different pin-outs or configurations.

Abstract: A system for repairable interconnect links using laser energy in a semiconductor integrated circuit die. The integrated circuit die is fabricated to include a plurality of interconnect links. At least a first and a second interconnect element are included in the integrated circuit die. The first and second interconnect elements are couple via an interconnect link. An anti-reflective layer is disposed on a surface above the interconnect link. The anti-reflective layer is configured to increase an amount of laser energy absorbed by the interconnect link in order to fuse the interconnect link, and thereby repair the integrated circuit die.

Abstract: A system and method for handling post epitaxial thermal oxidation. The method produces semiconductor wafers by performing the steps of forming a wafer substrate, depositing an epilayer on the substrate, oxidizing a top portion of the epilayer, and removing the oxidized top portion. As a result, the wafer's surface is very smooth, with little or no micro-steps thereon.

Abstract: A method and apparatus for repairing and improving the endurance characteristics of process damaged oxide film formed in a semiconductor device involving sonic annealing by vibrating or oscillating a wafer at a predetermined frequency, wave amplitude, and duration. A signal from a frequency generator is amplified by a voltage amplifier and then sent to a speaker or other acoustic device for the production of vibrating acoustical wave energy. This acoustical wave energy is then directed at a submicron device wafer during a specified time period in order to anneal the gate oxide and, thereby, improve the characteristics of the oxide film.

Abstract: A method of repairing a light emitting device which makes high quality image display possible even if a pin hole is formed during formation of an EL layer is provided. The method of repairing a light emitting device is characterized in that a reverse bias voltage is applied to an EL element at given time intervals to thereby reduce a current flowing into an EL element when the reverse bias voltage is applied to the EL element.

Abstract: A tester is designed to test a semiconductor memory device. First of all, the tester executes the function test of a memory cell array, which is among the function tests of the semiconductor device. Then, the tester performs redundancy analysis to replace an abnormal portion of the memory cell array with a spare row/column. The tester also executes the DC characteristic test of the semiconductor memory device and the function test of a peripheral circuit of the semiconductor memory device. The redundancy analysis is performed in parallel to both the DC characteristic test and the function test of the peripheral circuit.

Abstract: An automated optical inspection method detects width defects by employing locally applied width information. A defect determination is based on proximal width information of nearby parts of a conductor. Automated optical inspection systems inspect the surfaces of patterned objects for line width defects, employing line width data that is at least partially obtained automatically from analyzing a reference image of a non-defective patterned object.

Abstract: A reverse biasing apparatus is used to remove short-circuited portions in a solar battery module having multiple strings of solar cells each including a first electrode layer, a photovoltaic semiconductor layer and a second electrode layer formed on a glass substrate, by applying a reverse bias voltage between the electrodes of adjacent solar cells. The reverse biasing apparatus comprises probes to be in contact with the electrodes of adjacent three or more strings of solar cells, an actuator for actuating the probes up and down, and a relay switch for selecting, from the probes, a pair of probes for applying the reverse bias voltage between the electrodes of an arbitrary pair of adjacent solar cells. The use of the reverse biasing apparatus can ensure an efficient reverse biasing process on a solar battery module having integrated multiple strings of solar cells.

Abstract: A method for forming ICs comprising a highly-resistive or semi-insulating semiconductor substrate having a thin, low resistance active semiconductor layer thereon. In accordance with one embodiment of the method, the entire semiconductor substrate with at least partially prefabricated semiconductor devices disposed thereon is subjected to irradiation sufficient to impart high resistance throughout the substrate and active semiconductor layer. A thin, low resistance, active semiconductor layer is then generated on the substrate body by localized annealing. The (partially) prefabricated semiconductor devices are restored to operability by virtue of the annealing step as defects in the top insulating layers and properties of thin layers underneath the insulator-semiconductor interfaces are “healed.” The annealing step does not, however, heal the defects in the bulk substrate so that it remains semi-insulating.

Abstract: Damaged low-density silicon oxide-based films having an Si-O backbone are repaired using a method for driving a self-limiting healing process. According to an example embodiment of the present invention, a deposition precursor and an oxidizer are introduced to a damaged side wall region of a low-density silicon oxide-based film. The unstable damaged portion of the film reacts with the deposition precursor and a thin repair film is grown within the interfacial layer of the damaged film. The repair film provides a strengthened interface, protects the underlying sensitive material from further chemical damage, and can improve the ability to integrate the film.

Abstract: A method of manufacturing a semiconductor device having transistors with lightly doped diffusion regions (LDD) and self-aligned contacts to a reduced inter-gate spaces is disclosed. According to one embodiment, a method may include forming a gate and top insulating layer (004 and 005) on a semiconductor substrate (001). LDD regions (007) may be formed in a first area (Rpc) and source/drain regions (011) may be formed in a second area (Rmc). An etch stop layer (012), which may comprise silicon nitride, can then be formed. Sidewalls (006), which may comprise silicon dioxide, may be formed on gate layer (004) in a first area (Rpc), while inter-gate spaces in the second area (Rmc) may be filled with a sidewall layer. Source/drain regions (008) may then be formed in a first area (Rpc). A heat treatment can be applied that can restore etch resistance properties of the etch stop layer (012) which can be degraded when source/drain regions (008) are formed.

Abstract: Methods and apparatuses are disclosed that can introduce deliberate semiconductor film variation during semiconductor manufacturing to compensate for radial processing differences, to determine optimal device characteristics, or produce small production runs. The present invention radially varies the thickness and/or composition of a semiconductor film to compensate for a known radial variation in the semiconductor film that is caused by performing a subsequent semiconductor processing step on the semiconductor film. Additionally, methods and apparatuses are disclosed that can introduce deliberate semiconductor film variations to determine optimal device characteristics or produce small production runs. Introducing semiconductor film variations, such as thickness variations and/or composition variations, allow different devices to be made. A number of devices may be made having variations in semiconductor film.

Abstract: A method of reworking copper metallurgy on semiconductor devices which includes selective removal of insulator, selective removal of copper, non-selective removal of copper and insulator followed by the redeposition of an insulating copper barrier layer and at least one metallurgical interconnect layer.

Abstract: A semiconductor manufacturing apparatus for executing an exposure process upon filling a chamber, an illuminating optics unit and a projection optics unit with an inert gas is provided with a supply unit that supplies clean, dry air for raising the concentration of oxygen in a maintenance area, and with a sensor for sensing oxygen concentration or ozone concentration in the maintenance area. When maintenance is carried out, the supply unit is actuated to raise the oxygen concentration in the maintenance area, thereby assuring the safety of workers. A maintenance cover is provided with a door switch for sensing that the cover has been opened. Actuation of the supply unit is started in accordance with the state sensed by the door switch. Alternatively, the supply unit is actuated on the basis of an input ordering the start of a maintenance operation.

Abstract: A tester is designed to test a semiconductor memory device. First of all, the tester executes the function test of a memory cell array, which is among the function tests of the semiconductor device. Then, the tester performs redundancy analysis to replace an abnormal portion of the memory cell array with a spare row/column. The tester also executes the DC characteristic test of the semiconductor memory device and the function test of a peripheral circuit of the semiconductor memory device. The redundancy analysis is performed in parallel to both the DC characteristic test and the function test of the peripheral circuit.

Abstract: A decapsulation apparatus 100 has a laser 8 that removes plastic encapsulant from a device 24. Chamber 20 is sealed. Exhaust port 9 removes debris and fumes. The device 24 is positioned and scanned using an X,Y table 2. A hinged end 4 rotates the device to an acute angle of incidence with respect to a laser 8. Endpoint detector 10 senses the exposed integrated circuit and moves or shuts down the laser 8.

Abstract: A method for preparing for analysis the back side of a die in a package. The method comprises removing a selected portion of the package, whereby a selected area of the die is exposed and a cavity is formed in the package. Thereafter, a selected portion the die at the exposed area is removed. In a final phase, the exposed surface of the die is polished.

Abstract: The invention is an encapsulated circuit assembly including a chip; a substrate; at least one solder joint, wherein the solder joint spans between the chip and the substrate forming an electrically conductive connection between the chip and the substrate; and an encapsulant formed adjacent the solder joint, wherein the encapsulant comprises a hyperbranched polymer formed by the reaction of a monomer of the formula: (A)nRB, wherein A is a coupling group reactive with B, B is a coupling group reactive with A, n is greater than 1, and R is a group selected from the group consisting of an aromatic group, an aliphatic group, and mixtures thereof Also disclosed is a method of encapsulating a circuit assembly using the encapsulant of the invention.

Abstract: Method and apparatus are disclosed for protection of a circuit against process-induced electrical discharge. The method includes forming a diode in close proximity to a charge collector structure capable of exhibiting the antenna effect, and connecting the diode to the charge collector structure by means of local interconnect techniques during intermediate processing steps. Additionally, the diode may be formed beneath a connecting pad to reduce or eliminate antenna effect problems without significant loss of die area.

Abstract: A method and structure for providing top-to-bottom repair of a defective I/O net in a thin film transfer and join process. At least one C4 location and at least one capture pad are provided on a thin film substrate. The substrate is preferably ceramic. The C4 location of the defective net is severed by removal of a delete strap. The corresponding solder connection of the associated capture pad is also removed. A spare C4 location and capture pad are connected to provide a Z-repair line imbedded in the TF wiring structure. The Z-repair line is wired to the defective net.

Abstract: In order to prevent a decrease of yield due to a discontinuity of a wire or a short between upper and lower metal wires in production of a TFT matrix panel having pixel capacitors and TFTs and produce the TFT panel in a good yield without decrease of an aperture rate of the pixel capacitor portions even with increase in the size of the panel and with micronization of the pixel pattern, ends of bias lines on the opposite side to connection to a common electrode driver for application of bias are electrically connected to each other by a redundant wire.

Abstract: A method and apparatus for reducing plasma-induced charging damage in a semiconducting device are provided. The method includes exposing an article having a dielectric material susceptible to plasma-induced charging, to vacuum-ultraviolet (VUV) radiation of an energy greater than the bandgap energy of the dielectric material during or after plasma processing of the device. The plasma-induced charge is conducted from, or recombined at, the charging site.

Abstract: Channel doping and gate lithography are simulatneously performed by focusing an ion beam into the wafer through a positive or negative photoresist that is sensitive to the ion beam. Additional fabrication is then performed to provide a gate that is self-aligned with the doped channel.

Abstract: A method and system for removing a die from a semiconductor package is disclosed. The semiconductor package includes the die and a ceramic base. The die has a first face, a second face and a plurality of sides. The second face of the die is coupled with the ceramic base. The method and system include covering at least the first face and a portion of the plurality of sides of the die with a hard wax and encapsulating the hard wax and at least a first portion of the ceramic base in a resin. The method and system also include removing at least a second portion of the ceramic base to expose the second face of the die and removing the hard wax to free the die.

Abstract: A method and an apparatus providing a circuit edit structure to an integrated circuit enabling circuit edits to be performed through the back side of an integrated circuit die. In one embodiment, a passive diffusion is disposed in the substrate of a flip-chip packaged integrated circuit die. A plurality of contacts couple the passive diffusion to a signal line disposed in a dielectric isolation layer of the integrated circuit die. In another embodiment, the signal line includes an uninterrupted length of approximately 3.0 microns beneath a field oxide region in the integrated circuit die, which provides a circuit edit cut location. The passive diffusion and circuit edit cut locations may be accessed through the back side of the flip-chip packaged integrated circuit, which enable circuit edits to be performed on the flip-chip packaged integrated circuit.

Abstract: The present invention provides an improved fluorinated polymer encapsulant for protectively coating electronic devices in an electronic device module. Also provided is a method for applying and reworkably removing the same to and from the electronic device module. In one embodiment, a coating of a fluorinated polymer solution is applied to at least a portion of an electronic device module. The module is then baked to operably fix to it the fluorinated polymer coating.

Abstract: The present invention is directed to a method for post-manufacturing analysis of a semiconductor device including a die in a semiconductor device package. According to an example embodiment of the present invention, the package is removed and the die is exposed. Conductive ions are impregnated in a region of the die and a diode is formed. Using the formed diode, target circuitry within the die is analyzed. In this manner, a diode can be formed and used for purposes such as testing or repairing a die.

Abstract: A method for reducing imprint in a ferroelectric device which includes the steps of: applying a signal having a bipolar pulse shape for a predetermined time to the ferroelectric device; and decreasing the signal amplitude gradually in predetermined intervals of time and amplitude. Preferably, the bipolar shape signal is a sinusoidal wave, a square wave, or a sawtooth wave and the ferroelectric device is a capacitor or a memory cell in a computer. Also provided is an apparatus for reducing imprint in a ferroelectric device.

Abstract: A repairable integrated thin film transistor matrix substrate includes an insulated substrate, and a plurality of parallel gate bus lines and a plurality of accumulated capacitance bus lines formed on the insulated substrate. Each of the accumulated capacitance bus lines extend parallel to and between a pair of the gate bus lines, and has a plurality of auxiliary capacitance electrodes which extend from it. A first insulated film is provided on the gate and accumulated capacitance bus lines and the auxiliary capacitance electrodes. A plurality of operating films are formed on the first insulated film, and on each of the operating films, a corresponding thin film transistors are provided. At least two of the thin film transistors are electrically connected to each of the gate bus lines. Also included is a plurality of parallel drain bus lines which are provided substantially perpendicular to the gate and the accumulated capacitance bus lines on the first insulated film.

Abstract: A device repair process that includes removing a passivation polyimide layer. The passivation polyimide layer is removed using a first-half ash followed by a second-half ash. The device is rotated during the second-half ash. The device is then cleaned using sodium hydroxide (NaOH) and a subsequent light ash step is implemented. After the passivation polyimide layer is removed, a seed layer is deposited on the device. A photoresist is formed on the seed layer and bond sites are formed in the photoresist. Repair metallurgy is plated through the bond sites. The bond sites are plated by coupling the device to a fixture and applying the current for plating to the fixture. The contact between the device and the fixture is made though bottom surface metallurgy. After plating, the residual seed layer is removed and a laser delete process is implemented to disconnect and isolate the nets of the device.

Abstract: Methods are disclosed for performing reticle-substrate alignments in the context of charged-particle-beam (CPB) microlithography. More specifically, the subject methods pertain to detecting an amount of relative rotation between the “transfer-receiving” (e.g., substrate) side and the “transfer-originating” (e.g., reticle) side in one operation simply by detecting marks that are disposed near an axis of the CPB-optical system. A charged particle beam is passed through an alignment mark(s) situated relative to an alignment axis of the reticle and thus indicates reticle orientation. One or more respective index marks are defined on the substrate relative to an alignment axis of the substrate, thereby indicating substrate orientation. E.g., two index marks can be provided on the substrate, one convex and the other concave, but otherwise similarly shaped. The index marks can be situated linearly aligned with each other or at an angle to each other.

Abstract: Provided is a semiconductor structure that comprises a substrate; a conductor; and insulating layer separating the conductor from the substrate; and a removable conductive strap coupled to the conductor and the substrate for maintaining a common voltage between the conductor and substrate during ion beam and/or plasma processing; and a method for fabricating.

Abstract: A cathode-anode apparatus is constructed whereby the wafer under test, connected to a conducting wire, forms the cathode terminal and a copper plate, also connected to a conducting wire, forms the anode terminal. The wafer under test and the copper plate are immersed in a CuSO4—H2O solution. A positive dc voltage is applied to the copper plate; the dc current ionizes the CuSO4 solution and forms Cu2+ ions. These Cu2+ ions will diffuse to the wafer surface. Most of the Cu2+ ions will accumulate in and around defective contacts or vias in the semiconductor surface making these defective contacts or vias readily identifiable.

Abstract: A cathode-anode apparatus is constructed whereby the wafer under test, connected to a conducting wire, forms the cathode terminal and a copper plate, also connected to a conducting wire, forms the anode terminal. The wafer under test and the copper plate are immersed in a CuSO4—H2O solution. A positive dc voltage is applied to the copper plate, the dc current ionizes the CUSO4 solution and forms Cu2+ ions. These Cu2+ ions will diffuse to the wafer surface. Defects in the glassification surface will absorb most of the Cu2+ ions, concentrations of Cu2 ions will therefore from around these defects.

Abstract: A substrate removal approach involves sensing acoustic energy in an integrated circuit as a function of substrate in the integrated circuit being removed. According to an example embodiment of the present invention, a method for substrate removal includes removing a portion of substrate from the back side of a semiconductor chip circuitry near a circuit side and opposite the back side. The substrate is removed as a function of detected acoustic energy propagating through the device. The detected acoustic energy can be correlated to a parameter and used for controlling the substrate removal process, improving the ability to efficiently and accurately test semiconductor devices.

Abstract: The present invention provides a mounting structure for semiconductor devices which enables a semiconductor device, such as CSP/BGA, to be fixed to a circuit board. This invention also provides a mounting process for semiconductor devices.

Abstract: A method and apparatus for repair of a multi-chip module, such as a memory module, is provided where at least one redundant or auxiliary chip attach location is provided on the substrate of the multi-chip module. The auxiliary chip attach location preferably provides contacts for attachment of more than one type of replacement semiconductor chip. Accordingly, when one or more chips on the multi-chip module are found to be completely or partially defective, at least one replacement chip can be selected and attached to the auxiliary location to provide additional memory to bring the module back to its design capacity.

Abstract: A test method provides a sample of wafer level defects most likely to cause yield loss on a semiconductor wafer subdivided into a plurality of integrated circuits (IC's). Defect size and location data from an inspection tool is manipulated in an algorithm based on defect sizes and geometry parameters. The defects are classified by defect size to form size based populations The contribution of each size range of defect population to yield loss is calculated and random samples for review are selected from each defect size population. The number of samples from each size defect population is proportional to the predicted yield impact of each sample. The method is rapid and permits on-line process modification to reduce yield losses.

Abstract: A method for providing a low carbon and/or low oxygen containing conductive material includes providing a substrate assembly having a surface and providing a stream of a precursor containing conductive material to a region proximate the surface of the substrate assembly where the conductive material is to be deposited. A stream of reaction gas is also provided to the region proximate the surface of the substrate assembly where the conductive material is to be deposited. The reaction gas is one of an oxygen or hydrogen containing gas. A focused beam is scanned over the surface of the substrate assembly in the presence of the stream of precursor containing conductive material and the stream of the reaction gas to deposit the conductive material on the surface. The stream of the precursor containing conductive material may include a stream of a precursor containing one of platinum, palladium, rhodium, ruthenium, chromium, silver, and iridium; preferably platinum.

Abstract: The present invention relates, in one embodiment, to an integrated circuit including a first circuit structure, a first conductive bonding pad coupled to the first circuit structure, a second circuit structure, and a second conductive bonding pad coupled to the second circuit structure. The first conductive bonding pad is arranged to be separated from the second bonding pad by a gap having a gap dimension. The gap dimension is configured to be bridged by a wire bond, thereby permitting the wire bond to electrically couple the first conductive bonding pad with the second conductive bonding pad when the wire bond is coupled to the first bonding pad and the second bonding pad at the gap.

Abstract: A method for enhancing adhesion of photo-resist to silicon nitride surfaces is disclosed. An oxidation process is first performed on the surface of the semiconductor wafer using ozone-dissolved deionized water to transform most of the dangle bonds and Si-N bonds on the surface of the silicon nitride layer into Si-O bonds or Si-ON bonds. An HMDS layer is then formed on the surface of the silicon nitride layer. A photo-resist layer is next formed on the surface of the HMDS layer. Finally, a soft bake process is performed to remove solvents from the photo-resist layer and an exposure process is performed on the photo-resist layer to define a predetermined pattern in the photo-resist layer.

Abstract: A device repair process that includes removing a passivation polyimide layer. The passivation polyimide layer is removed using a first-half ash followed by a second-half ash. The device is then cleaned using sodium hydroxide (NaOH) and a subsequent light ash step is implemented. After the passivation polyimide layer is removed, a seed layer is deposited on the device. A photoresist is formed on the seed layer and bond sites are formed in the photoresist. Repair metallurgy is plated through the bond sites. The bond sites are plated by coupling the device to a fixture and applying the current for plating to the fixture. The contact between the device and the fixture is made though bottom surface metallurgy. After plating, the residual seed layer is removed and a laser delete process is implemented to disconnect and isolate the nets of the device.

Abstract: A method and apparatus for removing layers from a circuit side of a semiconductor die includes the use of a holder, for example a semiconductor wafer having an opening therein for receiving the semiconductor die. Additionally the holder can include one or more layers thereover which are removed at a similar rate as those layers which comprise the semiconductor die. A die is placed into the opening and a circuit side of the die is aligned with a front side of the holder, for example using a generally planar surface, and is secured to the holder with an adhesive material. Using a holder reduces uneven layer removal which is known to occur in conventional processing, for example excessive removal at the edges of the die. A potting jig which aids in aligning and securing the die to the holder is also described.

Abstract: A multi-chip module (MCM) that fails testing after its assembly is repaired by generating a wire-bonding solution for a repair die during testing, storing the repair solution in a computer system in association with a unique ID code read from the MCM, and then using the repair solution at a wire-bonding station to correctly bond out a repair die for the MCM.

Abstract: A method for removing short circuits in thin film solar cell elements during manufacturing by applying a pseudo-alternating voltage between the substrate side and the back electrodes of the solar cell elements. The waveform of the pseudo-alternating voltage may be a sinusoidal wave, a half-wave sinusoidal wave, a sawtooth wave, a square wave or the like. The peak voltage in the reverse direction is up to the reverse breakdown voltage of the solar cell element, and the waveform may either contain a small forward component or no fond component The peak voltage in Se reverse direction may also momentarily exceed the reverse breakdown voltage. The period of the pseudo-alternating voltage matches the tine constant of the solar cell element determined by the capacity and reverse resistance of the solar cell element.

Abstract: A multi-chip module (MCM) that fails testing after its assembly is repaired by generating a wire-bonding solution for a repair die during testing, storing the repair solution in a computer system in association with a unique ID code read from the MCM, and then using the repair solution at a wire-bonding station to correctly bond out a repair die for the MCM. The use of a stored repair solution at the wire-bonding station eliminates the need for a human operator to manually select the repair solution, and thus reduces the opportunity for error while shortening the length of time it takes to complete the repair process.

Abstract: The present invention provides a method of determining an endpoint of a reduction reaction of a metal deposited on a semiconductor wafer. The method comprises reducing an oxidized portion of the metal by subjecting the oxidized portion to a reducing agent that forms a reduction by-product and detecting the endpoint of the reduction reaction by monitoring a physical characteristic of either the reducing agent or the reduction by-product. This method is, therefore, particularly applicable in the fabrication of an integrated circuit device, such as a CMOS transistor, an NMOS transistor, a PMOS transistor, or a bi-polar transistor.

Abstract: An inspection pattern for a semiconductor device includes at least one inspection pattern groove and a dummy interconnection. The inspection pattern groove is formed in an interlevel insulating film or lower interconnection covering a surface of a semiconductor substrate. The dummy interconnection is formed to intersect the inspection pattern groove by burying a metal material in the inspection pattern groove. The dummy interconnection has a side wall which is exposed in the groove-like opening portion and which is inspected whether a void is present therein. An inspection method for a semiconductor device is also disclosed.