Abstract: The invention relates to a method for treating substrates (50) for microelectronics or optoelectronics, whereby said substrates comprise a useful layer (52) on at least one of the surfaces thereof. The inventive method includes a mechanical/chemical polishing step occurring on a bare surface (54) of the useful layer and is characterized in that it also comprises a post-curing step in a reductive atmosphere (100) before said polishing step occurs.

Abstract: A method for repairing a defective photomask having contained therein a minimum of one defect within a defective pattern employs a non-defective photomask for purposes of photoexposing a photoresist layer formed upon the defective photomask such as to form a patterned photoresist layer which leaves exposed the minimum of one defect. The minimum of one defect may then be repaired with the patterned photoresist layer in place as a repair mask. The method also provides for use of a non-defective pattern region within a defective photomask in a like fashion for repairing a defective pattern region within the same photomask. The method may be extended to repairing defective microelectronic products.

Abstract: High quality epitaxial layers of piezoelectric monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the piezoelectric monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying piezoelectric monocrystalline material layer.

Abstract: A system for fabricating semiconductor components includes mating mold cavity plates having mold cavities configured to mold body segments of the semiconductor components on either side of a leadframe. The mold cavity plates also include runners configured to direct molding compound between the mold cavities and into the corners of the mold cavities. The runners prevent trapped air from accumulating in the corners of the mold cavities, and eliminate the need for air vents in the corners. The mold cavity plates also include dummy mold cavities configured to form dummy segments on the leadframe, and air vents in flow communication with the dummy segments. The dummy mold cavities are configured to collect trapped air, and to direct the trapped air through the air vents to atmosphere. Each dummy mold cavity has only a single associated air vent, such that cleaning is facilitated, and flash particles from the air vents are reduced.

Abstract: The present invention provides a novel method for increasing the amount of deuterium incorporated into trap sites of a transistor device during a deuterium passivation anneal by electrically pre-stressing the fabricated device prior to a deuterium anneal. The method of the present invention equally applies to SOI and CMOS technology. As a result, the incorporation of more deuterium during a deuterium anneal in the process flow reduces the number of undesirable trap sites.

Abstract: An apparatus for repairing organic electroluminescent element defects is used to repair the electroluminescent element having a substantial short circuit portion/substantial short portions. The apparatus includes a transfer chamber, an electrical testing chamber and an insulator-forming chamber. In this case, the organic electroluminescent element is transferred in the transfer chamber. In the electrical testing chamber, a power supply source is provided to apply a current or voltage to the organic electroluminescent element, so that the short circuit portion or portions of the organic electroluminescent element is turned to an open circuit portion or open circuit portions. In the insulator-forming chamber, an insulator is formed on the open circuit portion or portions of the organic electroluminescent element. The invention also discloses an apparatus for repairing organic electroluminescent element defects, which further includes an optoelectrical detecting chamber.

Abstract: A new test structure to locate bridging defects in a conductive layer of an integrated circuit device is achieved. The test structure comprises a line comprising a conductive layer overlying a substrate. The line is coupled to ground. A plurality of rectangles comprises the conductive layer. The rectangles are not connected to the line or to other rectangles. Near edges of the rectangles and of the line are parallel. The rectangles are floating. The test structure is used with a passive voltage contrast test in a scanning electron microscope. A test structure and method to measure critical dimensions is disclosed.

Abstract: A multilayer ceramic repair process which provides a new electrical repair path to connect top surface vias. The repair path is established between a defective net and a redundant repair net contained within the multilayer ceramic substrate. The defective net and the repair net each terminate at surface vias of the substrate. A laser is used to form post fired circuitry on and in the substrate. This is followed by the electrical isolation of the defective net from the electrical repair structure and passivation of the electrical repair line.

Abstract: A system and method is provided herein to fabricate openings in a semiconductor topography using feed forward control of etch process parameters. In one embodiment, a method includes measuring one or more dimensional features of a semiconductor topography to obtain pre-etch values. The method also includes determining a statistical result of the pre-etch values and adjusting one or more processing parameters if the statistical result is less than a target value. Subsequently, the method includes etching the semiconductor topography based upon the statistical result to form one or more openings in the semiconductor topography. As such, the system and method described herein fabricates openings using feed forward control of the etch process parameters to compensate for structural variations within semiconductor topographies that may exist between wafer-to-wafer and/or between lot-to-lot.

Abstract: A method and an apparatus for sorting between actual and perceived errors related to processing of semiconductor wafers. A plurality of semiconductor wafers are processed. Fault data relating to the processed semiconductor wafers is acquired. A trend associated with the fault data is determined. A determination is made whether the fault data relates to an actual fault associated with the semiconductor wafers or to a calibration error, based upon the trend. A component is notified of the calibration error in response to the determination that the fault data relates to the calibration error.

Abstract: A test method provides a sample of wafer level defects most likely to cause yield loss on a semiconductor wafer subdivided into a plurality of integrated circuits (ICs). Defect size and location data from an inspection tool is manipulated in an algorithm based on defect sizes and geometry parameters. The defects are classified by defect size to form size based populations. The contribution of each size range of defect population to yield loss is calculated and random samples for review are selected from each defect size population. The number of samples from each size defect population is proportional to the predicted yield impact of each sample. The method is rapid and permits on-line process modification to reduce yield losses.

Abstract: This invention relates to epoxidized acetals and thioacetals, episulfidized acetals and thioacetals, thermosetting resin compositions based on such epoxidized acetals and thioacetals, episulfidized acetals and thioacetals, reaction products of which are controllably degradable when subjected to appropriate conditions.

Abstract: A method of specifying a Cu-contamination-causative step or steps in a Si wafer reclamation process including plural steps in combination, comprising: using p-type Si wafers, or p-type Si wafers and n-type Si wafers as monitor wafers, and performing a measuring operation for measuring the electrical resistance of the monitor wafers at least once before and after a single step or a series of successive steps during the Si wafer reclamation process. The present invention is capable of nondestructively, simply, and accurately detecting Cu that can contaminate Si wafers during a Si wafer reclamation process and is capable of specifying a Cu-contamination-causative process.

Abstract: First, a spin-on process is performed for forming a first dielectric layer over a plurality of metal interconnecting wires that are located on a semiconductor wafer. Then, an examining step is performed on the first dielectric layer, and the first dielectric layer is made to conform to a predetermined condition. Thereafter, an etching process is performed for completely removing the first dielectric layer. Subsequently, the semiconductor wafer is cleaned through use of a wet scrubber, and is dried. Finally, the spin-on process is re-performed for forming a second dielectric layer on the semiconductor wafer.

Abstract: An underfilling material for a semiconductor package holding semiconductor elements on a carrier substrate mounted on a circuit board, containing a one-pack type thermosetting urethane composition which preferably comprises a urethane prepolymer having a terminal isocyanate group, which is obtained by reacting a polyol with an excessive amount of a polyisocyanate, and a fine powder-coated curing agent comprising a curing agent which is in a solid state at room temperature and surface active sites of which are covered with a fine powder. This composition can achieve both the low temperature curing properties and the storage stability.

Abstract: A method for patching up thin-film transistor (TFT) circuit patterns on a display panel comprises the following steps. Firstly, a mask having an opening is placed above the display panel and the opening corresponds to the location of the cracks of the circuits on the display panel. Subsequently, a plasma sputtering procedure is performed to deposit a metal thin film through the opening of the mask on the display panel so as to connect the broken circuits. When the metal thin film is covered on a plurality of the circuits, a laser cut-out procedure is performed to cut apart the metal thin film on the plurality of the circuits so as to prevent the different circuits from short circuits.

Abstract: The manufacturing time of a mask is shortened. In a defect inspection of a mask having a light-shielding portion composed of a resist film, the presence or absence of defects, such as burr and film loss of a resist pattern on the mask, and foreign matters, etc. is inspected by reading optical information on either or both of reflection light and transmission light with respect to inspection light irradiated to the mask by the use of a foreign-matter inspection system. More specifically, in the inspection of the mask, it is possible to perform the defect inspection without performing a comparison inspection that requires a great amount of measuring time and advanced techniques. Therefore, the inspecting process of the mask can be simplified, and also the inspecting time of the mask can be shortened.

Abstract: A method and apparatus are provided for reworking of finishing metallurgy on pads of electronic components. The pads are copper or copper/nickel and have a layer of nickel thereon and an overlying layer of gold. The gold layer is removed first followed by the nickel layer and then the component is treated to remove etch and corrosion products. Media blasting is then used to restore the pads to their original condition as on prime parts. The pads are then replated using conventional nickel and gold plating solutions to form the reworked component.

Abstract: Provided is a method of fabricating and repairing ceramic components for semiconductor fabrication, through which erosion and polymer deposition occurring on ceramic components for semiconductor fabrication are decreased by modifying the dielectric surface of a component having an electrical insulation characteristic so that the ceramic components can be repaired after being used. The method includes activating a surface layer of a component, which is manufactured by sintering a ceramic, and depositing a dielectric coating layer on the surface layer of the ceramic component using a plasma spray process; when the dielectric coating layer is damaged as the ceramic component is used for semiconductor fabrication, removing the dielectric coating layer; and repairing the ceramic component by depositing a dielectric coating layer on the surface layer of the ceramic component from which the damaged dielectric coating layer has been removed.

Abstract: A method for reworking integrated circuit (IC) wafers having copper-metallized bond pads exposed in protective overcoat openings and one or more bondable metal layers deposited onto the bond pads by a technology which may produce some parts with off-spec or missing depositions. After identifying the wafer with off-spec metal layers, a layer of glass buffer is deposited over those wafers, which also fill any missing depositions at least partially. The glass-covered surface is then chemically-mechanically polished until the off-spec metal layers and at least portion a portion of the protective overcoat are removed, without damaging the copper metallization. Finally, a fresh layer of protective overcoat is deposited, selectively opened to expose the bond pads, and provided anew with one or more bondable metal layers.

Abstract: A method of repairing a light-emitting device capable of performing high quality image display even if pinholes are formed when forming an organic compound layer is provided. Device contamination can be prevented during repair. By applying a reverse bias voltage to an organic light emitting element during fixed periods of time, the electric current flowing in the EL element during application of the reverse bias voltage is reduced. Further, by forming a cathode so as to contain as little as possible of the high mobility ions Li and Na, contamination of the device when the reverse bias is applied can be prevented. It is preferable to use AlMg and MgAg for this type of cathode.

Abstract: The present invention is to provide a method for removing adhesive in a short time without requiring any solvent, a repair of which has conventionally been required for a long time, and there is provided a method for repairing a circuit connection part where circuit members having a large number of opposed circuits are connected electrically through an adhesive, wherein mutual joints at a circuit connection part requiring repair are separated, a basic material for transfer is bonded through a transfer adhesive for transfer to at least one circuit member where the adhesive remains and then the adhesive remaining on the circuit member and the transfer adhesive are removed from the circuit member along with the basic material for transfer.

Abstract: A simplified reticle removal system used with an electron beam system. The simplified reticle removal system includes a reticle chamber having an angled opening and a maintenance panel removably or pivotably attached thereto. The angled opening provides access to a reticle stage housed within the reticle chamber. The angled opening further permits removal of the reticle stage from the reticle chamber without having to disassemble and remove the optics system of the electron beam system. This reduces maintenance and repair costs, as well as reduces down time of the electron beam system.

Abstract: A method for forming a dielectric insulating layer with a reduced dielectric constant and increased hardness for semiconductor device manufacturing including providing a semiconductor wafer having a process surface for forming a dielectric insulting layer thereover; depositing according to a CVD process a carbon doped oxide layer the CVD process including an oregano-silane precursor having Si—O groups and Si—Ry groups, where R is an alkyl or cyclo-alkyl group and y the number of R groups bonded to Si; and, exposing the carbon doped oxide layer to a hydrogen plasma treatment for a period of time thereby reducing the carbon doped oxide layer thickness including reducing the carbon doped oxide layer dielectric constant and increasing the carbon doped oxide layer hardness.

Abstract: A method is described for repairing failure points, regions or locations in an electronic device to have a perfect function when a semiconductor device including an LCD or other electronic device has defects. Described is a method of transferring a single or multi-layer thin film piece into a recess with the physical properties of the thin film piece unchanged. An electronic device is described incorporating a substrate; and a plurality of thin films laminated on the substrate and part of the thin films are formed on a predetermined circuit pattern, wherein a transfer film for repairing a defect is fitted into a recess where the low layers of the thin films are exposed by removing part of a single or multi-layer thin films covering a defective portion included on the thin films and its surrounding portion.

Abstract: The present invention includes methods to pre-erase non-volatile memory cells using an electrical erase signal prior to dividing a wafer into dies. Particular aspects of the present invention are described in the claims, specification and drawings.

Abstract: The invention includes an engagement mechanism for semiconductor substrate deposition process kit hardware, including a body having a distal portion and a proximal portion. The body is sized for movement through a passageway of a semiconductor substrate deposition chamber through which semiconductor substrates pass into and out of the chamber for deposition processing. At least engager is mounted to the distal portion of the body The engager is sized for movement through said passageway with the body. The engager is configured to releasably engage a component of process kit hardware received within said chamber. The invention includes methods of replacing at least a portion of semiconductor substrate deposition process kit hardware. The invention includes methods of depositing materials over a plurality of semiconductor substrates. Other implementations are contemplated.

Abstract: A method of repairing a light-emitting device capable of performing high quality image display even if pinholes are formed when forming an organic compound layer is provided. Device contamination can be prevented during repair. By applying a reverse bias voltage to an organic light emitting element during fixed periods of time, the electric current flowing in the EL element during application of the reverse bias voltage is reduced. Further, by forming a cathode so as to contain as little as possible of the high mobility ions Li and Na, contamination of the device when the reverse bias is applied can be prevented. It is preferable to use AlMg and MgAg for this type of cathode.

Abstract: A method for replacing a microelectronic spring contact bonded to a terminal of a substrate is disclosed. The method includes removing the microelectronic spring contact from the terminal, such as by cutting the microelectronic spring contact in two adjacent to the terminal. Then, a bonding material, such as a solder paste, is applied to the terminal and a replacement spring contact is positioned on the bonding material. The bonding material is then cured to fix the replacement spring contact in place. The replacement spring contact includes a base configured to fit on or over any protruding material left on the terminal, and at least one resilient cantilever arm extending from the base. In an embodiment of the invention, the base includes at least two legs extending from the base in a direction opposite to the cantilever arm. In an alternative embodiment, the base of the replacement spring contact has a flat bottom, or one or more recesses to receive protrusions on the terminal.

Abstract: A method produces a semiconductor structure on a substrate. Then, a protective layer is applied to the semiconductor structure. To fabricate a further semiconductor structure that is to be formed on the substrate, intermediate processes, which lead to the formation of cracks in the protective layer, are carrier out. The protective layer is repaired with the aid of a repair layer.

Abstract: A domain controlled piezoelectnc single crystal is disclosed which uses a lateral vibration mode for an electromechanical coupling factor k31 not less than 70% and a piezoelectric constant −d31 not less than 1200 pC/N, with an electromechanical coupling factor k33 in the longitudinal vibration mode not less than 80% and a piezoelectric constant d33 not less than 800 pC/N. Also, a piezoelectric single crystal is disclosed which uses a high-performance longitudinal vibration mode with k31 not more than 30%. A fabrication method applies a DC electric field of 400 V/mm to 1500 V/mm for a maximum of two hours in a temperature range of 20° C. to 200° C. as polarization conditions in the thickness direction of the piezoelectric single crystal. The method can include cooling, or heating and cooling between temperature boundaries of rhombohedral and tetragonal crystals or between tetragonal and cubic crystals or within a cubic crystal temperature range.

Abstract: A laser repair facilitated pixel structure and repair method. The pixel structure includes a thin film transistor, a pixel electrode, and a conductive line. Control of the pixel structure is carried out through signals passing to a scan line and a data distributing line. The conductive line is underneath the data distributing line. The conductive line has a connective section and a repair section at each end of the connective section. Each repair section occupies an area greater than the data distributing line. A broken data distributing line is repaired through the formation of an electrical connection between the repair sections at each end of the conductive line and the data distributing line.

Abstract: A new test structure to locate bridging defects in a conductive layer of an integrated circuit device is achieved. The test structure comprises a line comprising a conductive layer overlying a substrate. The line is coupled to ground. A plurality of rectangles comprises the conductive layer. The rectangles are not connected to the line or to other rectangles. Near edges of the rectangles and of the line are parallel. The rectangles are floating. The test structure is used with a passive voltage contrast test in a scanning electron microscope. A test structure and method to measure critical dimensions is disclosed.

Abstract: Multi-chip module systems and method of fabrication thereof wherein the equivalent of a failed die of a multi-chip module (MCM) is added to the module in a vacancy position previously constructed with appropriate electrical connections. A variety of different dice may be attached to the same vacancy position of an MCM by means of adapters, wherein each adapter has the same footprint, but different adapters are capable of accommodating different numbers and types of dice.

Abstract: A substrate is provided with a plurality of regions, at least one of which is operationally redundant. An integrated circuit to be placed onto the substrate has a plurality of functional units that are designed to be interchangeable. The integrated circuit is tested for defects and, if a functional unit is found to be defective, then the integrated circuit is oriented (e.g., rotated or translated) with respect to the substrate such that the defective functional unit overlies the operationally redundant region of the substrate. A functional association is then formed between the remaining regions of the substrate and the non-defective functional units of the integrated circuit. Such functional association may be achieved by connecting each pair of unit and region. In this way, an integrated circuit with defective functional unit need not be discarded.

Abstract: A method for circuit modification of an microelectronic chip having at least one conductor in an organic dielectric, includes applying a protective inorganic surface layer on top of the organic dielectric, forming at least one window in the protective inorganic surface layer to selectively expose the underlying organic dielectric, etching the organic dielectric in the window area to selectively remove the organic dielectric adjacent to the conductor, and performing at least one process that modifies the conductor.

Abstract: A method of manufacturing a magnetic random access memory for excluding stress-induced defects in memory cells. The method is composed of forming a first magnetic film over a substrate, forming a tunnel insulating film on the first magnetic film such that the tunnel insulating film has a curvature, forming a second magnetic film on the tunnel insulating film, and etching the first magnetic film, the tunnel insulating film and the second magnetic film to form a memory cell. The etching is executed such that the curvature is excluded from the memory cell.

Abstract: A method of repairing a semiconductor chip containing copper is taught, whereby copper is selectively removed from the chip. The method involves processing the chip inside a chamber in which the chip is exposed to various gases and an energy source, such as a focused ion beam. To the extent the chip may have non-copper materials, such as nitride and oxide layers, on top of the copper that is to be removed, those non-copper materials will first be selectively removed. Such removal typically results in a hole (a so-called “elevator shaft”) leading to the copper that is to be removed. Next, the method teaches the introduction of a combination of nitrogen and oxygen into the chamber and the directing of the ion beam at the spot where the copper is to be removed. In this manner, the copper on the chip is cleanly and reliably removed, without causing damage to the processing chamber.

Abstract: Disclosed is a layer to electrically connect targets during a circuit edit of an integrated circuit and systems and methods for forming the layer. The layer contains a conductive material, such as gold or another metal, which has been physically deposited by sputtering, thermal evaporation, and other physical deposition technique.

Abstract: Computer programs and computer-implemented methods for predicting from first principles the behavior of dopants and defects in the processing of electronic materials. The distribution of dopant and defect components in a substrate lattice is predicted based on external conditions and fundamental data for a set of microscopic processes that can occur during material processing operations. The concentration behavior of one or more fast components is calculated in two stages, by solving a first relationship for a time period before the fast component reaches a pseudo steady state at which the concentration of the fast component is determined by concentrations of one or more second components, and by solving a second relationship for a time period after the first component reaches the pseudo steady state. Application of these methods to modeling ultrashallow junction processing is also described.

Abstract: A resist pattern formation method is characterized in that, after a resist pattern is formed on a wafer, a residue generated between resist sidewalls forming the resist pattern is irradiated with an electron beam under a reduced pressure. It is also preferable to detect the residue with pattern defect inspection equipment, and irradiate the detected residue site with an electron beam under a reduced pressure using an electron microscope. The reduced pressure is preferably equal to or lower than 5.0×102 Pa, and an acceleration voltage is preferably equal to or lower than 1200 V. A manufacturing method of a semiconductor device according to the present invention uses the above-described formation method to form a resist pattern. Thus, the residue generated between resist sidewalls can be removed without varying a dimension of a resist pattern spacing.

Abstract: A nonvolatile read-only memory device, wherein a word line is on a substrate and the word line includes a metal layer a polysilicon line. A trapping layer is further located between the word line and the substrate. A polysilicon protection line is formed over the substrate and the polysilicon protection line connects the word line and a grounded doped region in the substrate, wherein the resistance of the polysilicon protection line is higher than that of the word line.

Abstract: A method of reworking BEOL (back end of a processing line) metallization levels of damascene metallurgy comprises forming a plurality of BEOL metallization levels over a substrate, forming line and via portions in the BEOL metallization levels, selectively removing at least one of the BEOL metallization levels to expose the line and via portions, and replacing the removed BEOL metallization levels with at least one new BEOL metallization level, wherein the BEOL metallization levels comprise a first dielectric layer and a second dielectric layer, and wherein the first dielectric layer comprising a lower dielectric constant material than the second dielectric layer.

Abstract: A method of conducting a laser repair operation. A silicon wafer has a plurality of chips thereon. Each chip has a plurality of bonding pads, a plurality of testing pads, a plurality of fuses and a passivation layer for protecting the chip. The passivation layer exposes the bonding pads and the testing pads. A bump-forming process is conducted to form a bottom metallic layer and a bump sequentially over each bonding pad. Only a bottom metallic layer is formed over each testing pad. The bumps axe formed, for example, by electroplating or printing. Testing is carried out by probing various bottom metallic layers above the testing pads. Finally, a laser repair is conducted.

Abstract: A method of conducting a laser repair operation. A silicon wafer has a plurality of chips thereon. Each chip has a plurality of bonding pads, a plurality of testing pads, a plurality of fuses and a passivation layer for protecting the chip. The passivation layer exposes the bonding pads an the testing pads. A bump-forming process is conducted to form a bottom metallic layer and a bump sequentially over each bonding pad. Only a bottom metallic layer is formed over each testing pad. The bumps are formed, for example, by electroplating or printing. Testing is carried out by probing various bottom metallic layers above the testing pads. Finally, a laser repair is conducted.

Abstract: An integrated circuit includes first and second diodes that are electrically connected to a conductive line in antiparallel, to dissipate both positive and negative charges on the conductive line during plasma processing. The integrated circuit also includes a fuse for disconnecting one of the first and second diodes from the conductive line after the plasma processing, to thereby allow conduction of one of positive and negative charge on the conductive line after the plasma processing. Accordingly, integrated circuits are fabricated by forming a conductive line on an integrated circuit substrate and first and second diodes in the integrated circuit substrate that are electrically connected to the conductive line in antiparallel. Then, plasma processing is performed on the integrated circuit substrate including the conductive line and the first and second diodes, such that the first and second diodes dissipate both positive and negative charges on the conductive line during the plasma processing.

Abstract: The present invention is directed to a method of forming an FeRAM integrated circuit, which includes performing a capacitor stack etch to define the FeRAM capacitor. The method comprises etching a PZT ferroelectric layer with a high temperature BCl3 etch which provides substantial selectivity with respect to the hard mask. Alternatively, the PZT ferroelectric layer is etch using a low temperature fluorine component etch chemistry such as CHF3 to provide a non-vertical PZT sidewall profile. Such a profile prevents conductive material associated with a subsequent bottom electrode layer etch from depositing on the PZT sidewall, thereby preventing leakage or a “shorting out” of the resulting FeRAM capacitor.

Abstract: Within a method for electrical test testing a series of microelectronic fabrication die fabricated within a microelectronic frabrication substrate, there is first electrical probe tested the series of microelectronic fabrication die to determine at least one sub-series of electrically acceptable microelectronic fabrication die. Each electrically acceptable microelectronic fabrication die within the at least one sub-series of electrically acceptable microelectronic fabrication die is then electrical probe retested, but electrically unacceptable microelectronic fabrication die within corresponding sub-series of electrically unacceptable microelectronic fabrication die are not.

Abstract: A process of reclaiming a semiconductor wafer 10 comprises the steps of a) removing films of foreign matter from the surface of the wafer 10 by etching, b) polishing opposite sides of the wafer 10 between contra-rotating polishing means 26, 28 to remove doped and diffused regions in the surface of the wafer substrate, c) rendering matt at least a portion of one only of the polished major surfaces of the wafer, d) cleaning the major surfaces of the wafer; and e) drying the wafer. The wafer is not damaged because no abrasive grinding is used to remove the doped and diffused regions and the step of rendering matt enables the wafers to be subsequently processed using handling and processing apparatus which relies on a difference in finish to determine the correct side of the wafer to be processed.

Abstract: Laser Programming of Integrated Circuits. The invention relates to the laser adjustment or laser programming of laser fuses of an integrated circuit on a chip, with laser light, the integrated circuit having a plurality of laser fuses and being connected to a plurality of contact pads on the chip, and the chip being covered with a polymer layer which has at least windows on the plurality of contact pads, and comprising at least one wiring interconnect on the polymer layer which is electrically connected to at least one of the plurality of contact pads and ends at a predetermined location on a surface of the chip.