Using Same Conductivity-type Dopant Patents (Class 438/521)
  • Patent number: 9006024
    Abstract: In a semiconductor device in which transistors are formed in a plurality of layers to form a stack structure, a method for manufacturing the semiconductor device formed by controlling the threshold voltage of the transistors formed in the layers selectively is provided. Further, a method for manufacturing the semiconductor device by which oxygen supplying treatment is effectively performed is provided. First oxygen supplying treatment is performed on a first oxide semiconductor film including a first channel formation region of a transistor in the lower layer. Then, an interlayer insulating film including an opening which is formed so that the first channel formation region is exposed is formed over the first oxide semiconductor film and second oxygen supplying treatment is performed on a second oxide semiconductor film including a second channel formation region over the interlayer insulating film and the exposed first channel formation region.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: April 14, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kengo Akimoto
  • Publication number: 20150034970
    Abstract: A semiconductor device of the present invention includes a semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode being in contact with a surface of the semiconductor layer. The semiconductor layer includes a drift layer that forms the surface of the semiconductor layer and a high-resistance layer that is formed on a surface layer portion of the drift layer and that has higher resistance than the drift layer. The high-resistance layer is formed by implanting impurity ions from the surface of the semiconductor layer and then undergoing annealing treatment at less than 1500° C.
    Type: Application
    Filed: May 16, 2012
    Publication date: February 5, 2015
    Applicant: ROHM CO., LTD.
    Inventors: Masatoshi Aketa, Yuta Yokotsuji
  • Publication number: 20140284621
    Abstract: A semiconductor device of an embodiment includes an n-type SiC impurity region containing a p-type impurity and an n-type impurity. Where the p-type impurity is an element A and the n-type impurity is an element D, the element A and the element D form a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus). The ratio of the concentration of the element A to the concentration of the element D in the above combination is higher than 0.40 but lower than 0.95, and the concentration of the element D forming the above combination is not lower than 1×1018 cm?3 and not higher than 1×1022 cm?3.
    Type: Application
    Filed: March 12, 2014
    Publication date: September 25, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo SHIMIZU, Johji Nishio, Chiharu Ota, Takashi Shinohe
  • Publication number: 20140284622
    Abstract: A semiconductor device of an embodiment includes a p-type SiC impurity region containing a p-type impurity and an n-type impurity. Where the p-type impurity is an element A and the n-type impurity is an element D, the element A and the element D form a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus). The ratio of the concentration of the element D to the concentration of the element A in the above combination is higher than 0.33 but lower than 0.995, and the concentration of the element A forming part of the above combination is not lower than 1×1018 cm?3 and not higher than 1×1022 cm?3.
    Type: Application
    Filed: March 12, 2014
    Publication date: September 25, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo SHIMIZU, Takashi Shinohe, Johji Nishio, Chiharu Ota
  • Patent number: 8822315
    Abstract: A method is disclosed for treating a silicon carbide substrate for improved epitaxial deposition thereon and for use as a precursor in the manufacture of devices such as light emitting diodes. The method includes the steps of implanting dopant atoms of a first conductivity type into the first surface of a conductive silicon carbide wafer having the same conductivity type as the implanting ions at one or more predetermined dopant concentrations and implant energies to form a dopant profile, annealing the implanted wafer, and growing an epitaxial layer on the implanted first surface of the wafer.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: September 2, 2014
    Assignee: Cree, Inc.
    Inventors: Davis Andrew McClure, Alexander Suvorov, John Adam Edmond, David Beardsley Slater, Jr.
  • Publication number: 20130214291
    Abstract: As viewed along a normal to the principal surface of a substrate 101, this semiconductor element 100 has a unit cell region 100ul and a terminal region 100f located between the unit cell region and an edge of the semiconductor element. The terminal region 100f includes a ring region 103f of a second conductivity type which is arranged in a first silicon carbide semiconductor layer 102 so as to contact with a drift region 102d. The ring region includes a high concentration ring region 103af which contacts with the surface of the first silicon carbide semiconductor layer and a low concentration ring region 103bf which contains an impurity of the second conductivity type at a lower concentration than in the high concentration ring region and of which the bottom contacts with the first silicon carbide semiconductor layer. A side surface of the high concentration ring region 103af contacts with the drift region 102d.
    Type: Application
    Filed: October 27, 2011
    Publication date: August 22, 2013
    Applicant: PANASONIC CORPORATION
    Inventors: Masao Uchida, Koutarou Tanaka
  • Patent number: 8008140
    Abstract: It is an object of the present invention to manufacture a TFT having a small-sized LDD region in a process with a few processing step and to manufacture TFTs each having a structure depending on each circuit separately. According to the present invention, a gate electrode is a multilayer, and a hat-shaped gate electrode is formed by having the longer gate length of a lower-layer gate electrode than that of an upper-layer gate electrode. At this time, only the upper-layer gate electrode is etched by using a resist recess width to form the hat-shaped gate electrode. Accordingly, an LDD region can be formed also in a fine TFT; thus, TFTs having a structure depending on each circuit can be manufactured separately.
    Type: Grant
    Filed: October 24, 2005
    Date of Patent: August 30, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mayumi Yamaguchi, Atsuo Isobe, Satoru Saito
  • Patent number: 7973360
    Abstract: An integrated circuit device comprising a diode and a method of making an integrated circuit device comprising a diode are provided. The diode can comprise an island of a first conductivity type, a first region of a second conductivity type formed in the island, and a cathode diffusion contact region doped to the second conductivity type disposed in the first region. The diode can also comprise a cathode contact electrically contacting the cathode diffusion contact region, an anode disposed in the island, an anode contact electrically contacting the anode, and a first extension region doped to the first conductivity type disposed at a surface junction between the first region and the island.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: July 5, 2011
    Assignee: Intersil Americas Inc.
    Inventor: James Douglas Beasom
  • Patent number: 7879704
    Abstract: A memory function body has a medium interposed between a first conductor (e.g., a conductive substrate) and a second conductor (e.g., an electrode) and consisting of a first material (e.g., silicon oxide or silicon nitride). The medium contains particles. Each particle is covered with a second material (e.g., silver oxide) and formed of a third material (e.g., silver). The second material functions as a barrier against passage of electric charges, and the third material has a function of retaining electric charges. The third material is introduced into the medium by, for example, a negative ion implantation method.
    Type: Grant
    Filed: February 13, 2007
    Date of Patent: February 1, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Nobutoshi Arai, Hiroshi Iwata, Seizo Kakimoto
  • Patent number: 7790586
    Abstract: An impurity region is formed in a surface of a substrate by exposing the substrate to a plasma generated from a gas containing an impurity in a vacuum chamber. In this process, a plasma doping condition is set with respect to a dose of the impurity to be introduced into the substrate so that a first one of doses in a central portion and in a peripheral portion of the substrate is greater than a second one of the doses during an initial period of doping, with the second dose becoming greater than the first dose thereafter.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: September 7, 2010
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Sasaki, Katsumi Okashita, Hiroyuki Ito, Bunji Mizuno
  • Patent number: 7759728
    Abstract: An integrated circuit device comprising a diode and a method of making an integrated circuit device comprising a diode are provided. The diode can comprise an island of a first conductivity type, a first region of a second conductivity type formed in the island, and a cathode diffusion contact region doped to the second conductivity type disposed in the first region. The diode can also comprise a cathode contact electrically contacting the cathode diffusion contact region, an anode disposed in the island, an anode contact electrically contacting the anode, and a first extension region doped to the first conductivity type disposed at a surface junction between the first region and the island.
    Type: Grant
    Filed: May 6, 2008
    Date of Patent: July 20, 2010
    Assignee: Intersil Americas Inc.
    Inventor: James Douglas Beasom
  • Patent number: 7732246
    Abstract: A method of fabricating a vertical CMOS image sensor is disclosed, to improve the integration with the decrease in size of pixel by minimizing the lateral diffusion, in which phosphorous and arsenic ions are implanted while controlling the dose and energy, the method including forming a first photodiode in a semiconductor substrate; forming a first epitaxial layer on the semiconductor substrate; forming a first plug by sequentially implanting first and second ions in the first epitaxial layer; forming a second photodiode in the first epitaxial layer; forming a second epitaxial layer in the first epitaxial layer; forming an isolation area in the second epitaxial layer; and forming a third photodiode and a second plug in the second epitaxial layer.
    Type: Grant
    Filed: December 6, 2005
    Date of Patent: June 8, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Sang Gi Lee
  • Patent number: 7598162
    Abstract: It is an object to provide a method of manufacturing a semiconductor device capable of forming a MOS transistor of high performance, comprising the steps of forming a gate electrode on a semiconductor substrate via a gate-insulating film (step S1), introducing a impurity into the semiconductor substrate using the gate electrode as a mask (step S7), introducing a diffusion-controlling substance into the semiconductor substrate to control the diffusion of the impurity (step S8), forming a side wall-insulating film on each side surface of the gate electrode (step S9), deeply introducing impurity into the semiconductor substrate using the gate electrode and the side wall-insulating film as masks (step S10), activating the impurity by the annealing treatment using a rapid thermal annealing method (step S11), and further activating the impurity by the millisecond annealing treatment (step S12).
    Type: Grant
    Filed: September 26, 2006
    Date of Patent: October 6, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Tomonari Yamamoto, Tomohiro Kubo
  • Patent number: 7507646
    Abstract: With conventional device, the quantity of complex defects differs with each semiconductor device because the concentration of impurities intrinsically contained differs for each silicon wafer. Consequently, there is an undesirable variation in characteristics among the semiconductor devices. The invention provides a method for manufacturing PIN type diode which comprises an intermediate semiconductor region in which complex defects are formed. The method comprises introducing impurities (for example, carbon), which are the sane kind of impurities intrinsically contained in the intermediate semiconductor region, into the intermediate semiconductor region, and irradiating the intermediate semiconductor region with helium ions to form point defects.
    Type: Grant
    Filed: May 19, 2006
    Date of Patent: March 24, 2009
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Shinya Yamazaki, Tomoyoshi Kushida, Takahide Sugiyama
  • Patent number: 7410860
    Abstract: Apparatus and Methods for the self-alignment of separated regions in a lateral MOSFET of an integrate circuit. In one embodiment, a method comprising, forming a relatively thin dielectric layer on a surface of a substrate. Forming a first region of relatively thick material having a predetermined lateral length on the surface of the substrate adjacent the relatively thin dielectric layer. Implanting dopants to form a top gate using a first edge of the first region as a mask to define a first edge of the top gate. Implanting dopants to form a drain contact using a second edge of the first region as a mask to define a first edge of the drain contact, wherein the distance between the top gate and drain contact is defined by the lateral length of the first region.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: August 12, 2008
    Assignee: Intersil Americas Inc.
    Inventor: James D. Beasom
  • Patent number: 7385246
    Abstract: An integrated circuit device comprising a diode and a method of making an integrated circuit device comprising a diode are provided. The diode can comprise an island of a first conductivity type, a first region of a second conductivity type formed in the island, and a cathode diffusion contact region doped to the second conductivity type disposed in the first region. The diode can also comprise a cathode contact electrically contacting the cathode diffusion contact region, an anode disposed in the island, an anode contact electrically contacting the anode, and a first extension region doped to the first conductivity type disposed at a surface junction between the first region and the island.
    Type: Grant
    Filed: January 6, 2006
    Date of Patent: June 10, 2008
    Assignee: Intersil Americas Inc.
    Inventor: James Douglas Beasom
  • Patent number: 7276431
    Abstract: An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: October 2, 2007
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chan
  • Patent number: 7268065
    Abstract: A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the semi-conductive layer. At least a portion of the semi-conductive layer is doped by implanting through the conductive layer. The semi-conductive layer and the conductive layer may then be annealed.
    Type: Grant
    Filed: June 18, 2004
    Date of Patent: September 11, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Tung Lin, Chih-Wei Chang, Chii-Ming Wu, Mei-Yun Wang, Chiang-Ming Chuang, Shau-Lin Shue
  • Patent number: 7172933
    Abstract: A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate structure and in portions of the semiconductor substrate not occupied by the gate structure or by dummy spacers located on the sides of the conductive gate structure. The selectively defined recesses will be used to subsequently accommodate silicon-germanium shapes, with the silicon-germanium shapes located in the recesses in the semiconductor substrate inducing the desired strained channel region. The recessing of the conductive gate structure and of semiconductor substrate portions reduces the risk of silicon-germanium bridging across the surface of sidewall spacers during epitaxial growth of the alloy layer, thus reducing the risk of gate to substrate leakage or shorts.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: February 6, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Chun Huang, Bow-Wen Chan, Baw-Ching Perng, Lawrence Sheu, Hun-Jan Tao, Chih-Hsin Ko, Chun-Chieh Lin
  • Patent number: 7078325
    Abstract: A process is described which allows a buried, retrograde doping profile or a delta doping to be produced in a relatively simple and inexpensive way. The process uses individual process steps that are already used in the mass production of integrated circuits and accordingly can be configured for a high throughput.
    Type: Grant
    Filed: July 12, 2001
    Date of Patent: July 18, 2006
    Assignee: Infineon Technologies AG
    Inventors: Giuseppe Curello, Jürgen Faul
  • Patent number: 7005334
    Abstract: A zero threshold voltage (ZVt) pFET (104) and a method of making the same. The ZVt pFET is made by implanting a p-type substrate (112) with a retrograde n-well (116) so that a pocket (136) of the p-type substrate material remains adjacent the surface of the substrate. This is accomplished using an n-well mask (168) having a pocket-masking region (184) in the aperture (180) corresponding to the ZVt pFET. The n-well may be formed by first creating a ring-shaped precursor n-well (116?) and then annealing the substrate so as to cause the regions of the lower portion (140?) of the precursor n-well to merge with one another to isolate the pocket of p-type substrate material. After the n-well and isolated pocket of p-type substrate material have been formed, remaining structures of the ZVt pFET may be formed, such as a gate insulator (128), gate (132), source (120), and drain (124).
    Type: Grant
    Filed: May 14, 2004
    Date of Patent: February 28, 2006
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey S. Brown, Chung H. Lam, Randy W. Mann, Jeffery H. Oppold
  • Patent number: 7005364
    Abstract: The invention provides a method for manufacturing a semiconductor device with which an impurity introduction region and a positioning mark region can be formed aligned, based on a common insulating film pattern.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: February 28, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Naoto Niisoe
  • Patent number: 6897103
    Abstract: An integrated circuit having a high voltage lateral MOS with reduced ON resistance. In one embodiment, the integrated circuit includes a high voltage lateral MOS with an island formed in a substrate, a source, a gate and a first and second drain extension. The island is doped with a low density first conductivity type. The source and drain contact are both doped with a high density second conductivity type. The first drain extension is of the second conductivity type and extends laterally from under the gate past the drain contact. The second drain extension is of the second conductivity type and extends laterally from under the gate toward the source. A portion of the second drain extension overlaps the first drain extension under the gate to form a region of increased doping of the second conductivity type.
    Type: Grant
    Filed: February 12, 2003
    Date of Patent: May 24, 2005
    Assignee: Intersil Americas Inc.
    Inventor: James D. Beasom
  • Patent number: 6818534
    Abstract: A semiconductor memory device comprises a trench etched from a substrate below a shallow trench isolation and a doped collar oxide. The device further comprises a buried-strap junction formed adjacent to the shallow trench isolation and above the collar oxide, and a channel stop formed below the buried-strap junction, wherein a junction between the channel stop and the buried-strap junction is formed in the substrate.
    Type: Grant
    Filed: August 19, 2002
    Date of Patent: November 16, 2004
    Assignee: Infineon Technologies Richmond, LP
    Inventors: Jonathan Philip Davis, Stephen M. Rusinko, Jr.
  • Patent number: 6777758
    Abstract: P wells (11, 12) having different impurity profiles are adjacently formed in a surface (50S) of a semiconductor substrate (50). A P-type layer (20) having lower resistivity than the P wells (11, 12) is formed in the surface (50S) across the P wells (11, 12), so that the P wells (11, 12) are electrically connected with each other through the P-type layer (20). Contacts (31, 32) fill in contact holes (70H1, 70H2) formed in an interlayer isolation film (70) respectively in contact with the P-type layer (20). The contacts (31, 32) are connected to a wire (40). The wire (70) is connected to a prescribed potential, thereby fixing the P wells (11, 12) to prescribed potentials through the contacts (31, 32) and the P-type layer (20). Thus, the potentials of the wells can be stably fixed and the layout area of elements for fixing the aforementioned potentials can be reduced.
    Type: Grant
    Filed: January 5, 2001
    Date of Patent: August 17, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Tomohiro Yamashita, Yoshinori Okumura, Katsuyuki Horita
  • Patent number: 6670245
    Abstract: The present invention provides a method for fabricating an ESD device. First, a substrate undergoes first implantation to form a first first-type well comprising an electrostatic discharge region. Next, second implantation is performed on the substrate and the electrostatic discharge region to form a second first-type well and an ESD device. Finally, gates, sources, and drains are formed to complete the process.
    Type: Grant
    Filed: October 12, 2001
    Date of Patent: December 30, 2003
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Ta-Lee Yu
  • Patent number: 6642089
    Abstract: For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: November 4, 2003
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Koji Ono, Yoshihiro Kusuyama
  • Patent number: 6635505
    Abstract: There is provided an active matrix type semiconductor display device which realizes low power consumption and high reliability. In the active matrix type semiconductor display device of the present invention, a counter electrode is divided into two, different potentials are applied to the two counter electrodes, respectively and inversion driving is carried out each other. Since a potential of an image signal can be made low by doing so, it is possible to lower a voltage necessary for operation of a driver circuit. As a result, it is possible to realize improvement of reliability of an element such as a TFT and reduction of consumed electric power. Moreover, since it is possible to lower a voltage of a timing pulse supplied by the driver circuit, a booster circuit can be omitted, and reduction of an area of the driver circuit can be realized.
    Type: Grant
    Filed: November 18, 2002
    Date of Patent: October 21, 2003
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yukio Tanaka, Shou Nagao
  • Patent number: 6621131
    Abstract: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.
    Type: Grant
    Filed: November 1, 2001
    Date of Patent: September 16, 2003
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Robert S. Chau, Tahir Ghani, Kaizad R. Mistry
  • Patent number: 6583060
    Abstract: A dual depth trench isolation structure formed between active devices and conductive well regions of same conductivity type which comprises a first inter-well isolation structure having a first isolation trench depth, a second inter-well isolation structure having a second isolation trench depth which combine to form a dual depth trench containing the dual depth trench isolation structure comprising the first inter-well isolation structure and the second inter-well isolation structure, with the dual depth trench isolation interposed at the boundary of an n-well conductive region and a p-well conductive region, a first intra-well isolation structure having a first isolation trench depth, the first intra-well isolation structure interposed between a pair of p-channel transistors residing in the n-well region, and a second intra-well isolation structure having a second isolation trench depth, the second intra-well isolation structure interposed between a pair of n-channel transistors residing in the p-well regio
    Type: Grant
    Filed: July 13, 2001
    Date of Patent: June 24, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Jigish Trivedi
  • Patent number: 6541359
    Abstract: A method and apparatus thereof for fabricating an integrated circuit on a laminate having a gate electrode layer over a silicon dioxide layer. Detection of the gate etch endpoint signal is improved by maximizing the use of a faster etching dopant material (e.g., n-type dopant) and minimizing the use of a slower etching dopant material (e.g., p-type dopant) in the gate electrode layer. In one embodiment, a first portion of the gate electrode layer, substantially corresponding only to the location at which a gate is to be formed, is doped with the slower etching dopant material. The remaining portion of the gate electrode layer is doped with the faster etching dopant material; thus, more of the gate electrode layer is doped with the faster etching dopant material than with the slower etching dopant material. A gate mask is aligned over the gate electrode layer, and the unmasked portions of the gate electrode layer are removed using an etchant.
    Type: Grant
    Filed: January 31, 2000
    Date of Patent: April 1, 2003
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Calvin Todd Gabriel, Tammy D. Zheng, Emmanuel de Muizon, Linda A. Leard
  • Patent number: 6482714
    Abstract: Disclosed is a semiconductor device comprising a transistor structure including an epitaxial silicon layer formed on a main surface of an n-type semiconductor substrate, source-drain diffusion layers formed on at least the epitaxial silicon layer, a channel region formed between the source and drain regions, and a gate electrode formed on the channel region with a gate insulating film interposed therebetween, an element isolation region being sandwiched between adjacent transistor structures, wherein a punch-through stopper layer formed in a lower portion of the channel region has an impurity concentration higher than that of the channel region, and the source-drain diffusion layers do not extend to overlap with edge portion of insulating films for the element isolation.
    Type: Grant
    Filed: February 24, 2000
    Date of Patent: November 19, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuhiko Hieda, Kyoichi Suguro
  • Patent number: 6433392
    Abstract: The high current capabilities of a lateral npn transistor for application as a protection device against degradation due to electrostatic discharge (ESD) events are improved by adjusting the electrical resistivity of the material through which the collector current flows from the avalanching pn-junction to the wafer backside contact. As expressed in terms of the second threshold current improvements by a factor of 4 are reported. Two implant sequences are described which apply local masking and standard implant conditions to achieve the improvements without adding to the total number of process steps. The principle of p-well engineering is extended to ESD protection devices employing SCR-type devices.
    Type: Grant
    Filed: December 3, 1999
    Date of Patent: August 13, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: E. Ajith Amerasekera, Vikas Gupta, Stanton P. Ashburn
  • Patent number: 6383850
    Abstract: In a region on the left hand of FIG. 1 with respect to the gate electrode (107), a first source region (103a), a body-potential drawing region (105) and a second source region (103b) are formed in this order along the vertical direction of this figure. The first and second source regions (103a, 103b) are of n+ type, and the body-potential drawing region (105) is of p+ type. In a thin-film transistor (100), the body-potential drawing region (105) can draw and fix a body potential.
    Type: Grant
    Filed: January 4, 2001
    Date of Patent: May 7, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yuuichi Hirano
  • Patent number: 6291323
    Abstract: The present invention relates to the formation of trench isolation structures that isolate active areas and a preferred doping in the fabrication of a CMOS device with a minimized number of masks. Ions of a P-type dopant are implanted into a semiconductor substrate having therein a P-well and an N-well. Each of the N-well and P-well has therein a trench. The ions of the P-type dopant are implanted beneath each of the trenches in the P-well and the N-well to create a first P-type dopant concentration profile in the semiconductor substrate, wherein the P-well and the N-well are substantially unimplanted by the ions of the P-type dopant in active areas adjacent to the respective trenches therein. A second implanting ions of a P-type dopant is made into the semiconductor substrate. The second implanting is beneath each of the trenches in the P-well and the N-well to form a second P-type dopant concentration profile.
    Type: Grant
    Filed: August 9, 1999
    Date of Patent: September 18, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Fernando Gonzalez
  • Publication number: 20010001694
    Abstract: In one aspect, the invention includes a method of maintaining dimensions of an opening in a semiconductive material stencil mask comprising providing two different dopants within a periphery of the opening, the dopants each being provided to a concentration of at least about 1017 atoms/cm3.
    Type: Application
    Filed: December 12, 2000
    Publication date: May 24, 2001
    Inventor: J. Brett Rolfson
  • Patent number: 6232182
    Abstract: A non-volatile semiconductor memory device including a memory cell having a memory transistor and a selection transistor, comprising: a composite gate structure of the memory transistor formed on a surface of a semiconductor substrate at its first region with a first insulating film interposed therebetween and including a laminate of a floating gate electrode, a second insulating film and a control gate electrode; a gate electrode of the selection transistor formed on the surface of the semiconductor substrate at its second region close to the first region with a third insulating film interposed therebetween; and an impurity diffusion layer formed in the semiconductor substrate at its region between the first and second regions and functioning as a drain of the memory transistor, common to a source of the selection transistor, the impurity diffusion layer having at least an extension region extending to a part of the semiconductor substrate disposed under the composite gate structure, the extension region hav
    Type: Grant
    Filed: May 1, 1998
    Date of Patent: May 15, 2001
    Assignee: Nippon Steel Corporation
    Inventor: Fumitaka Sugaya
  • Patent number: 6040237
    Abstract: A semiconductor component and a method for processing said component, which comprises a pn junction, where both the p-conducting (3) and the n-conducting layers (2) of the pn junction constitute doped silicon carbide layers and where the edge of the higher doped conducting layer of the pn junction exhibits a charge profile with a stepwise or uniformly decreasing total charge or effective surface charge density from the initial value at the main pn junction to a zero or almost zero total charge or charge density at the outermost edge of the junction following a radial direction from the central part of the junction towards the outermost edge.
    Type: Grant
    Filed: October 23, 1997
    Date of Patent: March 21, 2000
    Assignee: ABB Research Ltd.
    Inventors: Mietek Bakowski, Ulf Gustafsson, Kurt Rottner, Susan Savage
  • Patent number: 5773358
    Abstract: Methods of forming field effect transistors.
    Type: Grant
    Filed: August 12, 1996
    Date of Patent: June 30, 1998
    Assignee: Micron Technology, Inc.
    Inventors: Jeff Zhiqiang Wu, Sittampalam Yoganathan