Of Compound Semiconductor Patents (Class 438/518)
  • Patent number: 9966256
    Abstract: There is provided a method of forming a film on a surface to be processed of a workpiece, the method including: accommodating the workpiece with a single-crystallized substance formed on the surface to be processed, into a processing chamber; supplying a crystallization suppressing process gas into the processing chamber such that a crystallization of the single-crystallized substance formed on the surface to be processed is suppressed; and supplying a source gas into the processing chamber to form an amorphous film on the surface to be processed of the workpiece.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: May 8, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Satoshi Takagi, Kazuya Takahashi, Hiroki Murakami, Daisuke Suzuki
  • Patent number: 9957638
    Abstract: A method for manufacturing a silicon carbide semiconductor device includes: preparing a silicon carbide single crystal substrate having a flatness with an average roughness of 0.2 nm or less; gas-etching a surface of the silicon carbide single crystal substrate under an atmosphere of a reducing gas; and forming a silicon carbide layer on the gas-etched surface of the silicon carbide single crystal substrate, wherein an etching rate of the gas etching is made in a range of 0.5 ?m/hour or faster to 2.0 ?m/hour or slower.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: May 1, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Akihito Ohno, Yoichiro Mitani, Takahiro Yamamoto, Nobuyuki Tomita, Kenichi Hamano
  • Patent number: 9941361
    Abstract: In a method for fabricating a semiconductor substrate according to an embodiment, an SiC substrate is formed by vapor growth and C (carbon) is introduced into the surface of the SiC substrate to form an n-type SiC layer on the SiC substrate by an epitaxial growth method.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: April 10, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Johji Nishio, Ryosuke Iijima, Kazuto Takao, Takashi Shinohe
  • Patent number: 9269577
    Abstract: Forming a group III nitride semiconductor layer having p-type conductivity on at least one layer or more formed on an Si substrate or sapphire substrate using at least one of an epitaxial growth or ion implantation method. When forming the group III nitride semiconductor layer, at least one type of metal element selected from Zn, Li, Au, Ag, Cu, Pt, and Pd having a formation energy of a group III element substitute higher than that of Mg is doped simultaneously with Mg of a p-type dopant to introduce an interstitial site. Subsequent to activation of Mg as an acceptor, the metal element is removed from the group III nitride semiconductor layer, and the concentration of the metal element is not more than 1/100 of the concentration of Mg to realize a hole concentration of not less than 1018 to 1019 cm?3.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: February 23, 2016
    Assignee: FURUKAWA ELECTRIC CO., LTD.
    Inventor: Masayuki Iwami
  • Patent number: 9034740
    Abstract: The deposition rate of a porous insulation film is increased, and the film strength of the porous insulation film is improved. Two or more organic siloxane raw materials each having a cyclic SiO structure as a main skeleton thereof, and having mutually different structures, are vaporized, and transported with a carrier gas to a reactor (chamber), and an oxidant gas including an oxygen atom is added thereto. Thus, a porous insulation film is formed by a plasma CVD (Chemical Vapor Deposition) method or a plasma polymerization method in the reactor (chamber). In the step, the ratio of the flow rate of the added oxidant gas to the flow rate of the carrier gas is more than 0 and 0.08 or less.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: May 19, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hironori Yamamoto, Fuminori Ito, Yoshihiro Hayashi
  • Patent number: 9020002
    Abstract: Photonic integrated circuits on silicon are disclosed. By bonding a wafer of compound semiconductor material as an active region to silicon and removing the substrate, the lasers, amplifiers, modulators, and other devices can be processed using standard photolithographic techniques on the silicon substrate. A silicon laser intermixed integrated device in accordance with one or more embodiments of the present invention comprises a silicon-on-insulator substrate, comprising at least one waveguide in a top surface, and a compound semiconductor substrate comprising a gain layer, the compound semiconductor substrate being subjected to a quantum well intermixing process, wherein the upper surface of the compound semiconductor substrate is bonded to the top surface of the silicon-on-insulator substrate.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: April 28, 2015
    Assignee: The Regents of the University of California
    Inventors: Matthew N. Sysak, John E. Bowers, Alexander W. Fang, Hyundai Park
  • Publication number: 20150104912
    Abstract: A method for fabricating a vertical GaN power device includes providing a first GaN material having a first conductivity type and forming a second GaN material having a second conductivity type and coupled to the first GaN material to create a junction. The method further includes implanting ions through the second GaN material and into a first portion of the first GaN material to increase a doping concentration of the first conductivity type. The first portion of the junction is characterized by a reduced breakdown voltage relative to a breakdown voltage of a second portion of the junction.
    Type: Application
    Filed: October 17, 2014
    Publication date: April 16, 2015
    Inventor: Donald R. Disney
  • Patent number: 8975156
    Abstract: A method of sealing a first wafer and a second wafer each made of semiconducting materials, including: implanting a metallic species in at least the first wafer, assembling the first wafer and the second wafer by molecular bonding, and after the molecular bonding, forming a metallic ohmic contact including alloys formed between the implanted metallic species and the semiconducting materials of the first wafer and the second wafer, the metallic ohmic contact being formed at an assembly interface between the first wafer and the second wafer, wherein the forming includes causing the implanted metallic species to diffuse towards the interface between the first wafer with the second wafer and beyond the interface.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: March 10, 2015
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Stephane Pocas, Hubert Moriceau, Jean-Francois Michaud
  • Patent number: 8951897
    Abstract: A method for controlling the concentration of a donor in a Ga2O3-based single crystal includes: a step in which a Group IV element is implanted as a donor impurity in a Ga2O3-based single crystal by ion implantation process to form, in the Ga2O3-based single crystal, a donor impurity implantation region that has a higher concentration of the Group IV element than the region in which the Group IV element has not been implanted; and a step in which annealing at 800 C or higher is conducted to activate the Group IV element present in the donor impurity implantation region and thereby form a high-donor-concentration region. Thus, the donor concentration in the Ga2O3-based single crystal is controlled.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: February 10, 2015
    Assignee: Tamura Corporation
    Inventor: Kohei Sasaki
  • Patent number: 8932944
    Abstract: In the manufacture of a silicon carbide semiconductor device having a termination region being a JTE region or FLR, the margin of the amount of etching for removing a damage layer formed in the surface of the termination region is enlarged. A silicon carbide semiconductor device has a termination region being a JTE (Junction Termination Extension) region or an FLR (Field Limiting Ring) at a termination of the semiconductor elements. The termination region is formed by one step of ion implantation in which the kind of impurity and the implant energy are fixed. In the impurity concentration profile of the termination region in the depth direction, the concentration peak in the shallowest position is in a position deeper than 0.35 ?m from the surface, and the concentration in the surface portion is not more than one-tenth of the shallowest concentration peak.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: January 13, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoichiro Tarui, Naoto Kaguchi, Takuyo Nakamura
  • Publication number: 20150008446
    Abstract: A method of manufacturing a semiconductor device is presented. The method includes providing a semiconductor layer comprising silicon carbide, wherein the semiconductor layer comprises a first region doped with a first dopant type. The method further includes implanting the semiconductor layer with a second dopant type using a single implantation mask and a substantially similar implantation dose to form a second region and a junction termination extension (JTE) in the semiconductor layer, wherein the implantation dose is in a range from about 2×1013 cm?2 to about 12×1013 cm?2. Semiconductor devices are also presented.
    Type: Application
    Filed: July 2, 2013
    Publication date: January 8, 2015
    Inventors: Peter Almern Losee, Alexander Viktorovich Bolotnikov, Stacey Joy Kennerly
  • Patent number: 8921206
    Abstract: First, a substrate with a recess is provided in a semiconductor process. Second, an embedded SiGe layer is formed in the substrate. The embedded SiGe layer includes an epitaxial SiGe material which fills up the recess. Then, a pre-amorphization implant (PAI) procedure is carried out on the embedded SiGe layer to form an amorphous region. Next, a source/drain implanting procedure is carried out on the embedded SiGe layer to form a source doping region and a drain doping region. Later, a source/drain annealing procedure is carried out to form a source and a drain in the substrate. At least one of the pre-amorphization implant procedure and the source/drain implanting procedure is carried out in a cryogenic procedure below ?30° C.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: December 30, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chan-Lon Yang, Ching-I Li, Ger-Pin Lin, I-Ming Lai, Yun-San Huang, Chin-I Liao, Chin-Cheng Chien
  • Publication number: 20140363959
    Abstract: The present invention provides a silicon carbide Schottky-barrier diode device and a method for manufacturing the same. The silicon carbide Schottky bather diode device includes a primary n? epitaxial layer, an n+ epitaxial region, and a Schottky metal layer. The primary n? epitaxial layer is deposited on an n+ substrate joined with an ohmic metal layer at an undersurface thereof. The n+ epitaxial region is formed by implanting n+ ions into a central region of the primary n? epitaxial layer. The Schottky metal layer is deposited on the n+ epitaxial layer.
    Type: Application
    Filed: June 18, 2014
    Publication date: December 11, 2014
    Inventors: Kyoung Kook Hong, Jong Seok Lee
  • Patent number: 8847280
    Abstract: An improved insulated gate field effect device is obtained by providing a substrate desirably comprising a III-V semiconductor, having a further semiconductor layer on the substrate adapted to contain the channel of the device between spaced apart source-drain electrodes formed on the semiconductor layer. A dielectric layer is formed on the semiconductor layer. A sealing layer is formed on the dielectric layer and exposed to an oxygen plasma. A gate electrode is formed on the dielectric layer between the source-drain electrodes. The dielectric layer preferably comprises gallium-oxide and/or gadolinium-gallium oxide, and the oxygen plasma is preferably an inductively coupled plasma. A further sealing layer of, for example, silicon nitride is desirably provided above the sealing layer. Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: September 30, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jonathan K. Abrokwah, Ravindranath Droopad, Matthias Passlack
  • Patent number: 8835288
    Abstract: A method of manufacturing a silicon carbide semiconductor device of an embodiment includes: implanting ions in a silicon carbide substrate; performing first heating processing of the silicon carbide substrate in which the ions are implanted; and performing second heating processing of the silicon carbide substrate for which the first heating processing is performed, at a temperature lower than the first heating processing.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: September 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Johji Nishio, Masaru Furukawa, Hiroshi Kono, Takashi Shinohe
  • Patent number: 8822315
    Abstract: A method is disclosed for treating a silicon carbide substrate for improved epitaxial deposition thereon and for use as a precursor in the manufacture of devices such as light emitting diodes. The method includes the steps of implanting dopant atoms of a first conductivity type into the first surface of a conductive silicon carbide wafer having the same conductivity type as the implanting ions at one or more predetermined dopant concentrations and implant energies to form a dopant profile, annealing the implanted wafer, and growing an epitaxial layer on the implanted first surface of the wafer.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: September 2, 2014
    Assignee: Cree, Inc.
    Inventors: Davis Andrew McClure, Alexander Suvorov, John Adam Edmond, David Beardsley Slater, Jr.
  • Publication number: 20140183561
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor part and a conductive electrode. The first semiconductor part is made of SiC. The SiC contains a first element as an n-type or p-type impurity. The first semiconductor part has a first interface part. The first interface part is configured to have maximum area density of the first element. The c conductive electrode is electrically connected to the first interface part.
    Type: Application
    Filed: December 16, 2013
    Publication date: July 3, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Tatsuo SHIMIZU
  • Patent number: 8765557
    Abstract: A first layer constituting a first surface of a silicon carbide layer and of a first conductivity type is prepared. An internal trench is formed at a face opposite to the first surface of the first layer. Impurities are implanted such that the conductivity type of the first layer is inverted on the sidewall of the internal trench. By the implantation of impurities, there are formed from the first layer an implantation region located on the sidewall of the internal trench and of a second conductivity type, and a non-implantation region of the first conductivity type. A second layer of the first conductivity type is formed, filling the internal trench, and constituting the first region together with the non-implantation region.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: July 1, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hideki Hayashi, Takeyoshi Masuda
  • Patent number: 8748276
    Abstract: A through portion is formed on a semiconductor substrate. Into the semiconductor substrate, a first ion implantation is performed via the through portion. The through portion is at least partially removed in the thickness direction from a region of at least a portion of the through portion when viewed in a plan view. A second ion implantation is performed into the semiconductor substrate at the region of at least the portion thereof. An implantation energy for the first ion implantation is equal to an implantation energy for the second ion implantation.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: June 10, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Hideki Hayashi
  • Patent number: 8734666
    Abstract: A method for preparing nanotubes by providing nanorods of a piezoelectric material having an asymmetric crystal structure and by further providing hydroxide ions to the nanorods to etch inner parts of the nanorods to form the nanotubes.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: May 27, 2014
    Assignees: Samsung Electronics Co., Ltd., Kumoh National Institute of Technology
    Inventors: Jaeyoung Choi, Sangwoo Kim
  • Patent number: 8729558
    Abstract: According to one embodiment, a nitride semiconductor device includes a semiconductor layer, a source electrode, a drain electrode, a first and a second gate electrode. The semiconductor layer includes a nitride semiconductor. The source electrode provided on a major surface of the layer forms ohmic contact with the layer. The drain electrode provided on the major surface forms ohmic contact with the layer and is separated from the source electrode. The first gate electrode is provided on the major surface between the source and drain electrodes. The second gate electrode is provided on the major surface between the source and first gate electrodes. When a potential difference between the source and first gate electrodes is 0 volts, a portion of the layer under the first gate electrode is conductive. The first gate electrode is configured to switch a constant current according to a voltage applied to the second gate electrode.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: May 20, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masahiko Kuraguchi
  • Patent number: 8716086
    Abstract: A first layer constituting a first surface of a silicon carbide layer and of a first conductivity type is prepared. An internal trench is formed at a face opposite to the first surface of the first layer. Impurities are implanted such that the conductivity type of the first layer is inverted on the sidewall of the internal trench. By the implantation of impurities, there are formed from the first layer an implantation region located on the sidewall of the internal trench and of a second conductivity type, and a non-implantation region of the first conductivity type. A second layer of the first conductivity type is formed, filling the internal trench, and constituting the first region together with the non-implantation region.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: May 6, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hideki Hayashi, Takeyoshi Masuda
  • Patent number: 8697467
    Abstract: Compound semiconductor devices and methods of doping compound semiconductors are provided. Embodiments of the invention provide post-deposition (or post-growth) doping of compound semiconductors, enabling nanoscale compound semiconductor devices including diodes and transistors. In one method, a self-limiting monolayer technique with an annealing step is used to form shallow junctions. By forming a sulfur monolayer on a surface of an InAs substrate and performing a thermal annealing to drive the sulfur into the InAs substrate, n-type doping for InAs-based devices can be achieved. The monolayer can be formed by surface chemistry reactions or a gas phase deposition of the dopant. In another method, a gas-phase technique with surface diffusion is used to form doped regions. By performing gas-phase surface diffusion of Zn into InAs, p-type doping for InAs-based devices can be achieved.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: April 15, 2014
    Assignee: The Regents of the University of California
    Inventors: Ali Javey, Alexandra C. Ford, Johnny C. Ho
  • Patent number: 8691676
    Abstract: To provide a temperature control method capable of equivalently maintaining qualities of substrates even when treated substrates are continuously carried in a treatment container in the case in which activation annealing treatment is performed by an electron impact heating method.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: April 8, 2014
    Assignee: Canon Anelva Corporation
    Inventors: Masami Shibagaki, Kaori Mashimo
  • Patent number: 8669590
    Abstract: Methods and apparatus for forming semiconductor structures are disclosed herein. In some embodiments, a semiconductor structure may include a first germanium carbon layer having a first side and an opposing second side; a germanium-containing layer directly contacting the first side of the first germanium carbon layer; and a first silicon layer directly contacting the opposing second side of the first germanium carbon layer. In some embodiments, a method of forming a semiconductor structure may include forming a first germanium carbon layer atop a first silicon layer; and forming a germanium-containing layer atop the first germanium carbon layer.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: March 11, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Errol Antonio C. Sanchez, Yi-Chiau Huang
  • Publication number: 20140021489
    Abstract: A semiconductor device having a high withstand voltage in which a stable withstand voltage can be obtained and a method for manufacturing the same. A JTE region having a second conductivity type is formed in a portion on an outer peripheral end side of an SiC substrate from a second conductivity type SiC region in a vicinal portion of a surface on one of sides in a thickness direction of a first conductivity type SiC epitaxial layer. A first conductivity type SiC region having a higher concentration of an impurity having the first conductivity type than that of the SiC epitaxial layer is formed in at least a vicinal portion of a surface on one of sides in a thickness direction of a portion in which the JTE regions are bonded to each other.
    Type: Application
    Filed: March 29, 2012
    Publication date: January 23, 2014
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kenji Hamada, Tsuyoshi Kawakami
  • Publication number: 20140021490
    Abstract: Fabrication of a termination structure in a semiconductor device increases in some cases the numbers of ion implantation processes or of photolithography processes, thus leading to an increase in fabrication costs. To overcome this problem, a semiconductor device is provided which includes an n-type drift layer formed on a semiconductor substrate; an element region formed in a surface portion of the drift layer; a recess formed in a loop in a laterally outer portion of the drift layer, spaced away a predetermined distance from the element region; and a p-type dopant region formed ranging from a bottom of the recess to a position away from the recess and toward the element region, a thickness of the dopant region where no recess is provided being greater than that where the recess is provided.
    Type: Application
    Filed: March 12, 2012
    Publication date: January 23, 2014
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kenichi Ohtsuka, Hiroshi Watanabe
  • Patent number: 8559478
    Abstract: Photonic integrated circuits on silicon are disclosed. By bonding a wafer of compound semiconductor material as an active region to silicon and removing the substrate, the lasers, amplifiers, modulators, and other devices can be processed using standard photolithographic techniques on the silicon substrate. A silicon laser intermixed integrated device in accordance with one or more embodiments of the present invention comprises a silicon-on-insulator substrate, comprising at least one waveguide in a top surface, and a compound semiconductor substrate comprising a gain layer, the compound semiconductor substrate being subjected to a quantum well intermixing process, wherein the upper surface of the compound semiconductor substrate is bonded to the top surface of the silicon-on-insulator substrate.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: October 15, 2013
    Assignee: The Regents of the University of California
    Inventors: Matthew N. Sysak, John E. Bowers, Alexander W. Fang, Hyundai Park
  • Publication number: 20130237043
    Abstract: A method of manufacturing an SiC semiconductor device according to the present invention includes the steps of (a) by using a single mask, etching regions of an SiC semiconductor layer which serve as an impurities implantation region and a mark region, to form recesses, (b) by using the same mask as in the step (a), performing ion-implantation in the recesses of the regions which serve as the impurities implantation region and the mark region, at least from an oblique direction relative to a surface of the SiC semiconductor layer and (c) positioning another mask based on the recess of the region which serves as the impurities implantation region or the mark region, and performing well implantation in a region containing the impurities implantation region.
    Type: Application
    Filed: April 17, 2013
    Publication date: September 12, 2013
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Noriaki Tsuchiya, Yoichiro Tarui
  • Patent number: 8524585
    Abstract: A method of manufacturing a MOSFET includes the steps of preparing a substrate with an epitaxial growth layer made of silicon carbide, performing ion implantation into the substrate with the epitaxial growth layer, forming a protective film made of silicon dioxide on the substrate with the epitaxial growth layer into which the ion implantation was performed, and heating the substrate with the epitaxial growth layer on which the protective film was formed to a temperature range of 1600° C. or more in an atmosphere containing gas including an oxygen atom.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: September 3, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Takeyoshi Masuda
  • Patent number: 8501600
    Abstract: Methods for depositing germanium-containing layers on silicon-containing layers are provided herein. In some embodiments, a method may include depositing a first layer atop an upper surface of the silicon-containing layer, wherein the first layer comprises predominantly germanium (Ge) and further comprises a lattice adjustment element having a concentration selected to enhance electrical activity of dopant elements, wherein the dopant elements are disposed in at least one of the first layer or in an optional second layer deposited atop of the first layer, wherein the optional second layer, if present, comprises predominantly germanium (Ge). In some embodiments, the second layer is deposited atop the first layer. In some embodiments, the second layer comprises germanium (Ge) and dopant elements.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: August 6, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Errol Sanchez, Yi-Chiau Huang, David K. Carlson
  • Patent number: 8501516
    Abstract: A method for producing micromechanical patterns having a relief-like sidewall outline shape or an angle of inclination that is able to be set, the micromechanical patterns being etched out of a SiGe mixed semiconductor layer that is present on or deposited on a silicon semiconductor substrate, by dry chemical etching of the SiGe mixed semiconductor layer; the sidewall outline shape of the micromechanical pattern being developed by varying the germanium proportion in the SiGe mixed semiconductor layer that is to be etched; a greater germanium proportion being present in regions that are to be etched more strongly; the variation in the germanium proportion in the SiGe mixed semiconductor layer being set by a method selected from the group including depositing a SiGe mixed semiconductor layer having varying germanium content, introducing germanium into a silicon semiconductor layer or a SiGe mixed semiconductor layer, introducing silicon into a germanium layer or an SiGe mixed semiconductor layer and/or by therm
    Type: Grant
    Filed: October 13, 2008
    Date of Patent: August 6, 2013
    Assignee: Robert Bosch GmbH
    Inventors: Franz Laermer, Tino Fuchs, Christina Leinenbach
  • Publication number: 20130171811
    Abstract: In a method for manufacturing a compound semiconductor, a silicon oxide film is formed in an upper part of a substrate made of silicon. Subsequently, a base layer made of single crystal silicon to which ions are implanted is formed by performing ion implantation to a region of the substrate below the silicon oxide film and performing a thermal process. Then, the base layer is exposed by removing the silicon oxide film. Finally, a GaN layer is formed on the base layer.
    Type: Application
    Filed: February 26, 2013
    Publication date: July 4, 2013
    Applicant: PANASONIC CORPORATION
    Inventor: PANASONIC CORPORATION
  • Patent number: 8470699
    Abstract: Disclosed is a method of manufacturing a silicon carbide semiconductor apparatus which provides a smooth silicon carbide surface while maintaining a high impurity activation ratio. The method of manufacturing a silicon carbide semiconductor apparatus which forms an impurity region in the surface layer of a silicon carbide substrate includes the steps of implanting an impurity into the surface layer of the silicon carbide substrate, forming a carbon film on the surface of the silicon carbide substrate, preliminarily heating the silicon carbide substrate with the carbon film as a protective film, and thermally activating the silicon carbide substrate with the carbon film as a protective film.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: June 25, 2013
    Assignee: Showa Denko K.K.
    Inventor: Kenji Suzuki
  • Patent number: 8470672
    Abstract: A method of manufacturing a semiconductor device includes forming a drift layer on a substrate; forming a base layer on the drift layer; forming a trench to penetrate the base layer and to reach the drift layer; rounding off a part of a shoulder corner and a part of a bottom corner of the trench; covering an inner wall of the trench with an organic film; implanting an impurity to a surface portion of the base layer; forming a source region by activating the implanted impurity; and removing the organic film after the source region is formed, in which the substrate, the drift layer, the base layer and the source region are made of silicon carbide, and the implanting and the activating of the impurity are performed under a condition that the trench is covered with the organic film.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: June 25, 2013
    Assignees: DENSO CORPORATION, Toyota Jidosha Kabushiki Kaisha
    Inventors: Takeshi Endo, Shinichiro Miyahara, Tomoo Morino, Masaki Konishi, Hirokazu Fujiwara, Jun Morimoto, Tsuyoshi Ishikawa, Takashi Katsuno, Yukihiko Watanabe
  • Patent number: 8470697
    Abstract: A method of forming a p-type compound semiconductor layer includes increasing a temperature of a substrate loaded into a reaction chamber to a first temperature. A source gas of a Group III element, a source gas of a p-type impurity, and a source gas of nitrogen containing hydrogen are supplied into the reaction chamber to grow the p-type compound semiconductor layer. Then, the supply of the source gas of the Group III element and the source gas of the p-type impurity is stopped and the temperature of the substrate is lowered to a second temperature. The supply of the source gas of nitrogen containing hydrogen is stopped and drawn out at the second temperature, and the temperature of the substrate is lowered to room temperature using a cooling gas. Accordingly, hydrogen is prevented from bonding to the p-type impurity in the p-type compound semiconductor layer.
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: June 25, 2013
    Assignee: Seoul Opto Device Co., Ltd.
    Inventors: Ki Bum Nam, Hwa Mok Kim, James S. Speck
  • Publication number: 20130137254
    Abstract: A method for manufacturing a semiconductor device has the following steps. A substrate having a silicon carbide layer of a first conductivity type is prepared. On the silicon carbide layer, a mask layer is formed. By ion implantation from above the mask layer, a well region of a second conductivity type is formed on the silicon carbide layer. At the step of forming the mask layer, the mask layer having an opening with a taper angle, which is an angle formed between a bottom surface and an inclined surface of mask layer, being larger than 60° and not larger than 80° is formed. Thus, a method of manufacturing a semiconductor device, capable of producing a semiconductor device having high degree of integration and high breakdown voltage, can be provided.
    Type: Application
    Filed: November 21, 2012
    Publication date: May 30, 2013
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventor: Sumitomo Electric Industries, Ltd.
  • Publication number: 20130137232
    Abstract: An oxide semiconductor film is formed over a substrate. A sacrifice film is formed to such a thickness that the local maximum of the concentration distribution of an injected substance injected into the oxide semiconductor film in the depth direction of the oxide semiconductor film is located in a region from an interface between the substrate and the oxide semiconductor film to a surface of the oxide semiconductor film. Oxygen ions are injected as the injected substance into the oxide semiconductor film through the sacrifice film at such an acceleration voltage that the local maximum of the concentration distribution of the injected substance in the depth direction of the oxide semiconductor film is located in the region, and then the sacrifice film is removed. Further, a semiconductor device is manufactured using the oxide semiconductor film.
    Type: Application
    Filed: November 27, 2012
    Publication date: May 30, 2013
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Semiconductor Energy Laboratory Co., Ltd.
  • Publication number: 20130045593
    Abstract: A silicon carbide substrate having a surface is prepared. A coating film made of a first material is formed directly on the surface of the silicon carbide substrate. A mask layer made of a second material is formed on the coating film. The first material is higher in adhesiveness with silicon carbide than the second material. A first opening is formed in the mask layer. First impurity ions for providing a first conductivity type are implanted into the silicon carbide substrate by using ion beams passing through the first opening in the mask layer and through the coating film.
    Type: Application
    Filed: August 8, 2012
    Publication date: February 21, 2013
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventor: Naoki OOI
  • Patent number: 8361893
    Abstract: An undoped semiconductor substrate is doped by applying stress at a side of the undoped semiconductor substrate to release self interstitials in the substrate and implanting chalcogen atoms into the side of the substrate. The substrate is annealed to form a first semiconductor region containing the chalcogen atoms and a second semiconductor region devoid of the chalcogen atoms. The first semiconductor region has a doping concentration higher than the doping concentration of the second semiconductor region. The indiffusion of chalcogen atoms into a semiconductor material in the presence of self interstitials can also be used to form field stop regions in power semiconductor devices.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: January 29, 2013
    Assignee: Infineon Technologies AG
    Inventors: Gerhard Schmidt, Hans-Joachim Schulze, Bernd Kolbesen
  • Patent number: 8288255
    Abstract: ZnTe is implanted with a first species selected from Group III and a second species selected from Group VII. This may be preformed using sequential implants, implants of the first species and second species that are at least partially simultaneous, or a molecular species comprising an atom selected from Group III and an atom selected from Group VII. The implants may be performed at an elevated temperature in one instance between 70° C. and 800° C.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: October 16, 2012
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Xianfeng Lu, Ludovic Godet, Anthony Renau
  • Publication number: 20120238046
    Abstract: A method of LED manufacturing is disclosed. A coating is applied to a mesa. This coating may have different thicknesses on the sidewalls of the mesa compared to the top of the mesa. Ion implantation into the mesa will form implanted regions in the sidewalls in one embodiment. These implanted regions may be used for LED isolation or passivation.
    Type: Application
    Filed: February 2, 2012
    Publication date: September 20, 2012
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: San Yu, Atul Gupta
  • Patent number: 8252196
    Abstract: A method for preparing nanotubes by providing nanorods of a piezoelectric material having an asymmetric crystal structure and by further providing hydroxide ions to the nanorods to etch inner parts of the nanorods to form the nanotubes.
    Type: Grant
    Filed: October 26, 2009
    Date of Patent: August 28, 2012
    Assignees: Samsung Electronics Co., Ltd., Kumoh National Institute of Technology
    Inventors: Jaeyoung Choi, Sangwoo Kim
  • Patent number: 8252672
    Abstract: A method of manufacturing a silicon carbide semiconductor device having a silicon carbide layer, the method including a step of implanting at least one of Al ions, B ions and Ga ions having an implantation concentration in a range not lower than 1E19 cm?3 and not higher than 1E21 cm?3 from a main surface of the silicon carbide layer toward the inside of the silicon carbide layer while maintaining the temperature of the silicon carbide layer at 175° C. or higher, to form a p-type impurity layer; and forming a contact electrode whose back surface establishes ohmic contact with a front surface of the p-type impurity layer on the front surface of the p-type impurity layer.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: August 28, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tomokatsu Watanabe, Sunao Aya, Naruhisa Miura, Keiko Sakai, Shohei Yoshida, Toshikazu Tanioka, Yukiyasu Nakao, Yoichiro Tarui, Masayuki Imaizumi
  • Patent number: 8168501
    Abstract: A semiconductor device and method of manufacture thereof wherein a PMOS source/drain region of a transistor within the substrate includes a first strained layer in the PMOS source/drain region and a first capping layer in contact with the first strained layer. Further, the semiconductor device and method provide for an NMOS source/drain region of a transistor within the substrate including a second strained layer in the NMOS source/drain region and a second capping layer in contact with the second strained layer.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: May 1, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Hua Yu, Ling-Yen Yeh, Tze-Liang Lee
  • Publication number: 20120097980
    Abstract: A termination configuration of a silicon carbide insulating gate type semiconductor device includes a semiconductor layer of a first conductivity type having a first main face, a gate electrode, and a source interconnection, as well as a circumferential resurf region. The semiconductor layer includes a body region of a second conductivity type, a source region of the first conductivity type, a contact region of the second conductivity type, and a circumferential resurf region of the second conductivity type. A width of a portion of the circumferential resurf region excluding the body region is greater than or equal to ½ the thickness of at least the semiconductor layer. A silicon carbide insulating gate type semiconductor device of high breakdown voltage and high performance can be provided.
    Type: Application
    Filed: February 7, 2011
    Publication date: April 26, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takeyoshi Masuda, Keiji Wada, Misako Honaga
  • Patent number: 8105925
    Abstract: An improved insulated gate field effect device (60) is obtained by providing a substrate (20) desirably comprising a III-V semiconductor, having a further semiconductor layer (22) on the substrate (20) adapted to contain the channel (230) of the device (60) between spaced apart source-drain electrodes (421, 422) formed on the semiconductor layer (22). A dielectric layer (24) is formed on the semiconductor layer (22). A sealing layer (28) is formed on the dielectric layer (24) and exposed to an oxygen plasma (36). A gate electrode (482) is formed on the dielectric layer (24) between the source-drain electrodes (421, 422). The dielectric layer (24) preferably comprises gallium-oxide (25) and/or gadolinium-gallium oxide (26, 27), and the oxygen plasma (36) is preferably an inductively coupled plasma. A further sealing layer (44) of, for example, silicon nitride is desirably provided above the sealing layer (28).
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: January 31, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jonathan K. Abrokwah, Ravindranath Droopad, Matthias Passlack
  • Patent number: 8084282
    Abstract: Wafer-level bonding of the hybrid laser portion of a silicon photonics platform is done by forming a weakened level in a semiconductive pillar that supports laser-active layers by ion implantation into the semiconductive pillar without penetrating the laser-active layers, and by separating the laser-active layers from the semiconductive pillar by cracking the weakened level by an epitaxial lift-off processes.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: December 27, 2011
    Assignee: Intel Corporation
    Inventors: John Heck, Richard Jones, Matthew N. Sysak
  • Patent number: 8062918
    Abstract: This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: November 22, 2011
    Assignee: Intermolecular, Inc.
    Inventors: Michael Miller, Prashant Phatak, Tony Chiang, Xiying Chen, April Schricker, Tanmay Kumar
  • Patent number: 8043947
    Abstract: A method for semiconductor processing provides a DSB semiconductor body having a first crystal orientation, a second crystal orientation, and a border region disposed between the first and second crystal orientations. The border region further has a defect associated with an interface of the first crystal orientation and second the second crystal orientation, wherein the defect generally extends a distance into the semiconductor body from a surface of the body. A sacrificial portion of the semiconductor body is removed from the surface thereof, wherein removing the sacrificial portion at least partially removes the defect. The sacrificial portion can be defined by oxidizing the surface at low temperature, wherein the oxidation at least partially consumes the defect. The sacrificial portion can also be removed by CMP. An STI feature may be further formed over the defect after removal of the sacrificial portion, therein consuming any remaining defect.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: October 25, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Angelo Pinto, Weize Xiong, Manfred Ramin