Including Multiple Implantation Steps Patents (Class 438/519)
  • Patent number: 10374043
    Abstract: In an edge termination structure portion, first and second JTE regions are disposed concentrically surrounding an active region. Between the first and second JTE regions, a p-type electric field relaxation region is disposed that includes a first subregion and a second subregion alternately and repeatedly arranged concentrically surround a periphery of the first JTE region. An average impurity concentration of the electric field relaxation region is higher that the impurity concentration of the first JTE region adjacent on the inner side and lower than the impurity concentration of the second JTE region adjacent on the outer side. First subregions have widths that decrease the farther outward they are arranged. Second subregions have widths that are substantially the same independent of position. The first subregions and the first JTE region have equal impurity concentrations. The second subregions and the second JTE region have equal impurity concentrations.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: August 6, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Shoji Kitamura
  • Patent number: 10304743
    Abstract: A semiconductor device according to this embodiment includes a semiconductor layer, a plurality of diffusion layers in the semiconductor layer, a gate insulating film, a gate electrode, first contacts, and second contacts. The gate insulating film is on the semiconductor layer between the plurality of diffusion layers. The gate electrode is on the gate insulating film. The first contacts include silicide layers of the same material which are on the gate electrode and the diffusion layers respectively, and first metal layers on the silicide layers. The second contacts are on the first contacts.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: May 28, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Naomi Fukumaki, Masaaki Hatano, Seiichi Omoto
  • Patent number: 9419133
    Abstract: P+ type regions and a p-type region are selectively disposed in a surface layer of a silicon carbide substrate base. The P+ type region is disposed in a breakdown voltage structure portion surrounding an active region. The P+ type region is disposed in the active region to make up a JBS structure. The p-type region surrounds the P+ type region to make up a junction termination (JTE) structure. A Schottky electrode forms a Schottky junction with an n-type silicon carbide epitaxial layer. The Schottky electrode overhangs an interlayer insulation film covering a portion of the P+ type region and the p-type region and this overhanging portion acts as a field plate. This enables the provision of a semiconductor device configured by using a wide band gap semiconductor capable of maintaining a high breakdown voltage with high reliability, and a method of fabricating thereof.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: August 16, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Akimasa Kinoshita, Takashi Tsuji, Kenji Fukuda
  • Patent number: 9029250
    Abstract: A method for producing semiconductor regions including impurities includes forming a trench in a first surface of a semiconductor body. Impurity atoms are implanted into a bottom of the trench. The trench is extended deeper into the semiconductor body, thereby forming a deeper trench. Impurity atoms are implanted into a bottom of the deeper trench.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: May 12, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Jens Peter Konrath, Ronny Kern, Hans-Joachim Schulze
  • Patent number: 8981337
    Abstract: The various technologies presented herein relate to a three dimensional manufacturing technique for application with semiconductor technologies. A membrane layer can be formed over a cavity. An opening can be formed in the membrane such that the membrane can act as a mask layer to the underlying wall surfaces and bottom surface of the cavity. A beam to facilitate an operation comprising any of implantation, etching or deposition can be directed through the opening onto the underlying surface, with the opening acting as a mask to control the area of the underlying surfaces on which any of implantation occurs, material is removed, and/or material is deposited. The membrane can be removed, a new membrane placed over the cavity and a new opening formed to facilitate another implantation, etching, or deposition operation. By changing the direction of the beam different wall/bottom surfaces can be utilized to form a plurality of structures.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: March 17, 2015
    Assignee: Sandia Corporation
    Inventors: David Bruce Burckel, Paul S. Davids, Paul J. Resnick, Bruce L. Draper
  • Patent number: 8955357
    Abstract: A method for embedding a dopant into a glass substrate is provided. The method may include the steps of applying the dopant to a surface of the glass substrate, positioning the glass substrate adjacent to a catalyst such that the dopant is intermediate the catalyst and the glass substrate, heating the glass substrate to a first temperature, operating a directed thermal energy source so as to generate thermal energy incident upon the dopant, reducing the temperature of the glass substrate to a second temperature below the first temperature, and holding the glass substrate at the second temperature for at least a period of time.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: February 17, 2015
    Assignee: Lighting Science Group Corporation
    Inventors: Fredric S. Maxik, David E. Bartine, Theodore Scone, Sepehr Sadeh
  • Patent number: 8951898
    Abstract: According to one embodiment, a semiconductor device includes a first, a second, a third, a fourth, and a fifth semiconductor region, an insulating film, a control electrode, and a first and a second electrode. The first, the second, the third, the fourth and the fifth semiconductor region include silicon carbide. The first semiconductor region has a first impurity concentration, and has a first portion. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The fourth semiconductor region is provided between the first portion and the second semiconductor region. The fourth semiconductor region is provided between the first portion and the third semiconductor region. The fifth semiconductor region includes a first region provided between the first portion and the second semiconductor region, and has a second impurity concentration higher than the first impurity concentration.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: February 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Kono, Takashi Shinohe, Takuma Suzuki, Johji Nishio
  • Patent number: 8912082
    Abstract: Methods to form complementary implant regions in a workpiece are disclosed. A mask may be aligned with respect to implanted or doped regions on the workpiece. The mask also may be aligned with respect to surface modifications on the workpiece, such as deposits or etched regions. A masking material also may be deposited on the implanted regions using the mask. The workpiece may be a solar cell.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: December 16, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Nicholas P. T. Bateman, William T. Weaver, Paul Sullivan, John W. Graff
  • Publication number: 20140353683
    Abstract: In a semiconductor substrate preparation step, a semiconductor substrate which is made of SiC and in which a first semiconductor region of a first conductivity type is formed is prepared. In a second semiconductor region forming step, a second semiconductor region is formed by implanting an impurity of a second conductivity type into a first semiconductor region through multiple ion implantation steps while varying implantation depths of the respective multiple ion implantation steps. In the second semiconductor region forming step, a dose amount of the impurity when an implantation energy of multiple ion implantation steps is the largest is smaller than a dose amount of impurity when the implantation energy is not the largest.
    Type: Application
    Filed: May 27, 2014
    Publication date: December 4, 2014
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Hisashi ISHIMABUSHI, Tomohiro MIMURA, Narumasa SOEJIMA
  • Patent number: 8900962
    Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include forming a base region and an emitter region in a front surface of a semiconductor layer. The method can include forming a first impurity implantation region by implanting first impurity of a first conductivity type into a back surface of the semiconductor layer. The method can include selectively forming a second impurity implantation region by selectively implanting second impurity of a second conductivity type into the first impurity implantation region. In addition, the method can include irradiating the first impurity implantation region and the second impurity implantation region with laser light. A peak of impurity concentration profile in a depth direction of at least one of the first impurity implantation region and the second impurity implantation region before irradiation with the laser light is adjusted to a depth of 0.05 ?m or more and 0.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: December 2, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Yamashita, Etsuo Hamada, Hideki Nozaki, Hironobu Shibata
  • Patent number: 8901649
    Abstract: A semiconductor device, an electrostatic discharge protection device and manufacturing method thereof are provided. The electrostatic discharge protection device includes a gate, a gate dielectric layer, an N-type source region, an N-type drain region, an N-type doped region and a P-type doped region. The gate dielectric layer is disposed on a substrate. The gate is disposed on the gate dielectric layer. The N-type source region and the N-type drain region are disposed in the substrate at two sides of the gate, respectively. The N-type doped region is disposed in the N-type drain region and connects to the top of the N-type drain region. The P-type doped region is disposed under the N-type drain region and connects to the bottom of the N-type drain region.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: December 2, 2014
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Chieh-Wei He, Shih-Yu Wang, Qi-An Xu
  • Patent number: 8860119
    Abstract: A nonvolatile memory device includes a substrate including a surface, a channel layer formed on the surface of the substrate, which protrudes perpendicularly from the surface, and a plurality of interlayer dielectric layers and a plurality of gate electrode layers alternately stacked along the channel layer, wherein the plurality of gate electrode layers protrude from the plurality of interlayer dielectric layers.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: October 14, 2014
    Assignee: SK Hynix Inc.
    Inventors: Min-Soo Kim, Dong-Sun Sheen, Seung-Ho Pyi, Sung-Jin Whang
  • Publication number: 20140291695
    Abstract: A silicon carbide device includes an epitaxial silicon carbide layer including a first conductivity type and a buried lateral silicon carbide edge termination region located within the epitaxial silicon carbide layer including a second conductivity type. The buried lateral silicon carbide edge termination region is covered by a silicon carbide surface layer including the first conductivity type.
    Type: Application
    Filed: March 26, 2013
    Publication date: October 2, 2014
    Applicant: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Christian Hecht, Roland Rupp, Rudolf Elpelt
  • Patent number: 8822315
    Abstract: A method is disclosed for treating a silicon carbide substrate for improved epitaxial deposition thereon and for use as a precursor in the manufacture of devices such as light emitting diodes. The method includes the steps of implanting dopant atoms of a first conductivity type into the first surface of a conductive silicon carbide wafer having the same conductivity type as the implanting ions at one or more predetermined dopant concentrations and implant energies to form a dopant profile, annealing the implanted wafer, and growing an epitaxial layer on the implanted first surface of the wafer.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: September 2, 2014
    Assignee: Cree, Inc.
    Inventors: Davis Andrew McClure, Alexander Suvorov, John Adam Edmond, David Beardsley Slater, Jr.
  • Patent number: 8796123
    Abstract: An impurity of a first conductivity type is implanted onto a silicon carbide substrate through an opening in a mask layer. First and second films made of first and second materials respectively are formed. It is sensed that etching of the first material is performed during anisotropic etching, and then anisotropic etching is stopped. An impurity of a second conductivity type is implanted onto the silicon carbide substrate through the opening narrowed by the first and second films. Thus, the impurity regions can be formed in an accurately self-aligned manner.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: August 5, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shunsuke Yamada, Takeyoshi Masuda
  • Patent number: 8778788
    Abstract: A semiconductor structure includes a III-nitride substrate with a first side and a second side opposing the first side. The III-nitride substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a III-nitride epitaxial structure including a first III-nitride epitaxial layer coupled to the first side of the III-nitride substrate and a plurality of III-nitride regions of a second conductivity type. The plurality of III-nitride regions have at least one III-nitride epitaxial region of the first conductivity type between each of the plurality of III-nitride regions. The semiconductor structure further includes a first metallic structure electrically coupled to one or more of the plurality of III-nitride regions and the at least one III-nitride epitaxial region. A Schottky contact is created between the first metallic structure and the at least one III-nitride epitaxial region.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: July 15, 2014
    Assignee: Avogy, Inc.
    Inventors: Andrew P. Edwards, Hui Nie, Isik C. Kizilyalli, Linda Romano, David P. Bour, Richard J. Brown, Thomas R. Prunty
  • Patent number: 8765583
    Abstract: An improved method of tilting a mask to perform a pattern implant of a substrate is disclosed. The mask has a plurality of apertures, and is placed between the ion source and the substrate. The mask and substrate are tilted at a first angle relative to the incoming ion beam. After the substrate is exposed to the ion beam, the mask and substrate are tilted at a second angle relative to the ion beam and a subsequent implant step is performed. Through the selection of the aperture size and shape, the cross-section of the mask, the distance between the mask and the substrate and the number of implant steps, a variety of implant patterns may be created. In some embodiments, the implant pattern includes heavily doped horizontal stripes with lighter doped regions between the stripes. In some embodiments, the implant pattern includes a grid of heavily doped regions.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: July 1, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Benjamin Riordon, Nicholas Bateman, Atul Gupta
  • Publication number: 20140147997
    Abstract: According to one embodiment, a semiconductor device includes a first, a second, a third, a fourth, and a fifth semiconductor region, an insulating film, a control electrode, and a first and a second electrode. The first, the second, the third, the fourth and the fifth semiconductor region include silicon carbide. The first semiconductor region has a first impurity concentration, and has a first portion. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The fourth semiconductor region is provided between the first portion and the second semiconductor region. The fourth semiconductor region is provided between the first portion and the third semiconductor region. The fifth semiconductor region includes a first region provided between the first portion and the second semiconductor region, and has a second impurity concentration higher than the first impurity concentration.
    Type: Application
    Filed: February 4, 2014
    Publication date: May 29, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi KONO, Takashi SHINOHE, Takuma SUZUKI, Johji NISHIO
  • Patent number: 8703522
    Abstract: A stratified photodiode for high resolution CMOS image sensors implemented with STI technology is provided. The photodiode includes a semi-conductive layer of a first conductivity type, multiple doping regions of a second conductivity type, multiple doping regions of the first conductivity type, and a pinning layer. The multiple doping regions of the second conductivity type are formed to different depths in the semi-conductive layer. The multiple doping regions of the first conductivity type are disposed between the multiple doping regions of the second conductivity type and form multiple junction capacitances without full depletion. In particular, the stratified doping arrangement allows the photodiode to have a small size, high charge storage capacity, low dark current, and low operation voltages.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: April 22, 2014
    Assignee: Intellectual Ventures II LLC
    Inventor: Jaroslav Hynecek
  • Patent number: 8679959
    Abstract: The present invention relates generally to methods for high throughput and controllable creation of high performance semiconductor substrates for use in devices such as high sensitivity photodetectors, imaging arrays, high efficiency solar cells and the like, to semiconductor substrates prepared according to the methods, and to an apparatus for performing the methods of the invention.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: March 25, 2014
    Assignee: Sionyx, Inc.
    Inventors: James E. Carey, Xia Li, Nathaniel J. McCaffrey
  • Patent number: 8652954
    Abstract: A method for manufacturing a silicon carbide semiconductor device includes the step of forming a mask pattern of a silicon oxide film by removing a portion of the silicon oxide film by means of etching employing a gas containing oxygen gas and at least one fluorine compound gas selected from a group consisting of CF4, C2F6, C3F8, and SF6.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: February 18, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Naoki Ooi, Hiromu Shiomi
  • Patent number: 8633080
    Abstract: A semiconductor device includes a region in a semiconductor substrate having a top surface with a first charge storage layer on the top surface. A first conductive line is on the first charge storage layer. A second charge storage layer is on the top surface. A second conductive line is on the second charge storage layer. A third charge storage layer is on the top surface. A third conductive line is on the third charge storage layer. A fourth charge storage layer has a first side adjoining a first sidewall of the first conductive line and a second side adjoining a first sidewall of the second conductive line. A fifth charge storage layer has a first side adjoining a second sidewall of the second conductive line and a second side adjoining a first sidewall of the third conductive line. Source and drain regions are formed in the substrate on either side of the semiconductor device.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: January 21, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mark D. Hall, Mehul D. Shroff
  • Patent number: 8530313
    Abstract: In according with the present invention, a semiconductor device is formed as follows. A contact insulation layer is deposited on the top surface of said silicon layer. A contact mask is applied and following with a dry oxide etching to remove the contact insulation layer from contact open areas. The silicon layer is implanted with a source dopant through the contact open areas and the source dopant is diffused to form source regions, thereby a source mask is saved. A dry silicon etch is carried out to form trenched source-body contacts in the contact open areas, penetrating through the source regions and extending into the body regions.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: September 10, 2013
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 8492250
    Abstract: A method for forming a polysilicon layer includes forming an amorphous silicon layer over a substrate, performing a first thermal treatment of the amorphous silicon layer by performing an implantation with a gas that includes silicon (Si), and performing a second thermal treatment on the thermally treated layer at a temperature higher than a temperature of the first thermal treatment.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: July 23, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Eun-Jung Ko
  • Patent number: 8487280
    Abstract: A first species is implanted into an entire surface of a workpiece and helium is implanted into this entire surface with a non-uniform dose. The first species may be, for example, hydrogen, helium, or nitrogen. The helium has a higher dose at a portion of a periphery of the workpiece. When the workpiece is split, this split is initiated at the periphery with the higher dose. The non-uniform dose may be formed by altering a scan speed of the workpiece or an ion beam current of the helium. In one instance, the non-uniform dose of the helium is larger than a uniform dose of the hydrogen.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: July 16, 2013
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Gary E. Dickerson, Julian G. Blake
  • Patent number: 8476133
    Abstract: A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.
    Type: Grant
    Filed: January 11, 2010
    Date of Patent: July 2, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Brian Sze-Ki Mo, Duc Chau, Steven Sapp, Izak Bencuya, Dean Edward Probst
  • Patent number: 8461028
    Abstract: A method and semiconductor device for synthesizing graphene using ion implantation of carbon. Carbon is implanted in a metal using ion implantation. After the carbon is distributed in the metal, the metal is annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the surface of the metal. The metal/graphene surface is then transferred to a dielectric layer in such a manner that the graphene layer is placed on top of the dielectric layer. The metal layer is then removed. Alternatively, recessed regions are patterned and etched in a dielectric layer located on a substrate. Metal is later formed in these recessed regions. Carbon is then implanted into the metal using ion implantation. The metal may then be annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the metal's surface.
    Type: Grant
    Filed: October 8, 2012
    Date of Patent: June 11, 2013
    Assignee: Board of Regents, The University of Texas System
    Inventors: Luigi Colombo, Robert M. Wallace, Rodney S. Ruoff
  • Patent number: 8460977
    Abstract: A method of forming an electronic device, including forming a preliminary buffer layer on a drift layer, forming a first layer on the preliminary buffer layer, selectively etching the first layer to form a first mesa that exposes a portion of the preliminary buffer layer, and selectively etching the exposed portion of the preliminary buffer layer to form a second mesa that covers a first portion of the drift layer, that exposes a second portion of the drift layer, and that includes a mesa step that protrudes from the first mesa. Dopants are selectively implanted into the drift layer adjacent the second mesa to form a junction termination region in the drift layer. Dopants are selectively implanted through a horizontal surface of the mesa step into a portion of the drift layer beneath the mesa step to form a buried junction extension in the drift layer.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: June 11, 2013
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Anant K. Agarwal
  • Patent number: 8409975
    Abstract: A method for decreasing polysilicon gate resistance in a carbon co-implantation process which includes: depositing a first salicide block layer on a formed gate of a MOS device and etching it to form a first spacer of a side surface of the gate of the MOS device; performing a P-type heavily doped boron implantation process and a thermal annealing treatment, so as to decrease the resistance of the polysilicon gate; removing said first spacer, performing a lightly doped drain process, and performing a carbon co-implantation process at the same time, so as to form ultra-shallow junctions at the interfaces between a substrate and source region and drain region below the gate; re-depositing a second salicide block layer on the gate and etching the mask to form a second spacer; forming a self-aligned silicide on the surface of the MOS device. The invention can decrease the resistance of the P-type polysilicon gate.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: April 2, 2013
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventor: Liujiang Yu
  • Patent number: 8377807
    Abstract: Defects in a semiconductor substrate due to ion implantation are minimized by forming an implant region in the semiconductor substrate and subjecting the semiconductor substrate to a first anneal to recrystallize the semiconductor substrate. The semiconductor substrate is subjected to a second anneal to suppress diffusion of implanted ions in the semiconductor substrate. The first anneal being at a lower temperature and longer duration than the second anneal.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: February 19, 2013
    Assignee: Suvolta, Inc.
    Inventors: Lucian Shifren, Taiji Ema
  • Patent number: 8372709
    Abstract: A method of forming a semiconductor device includes forming an interfacial layer on a semiconductor substrate, forming a high-k dielectric on the interfacial layer, forming a barrier metal on the high-k dielectric, forming a poly-silicon layer on the barrier metal, patterning the interfacial layer, the high-k dielectric, the barrier metal and the poly-silicon to form a gate stack forming spacers, extension regions, sidewalls and source/drain regions, forming an interlayer dielectric on the gate stack, etching off a portion of the interlayer dielectric to expose the poly-silicon layer, forming an impurity metal layer, which includes an impurity metal having a barrier effect to the diffusive material, and a metal layer including a diffusive material, on the poly-silicon layer and converting the poly-Si layer into a silicide containing the impurity metal. The barrier metal includes a titanium nitride (TiN) or a tantalum nitride (TaN).
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: February 12, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroshi Sunamura
  • Patent number: 8343815
    Abstract: A tunnel field effect transistor (TFET) includes a source region, the source region comprising a first portion of a nanowire; a channel region, the channel region comprising a second portion of the nanowire; a drain region, the drain region comprising a portion of a silicon pad, the silicon pad being located adjacent to the channel region; and a gate configured such that the gate surrounds the channel region and at least a portion of the source region.
    Type: Grant
    Filed: May 11, 2010
    Date of Patent: January 1, 2013
    Assignee: International Business Machines Corporation
    Inventors: Sarunya Bangsaruntip, Isaac Lauer, Amlan Majumdar, Jeffrey Sleight
  • Publication number: 20120315746
    Abstract: An impurity of a first conductivity type is implanted onto a silicon carbide substrate through an opening in a mask layer. First and second films made of first and second materials respectively are formed. It is sensed that etching of the first material is performed during anisotropic etching, and then anisotropic etching is stopped. An impurity of a second conductivity type is implanted onto the silicon carbide substrate through the opening narrowed by the first and second films. Thus, the impurity regions can be formed in an accurately self-aligned manner.
    Type: Application
    Filed: June 5, 2012
    Publication date: December 13, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Shunsuke YAMADA, Takeyoshi MASUDA
  • Patent number: 8318571
    Abstract: A method for forming a MOS device with an ultra shallow lightly doped diffusion region includes providing a gate dielectric layer overlying a substrate surface region, forming a gate structure overlying the gate dielectric layer, performing a first implant process using a germanium species to form an amorphous region within an LDD region using the gate structure as a mask, and performing a second implant process in the LDD region using a P-type impurity and a carbon species. A first thermal process activates the P-type impurity in the LDD region, forming side wall spacers overlying the gate structure, and performing a third implant process using a first impurity to form active source/drain regions in a vicinity of the surface region adjacent to the gate structure using the gate structure and the spacers as a mask. A second thermal process then activates the first impurity in the active source/drain regions.
    Type: Grant
    Filed: October 24, 2008
    Date of Patent: November 27, 2012
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Chia Hao Lee
  • Patent number: 8298889
    Abstract: An electronic device can include a first layer having a primary surface, a well region lying adjacent to the primary surface, and a buried doped region spaced apart from the primary surface and the well region. The electronic device can also include a trench extending towards the buried doped region, wherein the trench has a sidewall, and a sidewall doped region along the sidewall of the trench, wherein the sidewall doped region extends to a depth deeper than the well region. The first layer and the buried region have a first conductivity type, and the well region has a second conductivity type opposite that of the first conductivity type. The electronic device can include a conductive structure within the trench, wherein the conductive structure is electrically connected to the buried doped region and is electrically insulated from the sidewall doped region. Processes for forming the electronic device are also described.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: October 30, 2012
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Jaume Roig-Guitart, Peter Moens, Marnix Tack
  • Patent number: 8293629
    Abstract: Embodiments of a process for forming a photodetector region in a CMOS pixel by dopant implantation, the process comprising masking a photodetector area of a surface of a substrate for formation of the photodetector region, positioning the substrate at a plurality of twist angles, and at each of the plurality of twist angles, directing dopants at the photodetector area at a selected tilt angle. Embodiments of a CMOS pixel comprising a photodetector region formed in a substrate, the photodetector region comprising overlapping first and second dopant implants, wherein the overlap region has a different dopant concentration than the non-overlapping parts of the first and second implants, a floating diffusion formed in the substrate, and a transfer gate formed on the substrate between the photodetector and the transfer gate. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: October 23, 2012
    Assignee: OmniVision Technologies, Inc.
    Inventors: Duli Mao, Hsin-Chih Tai, Vincent Venezia, Yin Qian, Howard E. Rhodes
  • Patent number: 8288255
    Abstract: ZnTe is implanted with a first species selected from Group III and a second species selected from Group VII. This may be preformed using sequential implants, implants of the first species and second species that are at least partially simultaneous, or a molecular species comprising an atom selected from Group III and an atom selected from Group VII. The implants may be performed at an elevated temperature in one instance between 70° C. and 800° C.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: October 16, 2012
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Xianfeng Lu, Ludovic Godet, Anthony Renau
  • Patent number: 8278197
    Abstract: The invention provides a method to enhance the programmability of a prompt-shift device, which reduces the programming time to sub-millisecond times, by altering the extension and halo implants, instead of simply omitting the same from one side of the device as is the case in the prior art prompt-shift devices. The invention includes an embodiment in which no additional masks are employed, or one additional mask is employed. The altered extension implant is performed at a reduced ion dose as compared to a conventional extension implant process, while the altered halo implant is performed at a higher ion dose than a conventional halo implant. The altered halo/extension implant shifts the peak of the electrical field to under an extension dielectric spacer.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: October 2, 2012
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. Breitwisch, Roger W. Cheek, Jeffrey B. Johnson, Chung H. Lam, Beth A. Rainey, Michael J. Zierak
  • Patent number: 8278711
    Abstract: A substrate having semiconductor material and a surface that supports a gate electrode and defines a surface normal direction is provided. The substrate can include a drift region including a first dopant type. A well region can be disposed adjacent to the drift region and proximal to the surface, and can include a second dopant type. A termination extension region can be disposed adjacent to the well region and extend away from the gate electrode, and can have an effective concentration of second dopant type that is generally less than that in the well region. An adjust region can be disposed between the surface and at least part of the termination extension region. An effective concentration of second dopant type may generally decrease when moving from the termination extension region into the adjust region along the surface normal direction.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: October 2, 2012
    Assignee: General Electric Company
    Inventors: Ramakrishna Rao, Stephen Daley Arthur, Peter Almern Losee, Kevin Dean Matocha
  • Patent number: 8258052
    Abstract: A method of manufacturing a silicon carbide semiconductor device according to the present invention includes the steps of (a) forming an implantation mask made up of a plurality of unit masks on a silicon carbide semiconductor layer, and (b) implanting predetermined ion in the silicon carbide semiconductor layer at a predetermined implantation energy by using the implantation mask. In the step (a), the implantation mask is formed such that a length from any point in the unit mask to an end of the unit mask can be equal to or less than a scattering length obtained when the predetermined ion is implanted in silicon carbide at the predetermined implantation energy and the implantation mask can have a plurality of regions different from each other in terms of a size and an arrangement interval of the unit masks.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: September 4, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Koji Okuno, Yoichiro Tarui
  • Patent number: 8247286
    Abstract: One embodiment of inventive concepts exemplarily described herein may be generally characterized as a semiconductor device including an isolation region within a substrate. The isolation region may define an active region. The active region may include an edge portion that is adjacent to an interface of the isolation region and the active region and a center region that is surrounded by the edge portion. The semiconductor device may further include a gate electrode on the active region and the isolation region. The gate electrode may include a center gate portion overlapping a center portion of the active region, an edge gate portion overlapping the edge portion of the active region, and a first impurity region of a first conductivity type within the center gate portion and outside the edge portion. The semiconductor device may further include a gate insulating layer disposed between the active region and the gate electrode.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: August 21, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dong-Ryul Chang
  • Patent number: 8242005
    Abstract: A first species is directed through a first mask with a first aperture and a second mask with a second aperture. The first aperture and second aperture may be different shapes or have different spacing. The first species may be implanted in pattern defining non-implanted regions surrounded by implanted regions. These implanted regions are a sum of said first ion species implanted through said first aperture and said second aperture. Thus, the non-implanted regions are surrounded by the implanted regions formed using the first mask and second mask. The first species also may deposit on or etch the workpiece.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: August 14, 2012
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventor: Justin M. Ricci
  • Publication number: 20120202341
    Abstract: ZnTe is implanted with a first species selected from Group III and a second species selected from Group VII. This may be preformed using sequential implants, implants of the first species and second species that are at least partially simultaneous, or a molecular species comprising an atom selected from Group III and an atom selected from Group VII. The implants may be performed at an elevated temperature in one instance between 70° C. and 800° C.
    Type: Application
    Filed: February 2, 2012
    Publication date: August 9, 2012
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Xiangfeng LU, Ludovic GODET, Anthony RENAU
  • Publication number: 20120202340
    Abstract: ZnTe is implanted with a first species selected from Group III and a second species selected from Group VII. This may be performed using sequential implants, implants of the first species and second species that are at least partially simultaneous, or a molecular species comprising an atom selected from Group III and an atom selected from Group VII. The implants may be performed at an elevated temperature in one instance between 70° C. and 800° C.
    Type: Application
    Filed: February 4, 2011
    Publication date: August 9, 2012
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Xianfeng LU, Ludovic GODET, Anthony RENAU
  • Patent number: 8232162
    Abstract: A method of forming a deep trench structure for a semiconductor device includes forming a mask layer over a semiconductor substrate. An opening in the mask layer is formed by patterning the mask layer, and a deep trench is formed in the semiconductor substrate using the patterned opening in the mask layer. A sacrificial fill material is formed over the mask layer and into the deep trench. A first portion of the sacrificial fill material is recessed from the deep trench and a first dopant implant forms a first doped region in the semiconductor substrate. A second portion of the sacrificial fill material is recessed from the deep trench and a second dopant implant forms a second doped region in the semiconductor substrate, wherein the second doped region is formed underneath the first doped region such that the second doped region and the first doped region are contiguous with each other.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: July 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Roger A. Booth, Jr., Kangguo Cheng, Joseph Ervin, Chengwen Pei, Ravi M. Todi, Geng Wang, Yanli Zhang
  • Publication number: 20120184092
    Abstract: A method for manufacturing a silicon carbide semiconductor device includes the step of forming a mask pattern of a silicon oxide film by removing a portion of the silicon oxide film by means of etching employing a gas containing oxygen gas and at least one fluorine compound gas selected from a group consisting of CF4, C2F6, C3F8, and SF6.
    Type: Application
    Filed: January 17, 2012
    Publication date: July 19, 2012
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Naoki OOI, Hiromu Shiomi
  • Patent number: 8216923
    Abstract: An improved, lower cost method of processing substrates, such as to create solar cells is disclosed. In addition, a modified substrate carrier is disclosed. The carriers typically used to carry the substrates are modified so as to serve as shadow masks for a patterned implant. In some embodiments, various patterns can be created using the carriers such that different process steps can be performed on the substrate by changing the carrier or the position with the carrier. In addition, since the alignment of the substrate to the carrier is critical, the carrier may contain alignment features to insure that the substrate is positioned properly on the carrier. In some embodiments, gravity is used to hold the substrate on the carrier, and therefore, the ions are directed so that the ion beam travels upward toward the bottom side of the carrier.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: July 10, 2012
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Nicholas Bateman, Kevin Daniels, Atul Gupta, Russell Low, Benjamin Riordon, Robert Mitchell, Steven Anella
  • Patent number: 8202789
    Abstract: Various masks for use with ion implantation equipment are disclosed. In one embodiment, the masks are formed by assembling a collection of segments and spacers to create a mask having the desired configuration. This collection of parts is held together with a carrier or frame. In another embodiment, a panel is formed by machining open-ended slots into a substrate, so as to form a comb-shaped device. Two such panels may be connected together to form a mask. In other embodiments, the panels may be used sequentially in an ion implantation process to create interdigitated back contacts. In another embodiment, multiple masks are overlaid so as to create implant patterns that cannot be created effectively using a single mask.
    Type: Grant
    Filed: September 8, 2009
    Date of Patent: June 19, 2012
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Steven M. Anella, William Weaver
  • Patent number: 8198659
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device. A method of manufacturing a semiconductor device may include forming a gate electrode over a semiconductor substrate, a second conductive type ion implantation region at opposite sides of a gate electrode, a second conductive type ion implantation region as a first conductive type second ion implantation region by implanting a first conductive type impurity over opposite sides of said gate electrode, and/or forming a first conductive type first ion implantation region that substantially surrounds a first conductive type second ion implantation region. A method of manufacturing a semiconductor device may form an N type MOSFET and/or a P type MOSFET using a single photolithography process for each N+ source/drain photolithography process and/or P+ source/drain photolithography process.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: June 12, 2012
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Kyung-Wook Kwon
  • Patent number: 8187957
    Abstract: A field-effect transistor that increases the operation speeds of complementary field-effect transistors. Each of an nMOSFET and a pMODFET has a Ge channel and source and drain regions formed of an NiGe layer. The height of Schottky barriers formed at a junction between a channel region and the source region of the nMOSFET and at a junction between the channel region and the drain region of the nMOSFET is changed by very thin high-concentration segregation layers formed by making As atoms, Sb atoms, S atoms or the like segregate at the time of forming the NiGe layer. As a result, Schottky barrier height suitable for the nMOSFET and the pMODFET can be obtained, this being capable of realizing high-speed CMOSFETS.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: May 29, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Keiji Ikeda