Including Heat Treatment Patents (Class 438/522)
  • Patent number: 10319599
    Abstract: A method of planarizing a roughened surface of a SiC substrate includes: forming a sacrificial material on the roughened surface of the SiC substrate, the sacrificial material having a density between 35% and 120% of the density of the SiC substrate; implanting ions through the sacrificial material and into the roughened surface of the SiC substrate to form an amorphous region in the SiC substrate; and removing the sacrificial material and the amorphous region of the SiC substrate by wet etching.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: June 11, 2019
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Helmut Oefner, Roland Rupp
  • Patent number: 9769880
    Abstract: Flash light is emitted from flash lamps to the surface of a semiconductor substrate on which a metal layer has been formed for one second or less to momentarily raise temperature on the surface of the semiconductor substrate including the metal layer and an impurity region to a processing temperature of 1000° C. or more. Heat treatment is performed by emitting flash light to the surface of the semiconductor substrate in a forming gas atmosphere containing hydrogen. By heating the surface of the semiconductor substrate to a high temperature in the forming gas atmosphere for an extremely short time period, contact resistance can be reduced without desorbing hydrogen taken in the vicinity of an interface of a gate oxide film for hydrogen termination.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: September 19, 2017
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Takayuki Aoyama, Shinichi Kato
  • Patent number: 9698017
    Abstract: A manufacturing method of a semiconductor device is provided by forming a trench in a surface of a SiC substrate, positioning a protective substrate to cover the trench, and annealing the SiC substrate and the protective substrate.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: July 4, 2017
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Tomoharu Ikeda, Shinichiro Miyahara, Sachiko Aoi
  • Patent number: 9312293
    Abstract: Image sensors may include a plurality of photodiodes. The photodiodes may be isolated from each other using isolations regions formed from p-well or n-well implants. Deep and narrow isolation regions may be formed using a multi-step process that selectively places implants at desired depths in a substrate. If desired, the multi-step process may include only one photolithographic patterning step, which in turn can help reduce costs, fabrication time, and alignment errors. The process may include passing ions through a stack of alternating layers of material such as alternating layers of oxide and nitride. After each implant, a layer in the stack may be removed and ions may be passed through the layers remaining in the stack to form an implant at a different depth in the substrate.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: April 12, 2016
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Satyadev Nagaraja, Rayner Barboza, Giovanni Margutti
  • Patent number: 9105565
    Abstract: According to one embodiment, a nitride semiconductor device includes semiconductor stacked layers provided on a substrate and including a nitride semiconductor; a source electrode and a drain electrode provided on the layers and being in contact with the layers; and a gate electrode provided on the layers and provided between the source electrode and the drain electrode. The layers have a first barrier layer, a second barrier layer, and a carrier running layer interposed between the first barrier layer and the second barrier layer. The second barrier layer and the carrier running layer are removed in a region in which the source electrode on the layers is provided. A part of the source electrode is in contact with the first barrier layer. And another part of the source electrode other than the part of the source electrode is in contact with the second barrier layer.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: August 11, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masahiko Kuraguchi
  • Patent number: 9059081
    Abstract: The present invention is generally directed to methods of selectively doping a substrate and the resulting selectively doped substrates. The methods include doping an epilayer of a substrate with the selected doping material to adjust the conductivity of either the epilayers grown over a substrate or the substrate itself. The methods utilize lithography to control the location of the doped regions on the substrate. The process steps can be repeated to form a cyclic method of selectively doping different areas of the substrate with the same or different doping materials to further adjust the properties of the resulting substrate.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: June 16, 2015
    Assignee: University of South Carolina
    Inventors: Asif Khan, Vinod Adivarahan
  • Patent number: 9040398
    Abstract: Methods of forming semiconductor devices are provided by forming a semiconductor layer on a semiconductor substrate. A mask is formed on the semiconductor layer. Ions having a first conductivity type are implanted into the semiconductor layer according to the mask to form implanted regions on the semiconductor layer. Metal layers are formed on the implanted regions according to the mask. The implanted regions and the metal layers are annealed in a single step to respectively activate the implanted ions in the implanted regions and provide ohmic contacts on the implanted regions. Related devices are also provided.
    Type: Grant
    Filed: May 16, 2006
    Date of Patent: May 26, 2015
    Assignee: Cree, Inc.
    Inventors: Adam William Saxler, Scott Sheppard
  • Patent number: 9020002
    Abstract: Photonic integrated circuits on silicon are disclosed. By bonding a wafer of compound semiconductor material as an active region to silicon and removing the substrate, the lasers, amplifiers, modulators, and other devices can be processed using standard photolithographic techniques on the silicon substrate. A silicon laser intermixed integrated device in accordance with one or more embodiments of the present invention comprises a silicon-on-insulator substrate, comprising at least one waveguide in a top surface, and a compound semiconductor substrate comprising a gain layer, the compound semiconductor substrate being subjected to a quantum well intermixing process, wherein the upper surface of the compound semiconductor substrate is bonded to the top surface of the silicon-on-insulator substrate.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: April 28, 2015
    Assignee: The Regents of the University of California
    Inventors: Matthew N. Sysak, John E. Bowers, Alexander W. Fang, Hyundai Park
  • Publication number: 20150099350
    Abstract: Embodiments of the present disclosure generally relate to doping and annealing substrates. The substrates may be doped during a hot implantation process, and subsequently annealed using a nanosecond annealing process. The combination of hot implantation and nanosecond annealing reduces lattice damage of the substrates and facilitates a higher dopant concentration near the surface of the substrate to facilitate increased electrical contact with the substrate. An optional capping layer may be placed over the substrate to reduce outgassing of dopants or to control dopant implant depth.
    Type: Application
    Filed: October 1, 2014
    Publication date: April 9, 2015
    Inventors: Swaminathan T. SRINIVASAN, Fareen Adeni KHAJA
  • Patent number: 8998606
    Abstract: An apparatus for uniform reactive thermal treatment of thin-film materials includes a chamber enclosing a tube shaped space filled with a work gas and heaters disposed outside the chamber. The apparatus further includes a loading configuration for subjecting a plurality of planar substrates to the work gas in the tube shaped space. Baffles are disposed above and below the loading configuration.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: April 7, 2015
    Assignee: Stion Corporation
    Inventors: Paul Alexander, Steven Aragon
  • Patent number: 8962459
    Abstract: A method selectively diffuses dopants into a substrate wafer. The method comprises blanket depositing a doped liquid precursor including dopants on a surface of the substrate wafer to create a doped film on the surface of the substrate wafer, selectively forming a diffusion source in the doped film to selectively diffuse the dopants into the substrate wafer, and heating the doped film on the substrate wafer, wherein said heating the doped film diffuses the dopants from the doped film into the substrate wafer.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: February 24, 2015
    Assignee: Piquant Research LLC
    Inventor: Daniel Inns
  • Patent number: 8955357
    Abstract: A method for embedding a dopant into a glass substrate is provided. The method may include the steps of applying the dopant to a surface of the glass substrate, positioning the glass substrate adjacent to a catalyst such that the dopant is intermediate the catalyst and the glass substrate, heating the glass substrate to a first temperature, operating a directed thermal energy source so as to generate thermal energy incident upon the dopant, reducing the temperature of the glass substrate to a second temperature below the first temperature, and holding the glass substrate at the second temperature for at least a period of time.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: February 17, 2015
    Assignee: Lighting Science Group Corporation
    Inventors: Fredric S. Maxik, David E. Bartine, Theodore Scone, Sepehr Sadeh
  • Patent number: 8951895
    Abstract: Improved complementary doping methods are described herein. The complementary doping methods generally involve inducing a first and second chemical reaction in at least a first and second portion, respectively, of a dopant source, which has been disposed on a thin film of a semiconductor or semimetal material. The chemical reactions result in the introduction of an n-type dopant, a p-type dopant, or both from the dopant source to each of the first and second portions of the thin film of the semiconductor or semimetal. Ultimately, the methods produce at least one n-type and at least one p-type region in the thin film of the semiconductor or semimetal.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: February 10, 2015
    Assignee: Georgia Tech Research Corporation
    Inventors: Kevin Andrew Brenner, Raghunath Murali
  • Patent number: 8946006
    Abstract: A disposable dielectric spacer is formed on sidewalls of a disposable material stack. Raised source/drain regions are formed on planar source/drain regions by selective epitaxy. The disposable dielectric spacer is removed to expose portions of a semiconductor layer between the disposable material stack and the source/drain regions including the raised source/drain regions. Dopant ions are implanted to form source/drain extension regions in the exposed portions of the semiconductor layer. A gate-level dielectric layer is deposited and planarized. The disposable material stack is removed and a gate stack including a gate dielectric and a gate electrode fill a cavity formed by removal of the disposable material stack. Optionally, an inner dielectric spacer may be formed on sidewalls of the gate-level dielectric layer within the cavity prior to formation of the gate stack to tailor a gate length of a field effect transistor.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Shom Ponoth, David V. Horak, Chih-Chao Yang
  • Publication number: 20150028350
    Abstract: Methods of forming a semiconductor structure include the use of channeled implants into silicon carbide crystals. Some methods include providing a silicon carbide layer having a crystallographic axis, heating the silicon carbide layer to a temperature of about 300° C. or more, implanting dopant ions into the heated silicon carbide layer at an implant angle between a direction of implantation and the crystallographic axis of less than about 2°, and annealing the silicon carbide layer at a time-temperature product of less than about 30,000° C.-hours to activate the implanted ions.
    Type: Application
    Filed: May 19, 2014
    Publication date: January 29, 2015
    Applicant: Cree, Inc.
    Inventors: Alexander V. Suvorov, Vipindas Pala
  • Publication number: 20150017792
    Abstract: A method of forming a doped region in a III-nitride substrate includes providing the III-nitride substrate and forming a masking layer having a predetermined pattern and coupled to a portion of the III-nitride substrate. The III-nitride substrate is characterized by a first conductivity type and the predetermined pattern defines exposed regions of the III-nitride substrate. The method also includes heating the III-nitride substrate to a predetermined temperature and placing a dual-precursor gas adjacent the exposed regions of the III-nitride substrate. The dual-precursor gas includes a nitrogen source and a dopant source. The method further includes maintaining the predetermined temperature for a predetermined time period, forming p-type III-nitride regions adjacent the exposed regions of the III-nitride substrate, and removing the masking layer.
    Type: Application
    Filed: September 26, 2014
    Publication date: January 15, 2015
    Inventors: David P. Bour, Richard J. Brown, Isik C. Kizilyalli, Thomas R. Prunty, Linda Romano, Andrew P. Edwards, Hui Nie, Mahdan Raj
  • Patent number: 8921181
    Abstract: Methods for forming an electronic device having a fluorine-stabilized semiconductor substrate surface are disclosed. In an exemplary embodiment, a layer of a high-? dielectric material is formed together with a layer containing fluorine on a semiconductor substrate. Subsequent annealing causes the fluorine to migrate to the surface of the semiconductor (for example, silicon, germanium, or silicon-germanium). A thin interlayer of a semiconductor oxide may also be present at the semiconductor surface. The fluorine-containing layer can comprise F-containing WSix formed by ALD from WF6 and SiH4 precursor gases. A precise amount of F can be provided, sufficient to bind to substantially all of the dangling semiconductor atoms at the surface of the semiconductor substrate and sufficient to displace substantially all of the hydrogen atoms present at the surface of the semiconductor substrate.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: December 30, 2014
    Assignee: Intermolecular, Inc.
    Inventor: Dipankar Pramanik
  • Patent number: 8921206
    Abstract: First, a substrate with a recess is provided in a semiconductor process. Second, an embedded SiGe layer is formed in the substrate. The embedded SiGe layer includes an epitaxial SiGe material which fills up the recess. Then, a pre-amorphization implant (PAI) procedure is carried out on the embedded SiGe layer to form an amorphous region. Next, a source/drain implanting procedure is carried out on the embedded SiGe layer to form a source doping region and a drain doping region. Later, a source/drain annealing procedure is carried out to form a source and a drain in the substrate. At least one of the pre-amorphization implant procedure and the source/drain implanting procedure is carried out in a cryogenic procedure below ?30° C.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: December 30, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chan-Lon Yang, Ching-I Li, Ger-Pin Lin, I-Ming Lai, Yun-San Huang, Chin-I Liao, Chin-Cheng Chien
  • Patent number: 8906786
    Abstract: A single crystal SiC substrate is produced with low cost in which a polycrystalline SiC substrate with relatively low cost is used as a base material substrate where the single crystal SiC substrate has less strain, good crystallinity and large size. The method including a P-type ion introduction step for implanting P-type ions from a side of a surface Si layer 3 into an SOI substrate 1 in which the surface Si layer 3 and an embedded oxide layer 4 having a predetermined thickness are formed on an Si base material layer 2 to convert the embedded oxide layer 4 into a PSG layer 6 to lower a softening point, and an SiC forming step for heating the SOI substrate 1 having the PSG layer 6 formed therein in an atmosphere hydrocarbon-based gas to convert the surface Si layer 3 into SiC, and thereafter, cooling the resulting substrate to form a single crystal SiC layer 5 on a surface thereof.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: December 9, 2014
    Assignee: Air Water Inc.
    Inventors: Katsutoshi Izumi, Takashi Yokoyama
  • Publication number: 20140346529
    Abstract: A semiconductor-device manufacturing method of the present invention includes a step of selectively implanting impurity ions into a surface of an SiC semiconductor layer and forming impurity regions and a step of activating the impurity ions by annealing the SiC semiconductor layer at a temperature of 1400° C. or more when the surface of the SiC semiconductor layer is covered with an insulating film.
    Type: Application
    Filed: May 21, 2014
    Publication date: November 27, 2014
    Inventors: Yuki NAKANO, Ryota NAKAMURA
  • Publication number: 20140335684
    Abstract: A manufacturing method for a semiconductor device includes implanting dopants into a silicon carbide substrate, applying a carbon-containing material on at least one surface of the silicon carbide substrate, and heating the silicon carbide substrate having the carbon-containing material applied thereon to form a carbon layer on surfaces of the silicon carbide substrate. The heating is performed in a non-oxidizing atmosphere, and is followed by another heating step for activating the dopants.
    Type: Application
    Filed: February 28, 2014
    Publication date: November 13, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Makoto MIZUKAMI, Naoko YANASE, Atsuko YAMASHITA
  • Patent number: 8874254
    Abstract: An object of the present invention is to perform temperature setting of a heating plate so that a wafer is uniformly heated in an actual heat processing time. The temperature of a wafer is measured during a heat processing period from immediately after a temperature measuring wafer is mounted on the heating plate to the time when the actual heat processing time elapses. Whether the uniformity in temperature within the wafer is allowable or not is determined from the temperature of the wafer in the heat processing period, and if the determination result is negative, a correction value for a temperature setting parameter of the heating plate is calculated using a correction value calculation model from the measurement result, and the temperature setting parameter is changed.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: October 28, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Shuji Iwanaga, Nobuyuki Sata
  • Patent number: 8871566
    Abstract: A thin film transistor includes a gate electrode, a first insulating layer on the gate electrode, a semiconductor layer on the gate electrode and separated from the gate electrode by the first insulating layer, the semiconductor layer including a channel region corresponding to the gate electrode, a source region, and a drain region, a hydrogen diffusion barrier layer on the semiconductor layer, the hydrogen diffusion barrier layer covering the channel region and exposing the source and drain regions, and a second insulation layer on the source and drain regions and on the hydrogen diffusion barrier layer, such that the hydrogen diffusion barrier layer is between the second insulation layer and the channel region.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: October 28, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyun-soo Shin, Yeon-gon Mo, Jae-kyeong Jeong, Jin-seong Park, Hun-jung Lee, Jong-han Jeong
  • Patent number: 8835288
    Abstract: A method of manufacturing a silicon carbide semiconductor device of an embodiment includes: implanting ions in a silicon carbide substrate; performing first heating processing of the silicon carbide substrate in which the ions are implanted; and performing second heating processing of the silicon carbide substrate for which the first heating processing is performed, at a temperature lower than the first heating processing.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: September 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Johji Nishio, Masaru Furukawa, Hiroshi Kono, Takashi Shinohe
  • Patent number: 8822315
    Abstract: A method is disclosed for treating a silicon carbide substrate for improved epitaxial deposition thereon and for use as a precursor in the manufacture of devices such as light emitting diodes. The method includes the steps of implanting dopant atoms of a first conductivity type into the first surface of a conductive silicon carbide wafer having the same conductivity type as the implanting ions at one or more predetermined dopant concentrations and implant energies to form a dopant profile, annealing the implanted wafer, and growing an epitaxial layer on the implanted first surface of the wafer.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: September 2, 2014
    Assignee: Cree, Inc.
    Inventors: Davis Andrew McClure, Alexander Suvorov, John Adam Edmond, David Beardsley Slater, Jr.
  • Patent number: 8778766
    Abstract: A field effect transistor of an embodiment of the present invention includes, a semiconductor substrate containing Si atoms; a protruding structure formed on the semiconductor substrate; a channel region formed in the protruding structure and containing Ge atoms; an under channel region formed under the channel region in the protruding structure and containing Si and Ge atoms, the Ge composition ratio among Si and Ge atoms contained in the under channel region continuously changing from the channel region side to the semiconductor substrate side; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film on the channel region.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: July 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsutomu Tezuka, Toshifumi Irisawa
  • Publication number: 20140147998
    Abstract: There are disclosed herein various implementations of a method and system for ion implantation at high temperature surface equilibrium conditions. The method may include situating a III-Nitride semiconductor body in a surface equilibrium chamber, establishing a gas pressure greater than or approximately equal to a surface equilibrium pressure of the III-Nitride semiconductor body, and heating the III-Nitride semiconductor body to an elevated implantation temperature in the surface equilibrium chamber while substantially maintaining the gas pressure. The method also includes implanting the III-Nitride semiconductor body in the surface equilibrium at the elevated implantation temperature chamber while substantially maintaining the gas pressure, the implanting being performed using an ion implanter interfacing with the surface equilibrium chamber.
    Type: Application
    Filed: January 31, 2014
    Publication date: May 29, 2014
    Applicant: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Patent number: 8722482
    Abstract: A semiconductor is formed on a (110) silicon (Si) substrate, with improved electron mobility. Embodiments include semiconductor devices having a silicon carbide (SiC) portion in the nFET channel region. An embodiment includes forming an nFET channel region and a pFET channel region in a Si substrate, such as a (110) Si substrate, and forming a silicon carbide (SiC) portion on the nFET channel region. The SiC portion may be formed by ion implantation of C followed by a recrystallization anneal or by epitaxial growth of SiC in a recess formed in the substrate. The use of SiC in the nFET channel region improves electron mobility without introducing topographical differences between NMOS and PMOS transistors.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: May 13, 2014
    Assignee: GlobalFoundries Inc.
    Inventors: Jeremy A. Wahl, Kingsuk Maitra
  • Patent number: 8704229
    Abstract: Semiconductor devices are formed without zipper defects or channeling and through-implantation and with different silicide thicknesses in the gates and source/drain regions, Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region in the substrate on each side of the gate, forming a wet cap fill layer on the source/drain region on each side of the gate, removing the nitride cap from the gate, and forming an amorphized layer in a top portion of the gate. Embodiments include forming the amorphized layer by implanting low energy ions.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: April 22, 2014
    Assignee: GlobalFoundries Inc.
    Inventors: Peter Javorka, Glyn Braithwaite
  • Patent number: 8697555
    Abstract: The invention offers a method of producing a semiconductor device that can suppress the worsening of the property due to surface roughening of a wafer by sufficiently suppressing the surface roughening of the wafer in the heat treatment step and a semiconductor device in which the worsening of the property caused by the surface roughening is suppressed. The method of producing a MOSFET as a semiconductor device is provided with a step of preparing a wafer 3 made of silicon carbide and an activation annealing step that performs activation annealing by heating the wafer 3. In the activation annealing step, the wafer 3 is heated in an atmosphere containing a vapor of silicon carbide generated from the SiC piece 61, which is a generating source other than the wafer 3.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: April 15, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kazuhiro Fujikawa, Shin Harada, Yasuo Namikawa, Takeyoshi Masuda
  • Patent number: 8691676
    Abstract: To provide a temperature control method capable of equivalently maintaining qualities of substrates even when treated substrates are continuously carried in a treatment container in the case in which activation annealing treatment is performed by an electron impact heating method.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: April 8, 2014
    Assignee: Canon Anelva Corporation
    Inventors: Masami Shibagaki, Kaori Mashimo
  • Patent number: 8679959
    Abstract: The present invention relates generally to methods for high throughput and controllable creation of high performance semiconductor substrates for use in devices such as high sensitivity photodetectors, imaging arrays, high efficiency solar cells and the like, to semiconductor substrates prepared according to the methods, and to an apparatus for performing the methods of the invention.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: March 25, 2014
    Assignee: Sionyx, Inc.
    Inventors: James E. Carey, Xia Li, Nathaniel J. McCaffrey
  • Patent number: 8669169
    Abstract: Methods for selectively diffusing dopants into a substrate wafer are provided. A liquid precursor is doped with dopants. The liquid precursor is selected from a group comprising monomers, polymers, and oligomers of silicon and hydrogen. The doped liquid precursor is deposited on a surface of the substrate wafer to create a doped film. The doped film is heated on the substrate wafer for diffusing the dopants from the doped film into the substrate wafer at different diffusion rates to create a heavily diffused region and a lightly diffused region in the substrate wafer. The method disclosed herein further comprises selective curing of the doped film on the surface of the substrate wafer. The selectively cured doped film acts as a diffusion source for selectively diffusing the dopants into the substrate wafer.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: March 11, 2014
    Assignee: Piquant Research LLC
    Inventor: Daniel Inns
  • Patent number: 8669562
    Abstract: A semiconductor device according to an embodiment includes a silicon carbide, a metal silicide formed on the silicon carbide and including a first layer and a second layer having a carbon ratio lower than that of the first layer, and a metallic electrode formed on the metal silicide, wherein the second layer is formed on the first layer, and the second layer is in contact with the metallic electrode, and an average grain diameter of a metal silicide in the second layer is larger than an average grain diameter of a metal silicide in the first layer.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: March 11, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshinori Tsuchiya, Takashi Shinohe
  • Patent number: 8664099
    Abstract: The present invention discloses a MEMS device with particles blocking function, and a method for making the MEMS device. The MEMS device comprises: a substrate on which is formed a MEMS device region; and a particles blocking layer deposited on the substrate.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: March 4, 2014
    Assignee: PixArt Imaging Incorporation, R.O.C.
    Inventors: Chuan Wei Wang, Sheng Ta Lee
  • Patent number: 8623748
    Abstract: A method for reducing the effective thickness of a gate oxide using nitrogen implantation and anneal subsequent to dopant implantation and activation is provided. More particularly, the present invention provides a method for fabricating semiconductor devices, for example, transistors, which include a hardened gate oxide and which may be characterized by a relatively large nitrogen concentration at the polysilicon/gate oxide interface and a relatively small nitrogen concentration within the gate oxide and at the gate oxide/substrate interface. Additionally, the present invention provides a method for fabricating a semiconductor device having a metal gate strap (e.g., a metal silicide layer) disposed over the polysilicon layer thereof, which device includes a hardened gate oxide and which may be characterized by a relatively large nitrogen concentration at the silicide/polysilicon interface to substantially prevent cross-diffusion.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: January 7, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Zhongze Wang
  • Patent number: 8609521
    Abstract: A silicon carbide substrate having a surface is prepared. An impurity region is formed by implanting ions from the surface into the silicon carbide substrate. Annealing for activating the impurity region is performed. The annealing includes the step of applying first laser light having a first wavelength to the surface of the silicon carbide substrate, and the step of applying second laser light having a second wavelength to the surface of the silicon carbide substrate. The silicon carbide substrate has first and second extinction coefficients at the first and second wavelengths, respectively. A ratio of the first extinction coefficient to the first wavelength is higher than 5×105/m. A ratio of the second extinction coefficient to the second wavelength is lower than 5×105/m. Consequently, damage to the surface of the silicon carbide substrate during laser annealing can be reduced.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: December 17, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Ryosuke Kubota, Keiji Wada, Takeyoshi Masuda, Hiromu Shiomi
  • Patent number: 8603901
    Abstract: A method including a phosphorous ion introduction step for implanting phosphorous ions from a side of a surface Si layer into an SOI substrate in which the surface Si layer and an embedded oxide layer having a predetermined thickness are formed on an Si base material layer to convert the embedded oxide layer into a PSG layer to lower a softening point. An SiC forming step is performed by heating the SOI substrate having the PSG layer formed therein in an atmosphere of hydrocarbon-based gas to convert the surface Si layer into SiC. Thereafter, the resulting substrate is cooled to form a single crystal SiC layer on a surface thereof.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: December 10, 2013
    Assignees: Air Water Inc., Osaka Prefecture University Public Corporation
    Inventors: Katsutoshi Izumi, Takashi Yokoyama
  • Patent number: 8559478
    Abstract: Photonic integrated circuits on silicon are disclosed. By bonding a wafer of compound semiconductor material as an active region to silicon and removing the substrate, the lasers, amplifiers, modulators, and other devices can be processed using standard photolithographic techniques on the silicon substrate. A silicon laser intermixed integrated device in accordance with one or more embodiments of the present invention comprises a silicon-on-insulator substrate, comprising at least one waveguide in a top surface, and a compound semiconductor substrate comprising a gain layer, the compound semiconductor substrate being subjected to a quantum well intermixing process, wherein the upper surface of the compound semiconductor substrate is bonded to the top surface of the silicon-on-insulator substrate.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: October 15, 2013
    Assignee: The Regents of the University of California
    Inventors: Matthew N. Sysak, John E. Bowers, Alexander W. Fang, Hyundai Park
  • Patent number: 8559799
    Abstract: Two-step photo-irradiation heat treatment is performed so that a total photo-irradiation time is not more than one second and that a first step of photo-irradiation of a semiconductor wafer is performed with a light-emission output that averages out at a first light-emission output and a second step of photo-irradiation of the semiconductor wafer is performed in accordance with an output waveform that peaks at a second light-emission output that is higher than both average and maximum light-emission outputs in the first step. Performing preliminary photo-irradiation with a relatively low light-emission output in the first step and then performing intense photo-irradiation with a higher peak in the second step enables the surface temperature of a semiconductor wafer to increase further with a smaller amount of energy than in conventional cases, while preventing the semiconductor wafer from shattering.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: October 15, 2013
    Assignee: Dainippon Screen Mfg. Co., Ltd.
    Inventors: Hideo Nishihara, Shinichi Kato
  • Patent number: 8536032
    Abstract: An extremely-thin silicon-on-insulator transistor includes a buried oxide layer above a substrate. The buried oxide layer, for example, has a thickness that is less than 50 nm. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer includes at least a gate dielectric formed on the silicon layer and a gate conductor formed on the gate dielectric. A gate spacer has a first part on the silicon layer and a second part adjacent to the gate stack. A first raised source/drain region and a second raised source/drain region each have a first part that includes a portion of the silicon layer and a second part adjacent to the gate spacer. At least one embedded stressor is formed at least partially within the substrate that imparts a predetermined stress on a silicon channel region formed within the silicon layer.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: September 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Pranita Kulkarni, Ghavam G. Shahidi
  • Patent number: 8524585
    Abstract: A method of manufacturing a MOSFET includes the steps of preparing a substrate with an epitaxial growth layer made of silicon carbide, performing ion implantation into the substrate with the epitaxial growth layer, forming a protective film made of silicon dioxide on the substrate with the epitaxial growth layer into which the ion implantation was performed, and heating the substrate with the epitaxial growth layer on which the protective film was formed to a temperature range of 1600° C. or more in an atmosphere containing gas including an oxygen atom.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: September 3, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Takeyoshi Masuda
  • Patent number: 8492250
    Abstract: A method for forming a polysilicon layer includes forming an amorphous silicon layer over a substrate, performing a first thermal treatment of the amorphous silicon layer by performing an implantation with a gas that includes silicon (Si), and performing a second thermal treatment on the thermally treated layer at a temperature higher than a temperature of the first thermal treatment.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: July 23, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Eun-Jung Ko
  • Patent number: 8476153
    Abstract: A method of manufacturing a semiconductor device that includes a semiconductor substrate is provided. The method includes: exposing a photoresist coated on the semiconductor substrate using a photomask including a plurality of regions having different light transmittances; developing the photoresist to form a resist pattern including a plurality of regions having different thicknesses that depend on an exposure amount of the photoresist; and implanting impurity ions into the semiconductor substrate through the plurality of regions of the resist pattern having different thicknesses to form a plurality of impurity regions whose depths from a surface of the semiconductor substrate to peak positions are different from each other. The depths to the peak positions depend on the thickness of the resist pattern through which the implanted impurity ions pass.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: July 2, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tomoyuki Tezuka, Mahito Shinohara, Yasuhiro Kawabata
  • Patent number: 8470699
    Abstract: Disclosed is a method of manufacturing a silicon carbide semiconductor apparatus which provides a smooth silicon carbide surface while maintaining a high impurity activation ratio. The method of manufacturing a silicon carbide semiconductor apparatus which forms an impurity region in the surface layer of a silicon carbide substrate includes the steps of implanting an impurity into the surface layer of the silicon carbide substrate, forming a carbon film on the surface of the silicon carbide substrate, preliminarily heating the silicon carbide substrate with the carbon film as a protective film, and thermally activating the silicon carbide substrate with the carbon film as a protective film.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: June 25, 2013
    Assignee: Showa Denko K.K.
    Inventor: Kenji Suzuki
  • Patent number: 8455322
    Abstract: Disclosed is an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: June 4, 2013
    Assignee: International Business Machines Corporation
    Inventors: Oleg Gluschenkov, Rajendran Krishnasamy, Kathryn T. Schonenberg
  • Publication number: 20130075748
    Abstract: A method of forming a doped region in a III-nitride substrate includes providing the III-nitride substrate and forming a masking layer having a predetermined pattern and coupled to a portion of the III-nitride substrate. The III-nitride substrate is characterized by a first conductivity type and the predetermined pattern defines exposed regions of the III-nitride substrate. The method also includes heating the III-nitride substrate to a predetermined temperature and placing a dual-precursor gas adjacent the exposed regions of the III-nitride substrate. The dual-precursor gas includes a nitrogen source and a dopant source. The method further includes maintaining the predetermined temperature for a predetermined time period, forming p-type III-nitride regions adjacent the exposed regions of the III-nitride substrate, and removing the masking layer.
    Type: Application
    Filed: September 22, 2011
    Publication date: March 28, 2013
    Applicant: EPOWERSOFT, INC.
    Inventors: David P. Bour, Richard J. Brown, Isik C. Kizilyalli, Thomas R. Prunty, Linda Romano, Andrew P. Edwards, Hui Nie, Mahdan Raj
  • Publication number: 20130065382
    Abstract: A method of manufacturing a silicon carbide semiconductor device of an embodiment includes: implanting ions in a silicon carbide substrate; performing first heating processing of the silicon carbide substrate in which the ions are implanted; and performing second heating processing of the silicon carbide substrate for which the first heating processing is performed, at a temperature lower than the first heating processing.
    Type: Application
    Filed: February 28, 2012
    Publication date: March 14, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Johji Nishio, Masaru Furukawa, Hiroshi Kono, Takashi Shinohe
  • Publication number: 20130062624
    Abstract: A semiconductor device according to an embodiment includes a silicon carbide, a metal silicide formed on the silicon carbide and including a first layer and a second layer having a carbon ratio lower than that of the first layer, and a metallic electrode formed on the metal silicide, wherein the second layer is formed on the first layer, and the second layer is in contact with the metallic electrode, and an average grain diameter of a metal silicide in the second layer is larger than an average grain diameter of a metal silicide in the first layer.
    Type: Application
    Filed: February 24, 2012
    Publication date: March 14, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yoshinori TSUCHIYA, Takashi Shinohe
  • Patent number: RE45106
    Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method to manufacture a semiconductor structure includes forming a cavity in a substrate. A portion of the substrate is doped, or a doped material is deposited over a portion of the substrate. At least a portion of the doped substrate or at least a portion of the doped material is converted to a dielectric material to enclose the cavity. The forming of the cavity may occur before or after the doping of the substrate or the depositing of the doped material. Other embodiments are described and claimed.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: September 2, 2014
    Assignee: Estivation Properties LLC
    Inventor: Bishnu Prasanna Gogoi