Abstract: Using a beam current of an ion beam, a dose amount to a substrate, and a reference scan speed, a scan number of the substrate is calculated as an integer value in which digits after a decimal point are truncated. If the scan number is smaller than 2, the process is aborted. If the scan number is equal to or larger than 2, it is determined whether the scan number is even or odd. If the scan number is even, the current scan number is set as a practical scan number. If the scan number is odd, an even scan number which is smaller by 1 than the odd scan number is obtained, and the obtained even scan number is set as a practical scan number. A practical scan speed of the substrate is calculated by using the practical scan number, the beam current, and the dose amount.

Abstract: A silicon wafer which achieves a gettering effect without occurrence of slip dislocations is provided, and the silicon wafer is subject to heat treatment after slicing from a silicon monocrystal ingot so that a layer which has zero light scattering defects according to the 90° light scattering method is formed in a region at a depth from the wafer surface of 25 ?m or more but less than 100 ?m, and a layer which has a light scattering defect density of 1×108/cm3 or more according to the 90° light scattering method is formed in a region at a depth of 100 ?m from the wafer surface.

Abstract: Fabrication of a Group III-nitride transistor device can include implanting dopant ions into a stacked Group III-nitride channel layer and Group III-nitride barrier layer to form source/drain regions therein with a channel region therebetween. The channel layer has a lower bandgap energy than the barrier layer along a heterojunction interface between the channel layer and the barrier layer. The source/drain regions have a lower defect centers energy than the channel region. The source/drain regions and the channel region are exposed to a laser beam with a wavelength having a photon energy that is less than the bandgap energy of the channel region and higher than the defect centers energy of the source/drain regions to locally heat the source/drain regions to a temperature that anneals the source/drain regions.

Abstract: A method of manufacturing a silicon carbide semiconductor device is disclosed in which a trench and a hole are controlled to have a predetermined configuration even if the silicon carbide semiconductor device is subjected to a heat treatment at a temperature of not lower than 1,500° C. A heat treatment step(s) of a method of the invention includes a step of heat treatment in an argon atmosphere at a temperature in a range of 1,600° C. to 1,800° C. under a pressure of at most 10 Torr for a time duration in a range of 0.1 min to 10 min to evaporate silicon atoms from a surface of the silicon carbide semiconductor substrate or the silicon carbide epitaxial layer and to obtain a silicon carbide surface with a carbon atom concentration of at least 95%.

Abstract: A method of manufacturing a vertical power MOS transistor on a wide band gap semiconductor substrate having a wide band gap superficial semiconductor layer, including the steps of forming a screening structure on the superficial semiconductor layer that leaves a plurality of areas of the superficial semiconductor layer exposed, carrying out at least a first ion implantation of a first type of dopant in the superficial semiconductor layer for forming at least one deep implanted region, carrying out at least a second ion implantation of the first type of dopant in the superficial semiconductor layer for forming at least one implanted body region of the MOS transistor aligned with the deep implanted region, carrying out at least one ion implantation of a second type of dopant in the superficial semiconductor layer for forming at least an implanted source region of the MOS transistor inside the at least one implanted body region, and a low budget activation thermal process of the first and second dopant types sui

Abstract: A compound semiconductor is placed in a reaction vessel (12) of which the inner gas is subjected to replacement with a low-vapor-pressure gas (2) whose equilibrium vapor pressure at the melting point of the compound semiconductor is 1 atm or lower. The low-vapor-pressure gas is urged to flow along the surface of the compound semiconductor while keeping the internal pressure of the reaction vessel at a value not lower than that equilibrium vapor pressure. The surface of the compound semiconductor is irradiated with a pulsed-laser light (3) whose photon energy is higher than the band gap of the compound semiconductor. Thus, only that part of the compound semiconductor which is located at the pulsed-laser light irradiation position is instantly heated and melted while keeping the atmospheric temperature of the low-vapor-pressure gas at a room temperature or a temperature equal to or lower than the decomposition temperature.

Abstract: Methods of forming a p-channel MOS device in silicon carbide include forming an n-type well in a silicon carbide layer, and implanting p-type dopant ions to form a p-type region in the n-type well at a surface of the silicon carbide layer and at least partially defining a channel region in the n-type well adjacent the p-type region. A threshold adjustment region is formed in the channel region. The implanted ions are annealed in an inert atmosphere at a temperature greater than 1650° C. A gate oxide layer is formed on the channel region, and a gate is formed on the gate oxide layer. A silicon carbide-based transistor includes a silicon carbide layer, an n-type well in the silicon carbide layer, and a p-type region in the n-type well at a surface of the silicon carbide layer and at least partially defining a channel region in the n-type well adjacent the p-type region.

Abstract: A memory function body has a medium interposed between a first conductor (e.g., a conductive substrate) and a second conductor (e.g., an electrode) and consisting of a first material (e.g., silicon oxide or silicon nitride). The medium contains particles. Each particle is covered with a second material (e.g., silver oxide) and formed of a third material (e.g., silver). The second material functions as a barrier against passage of electric charges, and the third material has a function of retaining electric charges. The third material is introduced into the medium by, for example, a negative ion implantation method.

Abstract: A method is disclosed for forming a high electron mobility transistor. The method includes the steps of implanting a Group III nitride layer at a defined position with ions that when implanted produce an improved ohmic contact between the layer and contact metals, with the implantation being carried out at a temperature higher than room temperature and hot enough to reduce the amount of damage done to the Group III nitride layer, but below a temperature at which surface problems causing leakage at the gate or epitaxial layer dissociation would occur. An ohmic contact selected from the group consisting of titanium, aluminum, nickel and alloys thereof is added to the implanted defined position on the Group III nitride layer.

Abstract: A method of manufacturing an SiC semiconductor device includes the steps of ion implanting a dopant at least in a part of a surface of an SiC single crystal, forming an Si film on the surface of the ion-implanted SiC single crystal, and heating the SiC single crystal on which the Si film is formed to a temperature not less than a melting temperature of the Si film.

Abstract: A method for manufacturing a semiconductor device includes: forming a groove in a semiconductor substrate and embedding an element isolation film made of a silicon oxide film in the groove; forming a silicon nitride film on the element isolation film; forming an oxidized silicon nitride film on the surface of the element isolation film through thermal treatment of the element isolation film and the silicon nitride film; and removing the silicon nitride film.

Abstract: The present invention provides a method of manufacturing a bonded wafer. The method includes forming an oxygen ion implantation layer in an active layer wafer having a substrate resistivity of 1 to 100 m?cm by implanting oxygen ions in the active layer wafer, bonding a base wafer and the active layer wafer directly or through an insulating layer to form a bonded wafer, heat treating the bonded wafer to strengthen the bond and convert the oxygen ion implantation layer into a stop layer, grinding, polishing, and/or etching, from the active layer wafer surface side, the bonded wafer in which the bond has been strengthened to expose the stop layer on a surface of the bonded wafer, removing the stop layer, and subjecting the bonded wafer from which the stop layer has been removed to a heat treatment under a reducing atmosphere to diffuse an electrically conductive component comprised in the active layer wafer.

Abstract: A method of manufacturing a silicon carbide semiconductor device includes ion-implanting an impurity in a surface of a silicon carbide wafer, and forming a carbon protection film of a predetermined thickness over all surfaces of the silicon carbide wafer, which has been ion-implanted with the impurity, by a chemical vapor deposition method that deposits a film by pyrolyzing a hydrocarbon gas. The method also includes annealing the silicon carbide wafer after the forming the carbon protection film.

Abstract: A manufacturing method, remanufacturing method and reshipping method for a semiconductor memory device capable of preventing the charge hold characteristic from deteriorating even if information data is repeatedly written and erased. The manufacturing method is for a semiconductor memory device having a plurality of memory cells in an FET structure formed on a semiconductor substrate, wherein each of the plurality of memory cells is to store a unit bit and hold information data. Preparing a plurality of memory cells, bits of the information data are written to the memory cells. After writing the information data bits to the memory cells, the memory cells are allowed to stand at a predetermined ambient temperature for a predetermined time. Thereafter, bits of the information data are written to the memory cells.

Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method to manufacture a semiconductor structure includes forming a cavity in a substrate. A portion of the substrate is doped, or a doped material is deposited over a portion of the substrate. At least a portion of the doped substrate or at least a portion of the doped material is converted to a dielectric material to enclose the cavity. The forming of the cavity may occur before or after the doping of the substrate or the depositing of the doped material. Other embodiments are described and claimed.

Abstract: A method of fabricating a low, dark-current germanium-on-silicon PIN photo detector includes preparing a P-type silicon wafer; implanting the P-type silicon wafer with boron ions; activating the boron ions to form a P+ region on the silicon wafer; forming a boron-doped germanium layer on the P+ silicon surface; depositing an intrinsic germanium layer on the boron-doped germanium layer; cyclic annealing, including a relatively high temperature first anneal step and a relatively low temperature second anneal step; repeating the first and second anneal steps for about twenty cycles, thereby forcing crystal defects to the P+ germanium layer; implanting ions in the surface of germanium layer to form an N+ germanium surface layer and a PIN diode; activating the N+ germanium surface layer by thermal anneal; and completing device according to known techniques to form a low dark-current germanium-on-silicon PIN photodetector.

Abstract: A single crystal SiC substrate is produced with low cost in which a polycrystalline SiC substrate with relatively low cost is used as a base material substrate where the single crystal SiC substrate has less strain, good crystallinity and large size. The method including a P-type ion introduction step for implanting P-type ions from a side of a surface Si layer 3 into an SOI substrate 1 in which the surface Si layer 3 and an embedded oxide layer 4 having a predetermined thickness are foamed on an Si base material layer 2 to convert the embedded oxide layer 4 into a PSG layer 6 to lower a softening point, and an SiC forming step for heating the SOI substrate 1 having the PSG layer 6 formed therein in an atmosphere of hydrocarbon-based gas to convert the surface Si layer 3 into SiC, and thereafter, cooling the resulting substrate to foam a single crystal SiC layer 5 on a surface thereof.

Abstract: A substrate heating apparatus having a heating unit for heating a substrate placed in a process chamber which can be evacuated includes a suscepter which is installed between the heating unit and a substrate, and on which the substrate is mounted, and a heat receiving member which is installed to oppose the suscepter with the substrate being sandwiched between them, and receives heat from the heating unit via the suscepter. A ventilating portion which allows a space formed between the heat receiving member and substrate to communicate with a space in the process chamber is formed.

Abstract: A method for manufacturing a semiconductor device is provided, which includes forming a gate insulating film on a semiconductor substrate, forming a first layer on the gate insulating film, the first layer containing a first p-type impurity and, an amorphous or polycrystalline formed of Si1-xGex (0?x<0.25), subjecting the first layer to a first heat treatment wherein the first layer is heated for 1 msec or less at a temperature higher than 1100° C., forming a second layer on the first layer, the second layer containing a second p-type impurity and formed of amorphous silicon or polycrystalline silicon, the second p-type impurity having a smaller covalent bond radius than that of the first p-type impurity, and subjecting the second layer to a second heat treatment to heat the second layer at a temperature ranging from 800° C. to 1100° C.

Abstract: A 13C diamond is doped by proton induced transmutation. P-type doping is achieved by the 13C(p,??)10B reaction. N-type doping is achieved by the 13C(p,?)14N reaction. The transmutation reaction that occurs is determined by selection of proton beam energy. Stacks of junctions each calculated to be in the order of 10 nm thick have been achieved.

Abstract: On one face of a semiconductor wafer 1 having a first face (principal face) 1a and a second face (rear face) 1b, a protection film 2 is formed. When allowing the semiconductor wafer 1 to be attracted onto an attracting face of an electrostatic chuck 6 which is heated to 400° C. or more, the semiconductor wafer 1 is attracted onto the attracting face via the protection film 2. While heating the semiconductor wafer 1 to 400° C. or more, an ion implantation is performed for the face of the semiconductor wafer 1 on which the protection film 2 is not formed. Thereafter, the protection film 2 is removed from the semiconductor wafer 1.

Abstract: One aspect includes a semiconductor device with self-aligned contacts, integrated circuit and manufacturing method. One embodiment provides gate control structures. Each of the gate control structures is configured to control the conductivity of a channel region within a silicon carbide substrate by field effect. A contact hole is self-aligned to opposing sidewalls of adjacent gate control structures by intermediate spacers.

Abstract: An amorphous layer 101 is formed in a region from a surface of a silicon substrate 100 to a first depth A. At this time, defects 103 are generated near an amorphous-crystal interface 102. By heat treatment, the crystal structure of the amorphous layer 101 is restored in a region from the first depth A to a second depth B that is shallower than the first depth A. The resultant amorphous layer 101 extends from the surface of the silicon substrate 100 to the second depth B. The defects 103 remain at the first depth A. By ion implantation, a pn junction 104 is formed at a third depth C that is shallower than the second depth B.

Abstract: A method and device for thermal conduction is provided. A thermal interface device and method of formation is described that includes advantages such as improved interfacial strength, and improved interfacial contact. Embodiments of thermal conduction structures are shown that provide composite thermal conduction and circulated liquid cooling. Embodiments are further shown that require simple, low numbers of manufacturing steps and reduced thermal interface thickness.

Abstract: A method of producing a silicon carbide semiconductor device, including: step (A) of forming an impurity-doped region by implanting impurity ions 3 into at least a portion of a silicon carbide layer 2 formed on a first principal face of a silicon carbide substrate 1 having first and second principal faces; step (B) of forming capping layers 6 having thermal resistance on at least an upper face 2a of the silicon carbide layer 2 and on at least a second principal face 12a of the silicon carbide substrate 1; and step (C) of performing an activation annealing treatment by heating the silicon carbide layer 2 at a predetermined temperature.

Abstract: Disclosed herein is a method for production of a thin-film semiconductor device which includes, a first step to form a gate electrode on a substrate, a second step to form a gate insulating film of silicon oxynitride on the substrate in such a way as to cover the gate electrode, a third step to form a semiconductor thin film on the gate insulating film, and a fourth step to perform heat treatment in an oxygen-containing oxidizing atmosphere for modification through oxygen binding with oxygen-deficient parts in the silicon oxynitride film constituting the gate insulating film.

Abstract: Exemplary embodiments provide methods for implementing an ultra-high temperature (UHT) anneal on silicon germanium (SiGe) semiconductor materials by co-implanting carbon into the SiGe material prior to the UHT anneal. Specifically, the carbon implantation can be employed to increase the melting point of the SiGe material such that an ultra high temperature can be used for the subsequent anneal process. Wafer warpage can then be reduced during the UHT anneal process and potential lithographic mis-alignment for subsequent processes can be reduced. Exemplary embodiments further provide an inline control method, wherein the wafer warpage can be measured to determine the litho-mis-alignment and thus to control the fabrication process. In various embodiments, the disclosed methods can be employed for the fabrication of source/drain extension regions and/or source/drain regions of transistor devices, and/or for the fabrication of base regions of bipolar transistors.

Abstract: A method for forming a MOS transistor includes providing a substrate having at least a gate structure formed thereon, performing a pre-amorphization (PAI) process to form amorphized regions in the substrate, sequentially performing a co-implantation process, a first ion implantation process, and a first rapid thermal annealing (RTA) process to form lightly doped drains (LDDs), forming spacers on sidewalls of the gate structure, and forming a source/drain.

Abstract: On one face of a semiconductor wafer 1 having a first face (principal face) 1a and a second face (rear face) 1b, a protection film 2 is formed. When allowing the semiconductor wafer 1 to be attracted onto an attracting face of an electrostatic chuck 6 which is heated to 400° C. or more, the semiconductor wafer 1 is attracted onto the attracting face via the protection film 2. While heating the semiconductor wafer 1 to 400° C. or more, an ion implantation is performed for the face of the semiconductor wafer 1 on which the protection film 2 is not formed. Thereafter, the protection film 2 is removed from the semiconductor wafer 1.

Abstract: The invention provides a method for forming a deep well region of a power device, including: providing a substrate with a first sacrificial layer thereon; forming a first patterned mask layer on the first sacrificial layer exposing a first open region; performing a first doping process to the first open region to form a first sub-doped region; removing the first patterned mask layer and the first sacrificial layer; forming an epitaxial layer on the substrate; forming a second sacrificial layer on the epitaxial layer; forming a second patterned mask layer on the second sacrificial layer exposing a second open region; performing a second doping process to the second open region to form a second sub-doped region; removing the second patterned mask layer; performing an annealing process to make the first and the second sub-doped regions form a deep well region; and removing the second sacrificial layer.

Abstract: A method of manufacturing an SiC semiconductor device includes the steps of ion implanting a dopant at least in a part of a surface of an SiC single crystal, forming an Si film on the surface of the ion-implanted SiC single crystal, and heating the SiC single crystal on which the Si film is formed to a temperature not less than a melting temperature of the Si film.

Abstract: A semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes a lower wire, an interlayer insulating film formed on the lower wire and having a via hole exposing the upper surface of the lower wire, a diffusion barrier formed on the inner wall of the via hole, and an upper wire filling the via hole and directly contacting the lower wire, in which a dopant region containing a component of the diffusion barrier is formed in the lower wire in the extension direction of the via hole.

Abstract: A method of fabricating a hybrid substrate by direct bonding of donor and receiver substrates where each substrate has a respective front face and surface, with the front face of the receiver substrate having a semiconductor material near the surface, and the donor substrate including a zone of weakness that defines a layer to be transferred. The method includes preparing the substrate surfaces by exposing the surface of the receiver substrate to a temperature from about 900° C. to about 1200° C. in an inert atmosphere for at least 30 sec; directly bonding together the front faces of the prepared substrates to form a composite substrate; heat treating the composite substrate to increase bonding strength between the front surfaces of the donor and receiver substrates; and transferring the layer from the donor substrate by detaching the remainder of the donor substrate at the zone of weakness.

Abstract: A method for manufacturing a SiC semiconductor device includes: forming an impurity layer in a SiC layer; and forming an oxide film on the SiC layer. The forming the impurity layer includes: implanting an impurity ion in the SiC layer; forming a carbon layer on the SiC layer; heating the SiC layer for activating the implanted impurity in the SiC layer covered with the carbon layer; and removing the carbon layer from the SiC layer. The forming the carbon layer includes: coating a resist on the SiC layer; and heating the resist for evaporating organic matter in the resist so that the resist is carbonized. The forming the oxide film is performed after the removing the carbon layer.

Abstract: For manufacture of a semiconductor device using a low heat resistant substrate such as a glass substrate, a method of heat treatment for activating an impurity element that is used to dope a semiconductor film and for performing gettering on the semiconductor film in a short period of time without deforming the substrate, is provided. Also provided is a heat treatment apparatus for carrying out the above heat treatment. The heat treatment method of the present invention involves irradiating an object with light emitted from a lamp light source, and is characterized in that the lamp light source emits light for 0.1 to 20 seconds at a time and that light from the lamp light source irradiates the object several times. The method is also characterized in that the irradiated region is subjected to pulsating light from the lamp light source such that the irradiated region holds the temperature to its highest for 0.5 to 5 seconds.

Abstract: A method of producing a silicon carbide semiconductor device, including: step (A) of forming an impurity-doped region by implanting impurity ions 3 into at least a portion of a silicon carbide layer 2 formed on a first principal face of a silicon carbide substrate 1 having first and second principal faces; step (B) of forming capping layers 6 having thermal resistance on at least an upper face 2a of the silicon carbide layer 2 and on at least a second principal face 12a of the silicon carbide substrate 1; and step (C) of performing an activation annealing treatment by heating the silicon carbide layer 2 at a predetermined temperature.

Abstract: In this invention, a wafer is placed and kept in the low-temperature region at the bottom of a temperature space that is in a state of radiation equilibrium and that is formed inside chamber by a heating unit. The substrate temperature is gradually raised to a temperature ranging from 750° C. to 800° C. Next, the wafer is placed and kept in the high-temperature region in the temperature space and the substrate temperature is raised to the thermal processing temperature. Then thermal processing is performed for a specified period of time. By doing this, it is possible to perform uniform thermal processing without depending on the state of the wafer (ratio of an area covered by silicon nitride film or polysilicon film).

Abstract: A compound semiconductor is placed in a reaction vessel (12) of which the inner gas is subjected to replacement with a low-vapor-pressure gas (2) whose equilibrium vapor pressure at the melting point of the compound semiconductor is 1 atm or lower. The low-vapor-pressure gas is urged to flow along the surface of the compound semiconductor while keeping the internal pressure of the reaction vessel at a value not lower than that equilibrium vapor pressure. The surface of the compound semiconductor is irradiated with a pulsed-laser light (3) whose photon energy is higher than the band gap of the compound semiconductor. Thus, only that part of the compound semiconductor which is located at the pulsed-laser light irradiation position is instantly heated and melted while keeping the atmospheric temperature of the low-vapor-pressure gas at a room temperature or a temperature equal to or lower than the decomposition temperature.

Abstract: A method of making a silicon carbide MOSFET is disclosed. The method includes providing a semiconductor device structure, wherein the device structure comprises a silicon carbide semiconductor device layer, an ion implanted well region of a first conductivity type formed in the semiconductor device layer, an ion implanted source region of a second conductivity type formed into the ion implanted well region; providing a mask layer over the semiconductor device layer, the mask layer exposing a portion of the ion implanted source region, then etching through the portion of the ion implanted source region to form a dimple; then implanting ions through the dimple to form a high dopant concentration first conductivity type ion implanted contact region, wherein the ion implanted contact region is deeper than the ion implanted well region; then removing the contact region mask layer and annealing implanted ions.

Abstract: A SIMOX wafer is produced by implanting an oxygen ions into a surface of a Si substrate and then conducting a high-temperature annealing, in which an atmosphere in at least an end stage of the high-temperature annealing treatment is an Ar or N2 atmosphere containing an oxygen of more than 3 volume % but not more than 10 volume %.

Abstract: Exemplary embodiments provide methods for implementing an ultra-high temperature (UHT) anneal on silicon germanium (SiGe) semiconductor materials by co-implanting carbon into the SiGe material prior to the UHT anneal. Specifically, the carbon implantation can be employed to increase the melting point of the SiGe material such that an ultra high temperature can be used for the subsequent anneal process. Wafer warpage can then be reduced during the UHT anneal process and potential lithographic mis-alignment for subsequent processes can be reduced. Exemplary embodiments further provide an inline control method, wherein the wafer warpage can be measured to determine the litho-mis-alignment and thus to control the fabrication process. In various embodiments, the disclosed methods can be employed for the fabrication of source/drain extension regions and/or source/drain regions of transistor devices, and/or for the fabrication of base regions of bipolar transistors.

Abstract: A method for controlling dislocation position in a silicon germanium buffer layer located on a substrate includes irradiating one or more regions of the silicon germanium layer with a dislocation inducing agent and depositing a strained silicon germanium layer on the substrate. The dislocation inducing agent may include ions, electrons, or other radiation source. Dislocations in the silicon germanium layer are located in one or more of the regions. The substrate and strained silicon germanium layer may then be subjected to an annealing process to transform the strained silicon germanium layer into a relaxed state. A top layer of strained silicon or silicon germanium may be deposited on the relaxed silicon germanium layer. Semiconductor-based devices may then be fabricated in the non-damaged regions of the strained silicon or silicon germanium layer. Threading dislocations are confined to damaged areas which may be transformed into SiO2 isolation regions.

Abstract: In a production process for a semiconductor device employing an SiC semiconductor substrate (1), the SiC semiconductor substrate (1) is mounted on a susceptor (23), and a C heating member (3) of carbon is placed on a surface of the SiC semiconductor substrate (1). An annealing process is performed to form an impurity region in the surface of the SiC semiconductor substrate (1) by causing the susceptor (23) and the C heating member (3) to generate heat at high temperatures.

Abstract: A method of forming crystalline Si:C in source and drain regions is provided. After formation of shallow trench isolation and gate electrodes of field effect transistors, gate spacers are formed on gate electrodes. Preamorphization implantation is performed in the source and drain regions, followed by carbon implantation. The upper portion of the source and drain regions comprises an amorphous mixture of silicon, germanium, and/or carbon. An anti-reflective layer is deposited to enhance the absorption of a laser beam into the silicon substrate. The laser beam is scanned over the silicon substrate including the upper source and drain region with the amorphous mixture. The energy of the laser beam is controlled so that the temperature of the semiconductor substrate is above the melting temperature of the amorphous mixture but below the glass transition temperature of silicon oxide so that structural integrity of the semiconductor structure is preserved.

Abstract: With conventional device, the quantity of complex defects differs with each semiconductor device because the concentration of impurities intrinsically contained differs for each silicon wafer. Consequently, there is an undesirable variation in characteristics among the semiconductor devices. The invention provides a method for manufacturing PIN type diode which comprises an intermediate semiconductor region in which complex defects are formed. The method comprises introducing impurities (for example, carbon), which are the sane kind of impurities intrinsically contained in the intermediate semiconductor region, into the intermediate semiconductor region, and irradiating the intermediate semiconductor region with helium ions to form point defects.

Abstract: A method of manufacturing a silicon carbide semiconductor device includes a step of ion-implanting an impurity in a surface of a silicon carbide wafer (1 and 2); a step of forming a carbon protection film (6) of a predetermined thickness over the entire surface of the silicon carbide wafer (1 and 2) having been ion-implanted with the impurity, by a chemical vapor deposition method that deposits a film by pyrolyzing a hydrocarbon gas; and a step of annealing the silicon carbide wafer (1 and 2) having been formed with the carbon protection film (6). Thereby, the carbon protection film (6) can be formed that contains extremely few contaminants, and prevents step bunching from creating on the surface of the silicon carbide wafer (1 and 2) and crystal defects created therein due to unbalanced thermal stress form increasing.

Abstract: A method of forming a Si strained layer 16 on a Si substrate 10 includes forming a first SiGe buffer layer 12 on the Si substrate 10. Then, the first SiGe buffer layer is implanted with an amorphising implant to render the first SiGe buffer layer amorphous using ion implantation. A second SiGe buffer layer 14 is grown on the first SiGe buffer layer after annealing. This produces a relaxed SiGe layer 12, 14. Then, the strained layer of Si 16 is grown.

Abstract: The present invention relates to a method of fabricating a semiconductor-on-insulator-type heterostructure that includes at least one insulating layer interposed between a receiver substrate of semiconductor material and an active layer derived from a donor substrate of semiconductor material. The method includes the steps of bonding and active layer transfer. Prior to bonding, an atomic species which is identical or isoelectric with the insulating layer material is implanted in the insulating layer. The implantation forms a trapping layer, which can retain gaseous species present in the various interfaces of the heterostructure, thereby limiting formation of defects on the surface of the active layer.

Abstract: A method for manufacturing a SiC semiconductor device includes: forming an impurity layer in a SiC layer; and forming an oxide film on the SiC layer. The forming the impurity layer includes: implanting an impurity in the SiC layer; applying a cap layer on the SiC layer; annealing the cap layer to be transformed a carbon layer; annealing the SiC layer to activate the impurity; and removing the carbon layer. The annealing the SiC layer includes: increasing a temperature of the SiC layer from a second temperature to a first temperature within a first time duration; and decreasing the temperature of the SiC layer from the first temperature to the second temperature within a second time duration. The first temperature is equal to or higher than 1800° C., and the second temperature is lower than 1800° C. The first and second time durations are small.

Abstract: There is provided a method of fabricating semiconductor devices that allows ion implantation to be performed at high temperature with ions accelerated with high energy to help to introduce dopant in a semiconductor substrate, in particular a SiC semiconductor substrate, at a selected region to sufficient depth. To achieve this the method includes the steps of: providing the semiconductor substrate at a surface thereof with a mask layer including a polyimide resin film, or a SiO2 film and a thin metal film; and introducing dopant ions.