Abstract: Methods of optimizing a preheat recipe for rapid thermal processing workpieces are provided. In one aspect, a method of manufacturing is provided that includes preheating a rapid thermal processing chamber according to a preheating recipe and processing a first plurality of workpieces in the rapid thermal processing chamber. Parameter measurements are performed on a first workpiece and a second workpiece of the first plurality of workpieces. The parameter measurements are indicative of processing differences between the first and second workpieces. An output signal is formed corresponding to the parameter measurements and a control signal based on the output signal is used to adjust the preheating recipe for preheating the rapid thermal processing chamber for processing a second plurality of workpieces in the rapid thermal processing chamber to reduce processing differences between first and second workpieces of the second plurality of workpieces.

Abstract: A power MOSFET suitable for use in RF applications and a method for making the same is disclosed. The power MOSFET reduces the gate coverage of the drain region of the device in order to decrease the device gate to drain capacitance Cgd. A significant portion of the gate overlaying the drain region is eliminated by the removal of a portion of a polysilicon layer that is disposed over a substantial portion of the drain region that resides between the channel portions of the body regions of the device. The resulting open area, that is subsequently covered by an oxide layer, separates the polysilicon gate electrodes of the device. Finally, a metal layer is deposited over the entire structure to form the gate and source electrodes of the device.

Abstract: A method for making electrical contacts and junctions in silicon carbide that concurrently incorporates and activates dopants from a gaseous ambient. The low temperature processing of the present invention prevents the formation of crystalline defects during annealing and preserves the quantitative chemical properties of the silicon carbide. Improved activation of dopants incorporated in a silicon carbide sample is provided for making the electrical contacts and junctions.

Abstract: This invention comprises improvements in the ways in which spin-on dielectric layers are cured. A semiconductor wafer is coated with a precursor for a spin-on dielectric material, and after the solution is thinned and evened, the wafer is placed in a curing oven, optionally containing an inert gas, and pre-heated to a temperature below which excessive thermomechanical stresses and/or oxidation are not created in the semiconductor wafer. The temperature within the curing oven is then raised to a curing temperature, and thereafter the temperature is slowly lowered to prevent the formation of stress cracks and the loss of dielectric function of the thin film. The curing method of this invention is useful for the manufacture of semiconductor devices employing a variety of spin-on materials.

Abstract: A method and structure providing a dual layer silicon gate film having a uniform boron distribution therein and an ordered, uniform grain structure. Rapid thermal annealing is used to cause the diffusion of boron from an originally doped film to an originally undoped film, resulting in a uniform boron distribution within the structure, thereby rendering the structure resistant to vertical and lateral diffusion of the boron during subsequent processing at elevated temperatures.

Abstract: Described are preferred processes for conditioning semiconductor devices with deuterium to improve operating characteristics and decrease depassivation which occurs during the course of device operation. Also described are semiconductor devices which can be prepared by such processes.

Abstract: A process for semiconductor device fabrication in which a Czochralski silicon substrate is implanted with boron is disclosed. The boron is implanted using an energy of about 500 keV to about 3 MeV and a dose of about 3.times.10.sup.13 /cm.sup.2 to about 3.times.10.sup.14 /cm.sup.2. In order to reduce the threading dislocation density in the substrate to less than about 10.sup.3 /cm.sup.2 at a depth in the substrate of at least about 0.5 .mu.m, after the implant, the substrate is annealed in a two-step process. First the substrate is annealed at a temperature in the range of about 725.degree. C. to about 775.degree. C. followed by an anneal at a temperature of at least about 900.degree. C. The duration of the first step is selected to provide a dislocation density of less than about 10.sup.3 /cm.sup.2 at the desired depth in the substrate.

Abstract: Disclosed is a manufacturing method of a semiconductor device which comprises which comprises an element isolation region formation step; a side wall formation step; a diffusion layer formation step; an activation step; a silicide formation step; and a removing step. The element isolation region formation step is the one for forming a field oxide film on a semiconductor substrate to form an element isolation region. In order to form a diffusion layer by introducing impurities into the semiconductor substrate, after injecting the fluorides (ion injection species) of elements into the semiconductor substrate, a thermal treatment is performed at a lower temperature than that of a thermal treatment for activating the diffusion layer prior to the activation of the diffusion layer, and fluorine produced from the ion injection species is discharged to the outside.

Abstract: Silicon carbide power devices are fabricated by implanting p-type dopants into a silicon carbide substrate through an opening in a mask, to form a deep p-type implant. N-type dopants are implanted into the silicon carbide substrates through the same opening in the mask, to form a shallow n-type implant relative to the p-type implant. Annealing is then performed at temperature and time that is sufficient to laterally diffuse the deep p-type implant to the surface of the silicon carbide substrate surrounding the shallow n-type implant, without vertically diffusing the p-type implant to the surface of the silicon carbide substrate through the shallow n-type implant. Accordingly, self-aligned shallow and deep implants may be performed by ion implantation, and a well-controlled channel may be formed by the annealing that promotes significant diffusion of the p-type dopant having high diffusivity, while the n-type dopant having low diffusivity remains relatively fixed.

Abstract: Silicon carbide power devices are fabricated by masking the surface of a silicon carbide substrate to define an opening at the substrate, implanting p-type dopants into the silicon carbide substrate through the opening at implant energy and dosage that form a deep p-type implant, and implanting n-type dopants into the silicon carbide substrate through the opening at implant energy and dosage that form a shallow n-type implant relative to the deep p-type implant. The deep p-type implant and the shallow n-type implant are annealed at less than 1650.degree. C., but preferably more than about 1500.degree.. The annealing preferably takes place for between about five minutes and about thirty minutes. Ramp-up time from room temperature to the anneal temperature is also controlled to be less than about one hundred minutes but more than about thirty minutes. Ramp-down time after annealing is also controlled by decreasing the temperature from the annealing temperature to below about 1500.degree. C.

Abstract: A method for manufacturing a silicon carbide semiconductor device having pn junctions is provided wherein a recessed portion is formed in a certain pattern in a surface of a substrate formed of a silicon carbide crystal, and an epitaxial layer having a conductivity type opposite to that of the substrate is grown on the substrate, and the surface of the surface is flattened so that the pn junctions appear on the surface of the substrate.

Abstract: A method for producing a polycrystalline silicon structure and a polycrystalline silicon layer to be produced by the method of first forming a primary silicon structure in an amorphous or polycrystalline form, and doping the structure with a dopant, in particular with oxygen, in a concentration exceeding the solubility limit. In a subsequent heat treatment, dopant precipitations are formed which control grain growth in a secondary structure being produced. Such a contact polycrystalline silicon structure can be used, in particular, as a connection of a monocrystalline silicon region.

Abstract: A method for making a semiconductor device comprises: depositing at least one Group II-VI compound semiconductor layer comprising at least one Group II element selected from the group consisting of zinc, magnesium, manganese, beryllium, cadmium and mercury and at least one Group VI element selected from the group consisting of oxygen, sulfur, selenium and tellurium onto a Group III-V compound semiconductor layer comprising at least one Group III element selected from the group consisting of gallium, aluminum, boron and indium and at least one Group V element selected from the group consisting of nitrogen, phosphorus, arsenic, antimony and bismuth; whereinbefore depositing the Group II-VI compound semiconductor layer, a particle beam composed of at least one Group II element selected from the group consisting of zinc, magnesium, beryllium, cadmium and mercury is radiated onto the Group III-V compound semiconductor layer in a dose of 8.times.10.sup.-4 Torr.multidot.sec or more.

Abstract: In a method of bandgap tuning of a quantum well heterostructure wherein ions are implanted in the heterostructure by ion implantation, the ions are implanted so that different regions are implanted in such a way as to create different concentrations of defects. This provides varying bandgap energies to various areas of the heterostructure during a subsequent thermal treatment, which removes residual defects and initiates intermixing in the quantum well region to result in a structure having a selectively shifted bandgap.

Abstract: A semiconductor structure having a first conductive trace fabricated adjacent to a second conductive trace over an insulating layer. A dielectric material is located over and between the first and second conductive traces. A borderless contact extends through the dielectric material to contact the first conductive trace. An air gap is formed in the dielectric material between the first and second conductive traces, thereby increasing the capacitance between the first and second traces. The air gap has a first portion with a first width adjacent to the borderless contact, and a second portion with a second width away from the borderless contact. The second width is greater than the first width, and the second portion of the air gap is substantially longer than the first portion of the air gap. The first portion of the air gap is offset toward the second trace.

Abstract: A method of fabricating a semiconductor device wherein there is provided a partially fabricated semiconductor device having a Si/SiO.sub.2 interface in which all processing steps involving heating of the device to a temperature above the Si-hydrogen dissociation temperature for a sufficient time to cause at least substantial dissociation of hydrogen from silicon have been completed. The device is immersed in a deuterium ambient for a sufficient time to permit the device structure in the region of the Si/SiO.sub.2 interface to have an excess of deuterium atoms. The device is then heated to a temperature above the dissociation temperature of hydrogen-silicon bonds for a time sufficient to cause substantial dissociation of hydrogen and/or deuterium from Si in the region of the Si/SiO.sub.2 interface while the deuterium remains in the device structure at the Si and SiO.sub.2 interface.

Abstract: A method for fabricating a plurality of shallow-junction metal oxide semiconductor field-effect transistors (MOSFETs) on a selected area of a silicon wafer, in the case in which the MOSFETs are spaced from one another by substantially transparent isolation elements. The method includes the step of flooding the entire selected area with laser radiation that is intended to effect the heating to a desired threshold temperature of only the selected depth of a surface layer of silicon that has been previously amorphized to this selected depth and then doped. This threshold temperature is sufficient to melt amorphized silicon but is insufficient to melt crystalline silicon.

Abstract: A method for providing an epitaxial layer of a first material over a substrate comprising a second material having a lattice constant different from that of the first material. In the method of the present invention, a first layer of the first material is grown on the substrate. A portion of the first layer is treated to render that portion amorphous. The amorphous portion is then annealed at a temperature above the recrystallization point of the amorphous portion, but below the melting point of the crystallized portion of the first layer thereby recrystallizing the amorphous portion of the first layer. The first layer may rendered amorphous by ion implantation. The method may be used to generate GaN layers on sapphire having fewer dislocations than GaN layers generated by conventional deposition techniques.

Abstract: Thin layers of semiconductor material having a high degree of surface uniformity are produced by: implantion of deuterium ions into a body of semiconductor material to form a buried region of high stress, the buried region defining a thin outer region of the body; attaching a stiffening carrier to the thin outer region of the semiconductor body; and heating the body at 350-450 degrees C. to separate the thin outer region. The separated layer is useful in the production of silicon-on-insulator semiconductor devices, and silicon-on-glass devices for liquid crystal display and microwave applications.

Abstract: A pn-diode of SiC has a first emitter layer part doped with first dopants having a low ionization energy and a second part designed as a grid and having portions extending vertically from above and past the junction between the drift layer and the first part and being laterally separated from each other by drift layer regions for forming a pn-junction by the first part and the drift layer adjacent such portions at a vertical distance from a lower end of the grid portions. The different parameters of the device are selected to allow a depletion of the drift layer in the blocking state form a continuous depleted region between the grid portions, to thereby screen off the high electric field at the pn-junction so that it will not be exposed to high electrical fields.

Abstract: A laser annealing process for recovering crystallinity of a deposited semiconductor film such as of silicon which had undergone morphological damage, said process comprising activating the semiconductor by irradiating a pulsed laser beam operating at a wavelength of 400 nm or less and at a pulse width of 50 nsec or less onto the surface of the film, wherein,said deposited film is coated with a transparent film such as a silicon oxide film at a thickness of from 3 to 300 nm, and the laser beam incident to said coating is applied at an energy density E (mJ/cm.sup.2) provided that it satisfies the relation:log.sub.10 N.ltoreq.-0.02(E-350),where N is the number of shots of the pulsed laser beam.

Abstract: An integrated circuit is provided having both NMOS transistors and PMOS transistors. The NMOS transistor junction regions are preferably formed before the PMOS transistor junction regions with pre-defined anneal temperatures applied after select implant steps. Both the NMOS and PMOS transistor junction are graded such that the drain areas include a relatively large LDD implant area and the source junctions do not. Whatever LDD area pre-existing in the source implanted with a higher concentration source/drain or MDD implant. The ensuing integrated circuit is therefore a CMOS circuit having asymmetrical transistor junctions and carefully controlled implant and anneal sequences. The asymmetrical junctions are retained, or at least optimized, by controlling the anneal temperatures such that diffusivity distances of n-type implants are relatively similar to p-type implants. Diffusivity is controlled by regulating the post-implant anneal temperatures of p-type implants lesser than previous n-type implants.

Abstract: Active acceptor concentrations of p-doped II-VI and III-V semiconductor compound layer provided by chemical vapor deposition are increased by photo-assisted annealing.

Abstract: A method of forming a high density cell in electrically erasable and programmable read only memory (EEPROM) is disclosed. The doubling efficiency is achieved through providing two floating gates in a single cell, unlike what is found in prior art. While the polysilicon control gate is formed by conventional means, the floating gates are formed through a novel method of forming additional polysilicon spacers which are then coupled with lightly doped drain (LDD) regions to function as floating gates. Furthermore, the cell is turned on and off through the modulation of the LDD resistance and not through charge saturation methods of prior art. Finally, it is shown that through the use of two floating gates, rather than one, two bits of information can be stored in one cell with the concomitant advantage of doubled efficiency.

Abstract: A method of simultaneously forming a gallium arsenide p-i-n structure having p, i, and n regions, which includes heating to dissolve gallium arsenide in a solvent such as bismuth or gallium to form a saturated solution of gallium arsenide in the solvent, contacting the solution with a gaseous mixture, which mixture includes hydrogen, water vapor and products of reactions between the hydrogen and the water vapor with the solvent and with silicon dioxide, to form a contacted solution, coating a suitably selected substrate, such as a group III-V compound such as gallium arsenide, with the contacted solution, cooling the coated substrate to precipitate gallium arsenide from the contacted solution onto the substrate, and removing the substrate coated with a layer of gallium arsenide having a p-i-n structure which constitutes the product having an i region dopant concentration of less than about 10.sup.12 cm.sup.-3.

Abstract: Several methods have been found to make p-type gallium nitride. P-type gallium nitride has long been sought for electronic devices. N-type gallium nitride is readily available. Discovery of p-type gallium nitride and the methods for making it will enable its use in ultraviolet and blue light-emitting diodes and lasers. pGaN will further enable blue photocathode elements to be made. Molecular beam epitaxy on substrates held at the proper temperatures, assisted by a nitrogen beam of the proper energy produced several types of p-type GaN with hole concentrations of about 5.times.10.sup.11 /cm.sup.3 and hole mobilities of about 500 cm.sup.2 /V-sec, measured at 250.degree. K. P-type GaN can be formed of unintentionally-doped material or can be doped with magnesium by diffusion, ion implantation, or co-evaporation. When applicable, the nitrogen can be substituted with other group III elements such as Al.

Abstract: The present invention relates to a method for producing a semiconductor device having a semiconductor layer of SiC. The method comprises the steps of a) applying a mask on at least a portion of the SiC layer to coat a first portion of the SiC layer leaving a second portion thereof uncoated, b) applying a heat treatment to the SiC layer, and c) supplying dopants to the SiC layer during the heat treatment for diffusion of the dopants into the SiC layer at the second portion thereof for doping the SiC layer. The mask is made of crystalline AIN as the only component or AIN as a major component of a crystalline alloy constituting the material.