Into Grooved Semiconductor Substrate Region Patents (Class 438/524)
  • Patent number: 9978847
    Abstract: An integrated MOS transistor is formed in a substrate. The transistor includes a gate region buried in a trench of the substrate. The gate region is surrounded by a dielectric region covering internal walls of the trench. A source region and drain region are situated in the substrate on opposite sides of the trench. The dielectric region includes an upper dielectric zone situated at least partially between an upper part of the gate region and the source and drain regions. The dielectric region further includes a lower dielectric zone that is less thick than the upper dielectric zone and is situated between a lower part of the gate region and the substrate.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: May 22, 2018
    Assignee: STMicroelectronics (Roussett) SAS
    Inventors: Julien Delalleau, Christian Rivero
  • Patent number: 9722083
    Abstract: An embodiment method of forming a source/drain region for a transistor includes forming a recess in a substrate, epitaxially growing a semiconductor material in the recess, amorphizing the semiconductor material, and doping the semiconductor material to form a source/drain region. In an embodiment, the doping utilizes either phosphorus or boron as the dopant. Also, the amorphizing and the doping may be performed simultaneously. The amorphizing may be performed at least in part by doping with helium.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: August 1, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Sheng-Wen Yu, Ziwei Fang
  • Patent number: 9362363
    Abstract: A power integrated device includes a drift region disposed in a substrate, a source region disposed in the substrate spaced apart from the drift region, a drain region disposed in the drift region, a gate insulation layer and a gate electrode sequentially stacked on the substrate between the source region and the drift region, a trench isolation layer disposed in the drift region adjacent to a side of the drain region, and a deep trench field insulation layer disposed in the drift region adjacent to another side of the drain region, wherein a vertical height of the deep trench field insulation layer is greater than a width of the deep trench field insulation layer.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: June 7, 2016
    Assignee: SK Hynix Inc.
    Inventors: Joo Won Park, Sang Hyun Lee
  • Patent number: 9048095
    Abstract: A method of manufacturing a semiconductor device includes forming a semiconductor diode by forming a drift region, forming a first semiconductor region of a first conductivity type in or on the drift region and electrically coupling the first semiconductor region to a first terminal via a first surface of a semiconductor body, etching a trench into the semiconductor body, and forming a channel region of a second conductivity type in the trench and electrically coupling the channel region to the first terminal via the first surface of the semiconductor body. A first side of the channel region adjoins the first semiconductor region.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: June 2, 2015
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Franz Hirler, Hans Peter Felsl, Hans-Joachim Schulze
  • Patent number: 9041164
    Abstract: In one aspect, a method is disclosed that includes providing a substrate having a topography that comprises a relief and providing an anti-reflective film conformally over the substrate using a molecular layer deposition step. The anti-reflective film may be formed of a compound selected from the group consisting of: (i) an organic compound chemically bound to an inorganic compound, where one of the organic compound and the inorganic compound is bound to the substrate and where the organic compound absorbs light at at least one wavelength selected in the range 150-500 nm, or (ii) a monodisperse organic compound absorbing light at at least one wavelength selected in the range 150-500 nm. The method further includes providing a photoresist layer on the anti-reflective film.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: May 26, 2015
    Assignee: IMEC
    Inventors: Roel Gronheid, Christoph Adelmann, Annelies Delabie, Gustaf Winroth
  • Publication number: 20150137323
    Abstract: A method for fabricating through silicon via (TSV) structure is disclosed. The method includes the steps of: providing a substrate; forming a through-silicon via (TSV) in the substrate; depositing a liner in the TSV; removing the liner in a bottom of the TSV; and filling a first conductive layer in the TSV for forming a TSV structure.
    Type: Application
    Filed: November 15, 2013
    Publication date: May 21, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: ZHIBIAO ZHOU, Shao-Hui Wu, Chi-Fa Ku
  • Publication number: 20150108549
    Abstract: Disclosed is a trench formation technique wherein a first etch process forms an opening through a semiconductor layer into a semiconductor substrate and then a second etch process expands the portion of the opening within the substrate to form a trench. However, prior to the second etch, a doped region is formed in the substrate at the bottom surface of the opening. Then, the second etch is performed such that an undoped region of the substrate at the sidewalls of the opening is etched at a faster etch rate than the doped region, thereby ensuring that the trench has a relatively high aspect ratio. Also disclosed is a bipolar semiconductor device formation method. This method incorporates the trench formation technique so that a trench isolation region formed around a collector pedestal has a high aspect ratio and, thereby so that collector-to-base capacitance Ccb and collector resistance Rc are both minimized.
    Type: Application
    Filed: October 22, 2013
    Publication date: April 23, 2015
    Applicant: International Business Machines Corporation
    Inventors: John J. Benoit, James R. Elliott, Qizhi Liu
  • Publication number: 20150084153
    Abstract: A Schottky device includes a plurality of mesa structures where one or more of the mesa structures includes a doped region having a multi-concentration dopant profile. In accordance with an embodiment, the Schottky device is formed from a semiconductor material of a first conductivity type. Trenches having sidewalk and floors are formed in the semiconductor material to form a plurality of mesa structures. A doped region having a multi-concentration impurity profile is formed in at least one trench, where the impurity materials of the doped region having the multi-concentration impurity profile are of a second conductivity type. A Schottky contact is formed to at least one of the mesa structures having the dope region with the multi-concentration impurity profile.
    Type: Application
    Filed: January 21, 2014
    Publication date: March 26, 2015
    Applicant: Semiconductor Components Industries, LLC
    Inventors: Mohammed Tanvir Quddus, Mihir Mudholkar, Mingjiao Liu, Michael Thomason
  • Publication number: 20150079758
    Abstract: A method of manufacturing a semiconductor device includes forming trenches in a first conductivity type semiconductor layer. An insulating film is then formed to cover the inner surfaces of the trenches. A part of the insulating film which is covering a bottom part of the trenches is removed from at least a portion of the trenches. Dopant ions are implanted into regions of the semiconductor layer that are below the bottom parts of that portion of the trenches from which the portion of the insulating film has been removed.
    Type: Application
    Filed: February 28, 2014
    Publication date: March 19, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Toshifumi NISHIGUCHI
  • Patent number: 8975154
    Abstract: A method for producing at least one deep trench isolation in a semiconductor substrate including silicon and having a front side may include forming at least one cavity in the semiconductor substrate from the front side. The method may include conformally depositing dopant atoms on walls of the cavity, and forming, in the vicinity of the walls of the cavity, a silicon region doped with the dopant atoms. The method may further include filling the cavity with a filler material to form the at least one deep trench isolation.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: March 10, 2015
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Didier Dutartre, Zahra Aitfqirali-Guerry, Yves Campidelli, Denis Pellissier-Tanon
  • Publication number: 20140332844
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device comprises a plurality of trenches each having a trench endpoint with an endpoint sidewall perpendicular to a longitudinal direction of the trench and extends vertically downward from a top surface to a trench bottom surface. The semiconductor power device further includes a trench bottom dopant region disposed below the trench bottom surface and a sidewall dopant region disposed along the endpoint sidewall wherein the sidewall dopant region extends vertically downward along the endpoint sidewall of the trench to reach the trench bottom dopant region and pick-up the trench bottom dopant region to the top surface of the semiconductor substrate.
    Type: Application
    Filed: May 10, 2013
    Publication date: November 13, 2014
    Inventors: Yongping Ding, Lei Zhang, Hong Chang, Jongoh Kim, John Chen
  • Patent number: 8815720
    Abstract: A workpiece is implanted to a first depth to form a first amorphized region. This amorphized region is then etched to the first depth. After etching, the workpiece is implanted to a second depth to form a second amorphized region below a location of the first amorphized region. The second amorphized region is then etched to the second depth. The implant and etch steps may be repeated until structure is formed to the desired depth. The workpiece may be, for example, a compound semiconductor, such as GaN, a magnetic material, silicon, or other materials.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: August 26, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Ludovic Godet, Morgan D. Evans, Chi-Chun Chen
  • Patent number: 8809171
    Abstract: A method includes forming a first and a second gate stack to cover a first and a second middle portion of a first and a second semiconductor fin, respectively, and performing implantations to implant exposed portions of the first and the second semiconductor fins to form a first and a second n-type doped region, respectively. A portion of each of the first and the second middle portions is protected from the implantations. The first n-type doped region and the second n-type doped region have different gate proximities from edges of the first gate stack and the second stack, respectively. The first and the second n-type doped regions are etched using chlorine radicals to form a first and a second recess, respectively. An epitaxy is performed to re-grow a first semiconductor region and a second semiconductor region in the first recess and the second recess, respectively.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: August 19, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeffrey Junhao Xu, Ying Zhang, Ziwei Fang
  • Patent number: 8741714
    Abstract: Methods for preventing line collapse during the fabrication of NAND flash memory and other microelectronic devices that utilize closely spaced device structures with high aspect ratios are described. In some embodiments, one or more mechanical support structures may be provided to prevent the collapse of closely spaced device structures during fabrication. In one example, during fabrication of a NAND flash memory, one or more mechanical support structures may be set in place prior to performing a high aspect ratio word line etch for forming the NAND strings. The one or more mechanical support structures may comprise one or more fin supports that are arranged in a bit line direction. In another example, the one or more mechanical support structures may be developed during the word line etch for forming the NAND strings.
    Type: Grant
    Filed: October 3, 2012
    Date of Patent: June 3, 2014
    Assignee: Sandisk 3D LLC
    Inventor: Donovan Lee
  • Publication number: 20140147985
    Abstract: Methods for fabricating a semiconductor device are provided. In one embodiment, the method includes forming a Sub-Isolation Buried Layer (SIBL) stack over a semiconductor substrate. The SIBL stack includes a polish stop layer and a sacrificial implant block layer. The SIBL stack is patterned to create an opening therein, and the semiconductor substrate is etched through the opening to produce a trench in the semiconductor substrate. Ions are implanted into the semiconductor substrate at a predetermined energy level at which ion penetration through the patterned SIBL stack is substantially prevented to create a SIBL region beneath the trench. After ion implantation, a trench fill material is deposited over the SIBL stack and into the trench. The semiconductor device is polished to remove a portion of the trench fill material along with the sacrificial implant block layer and expose the polish stop layer.
    Type: Application
    Filed: November 29, 2012
    Publication date: May 29, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Jay P John, Scott A Hildreth, James A Kirchgessner
  • Publication number: 20140120677
    Abstract: Disclosed herein are various methods of forming stressed channel regions on 3D semiconductor devices, such as, for example, FinFET semiconductor devices, through use of epitaxially formed materials. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define at least a portion of a fin for the device, and performing an epitaxial deposition process to form an epitaxially formed stress-inducing material in the trenches.
    Type: Application
    Filed: October 30, 2012
    Publication date: May 1, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Daniel T. Pham, Robert J. Miller, Kungsuk Maitra
  • Publication number: 20140117437
    Abstract: A super junction semiconductor device may include one or more doped zones in a cell area. A drift layer is provided between a doped layer of a first conductivity type and the one or more doped zones. The drift layer includes first regions of the first conductivity type and second regions of a second conductivity type, which is the opposite of the first conductivity type. In an edge area that surrounds the cell area, the first regions may include first portions separating the second regions in a first direction and second portions separating the second regions in a second direction orthogonal to the first direction. The first and second portions are arranged such that a longest second region in the edge area is at most half as long as a dimension of the edge area parallel to the longest second region.
    Type: Application
    Filed: October 31, 2012
    Publication date: May 1, 2014
    Inventors: Armin Willmeroth, Franz Hirler, Hans Weber, Markus Schmitt, Thomas Wahls, Rolf Weis
  • Patent number: 8697553
    Abstract: Solar cells in accordance with the present invention have reduced ohmic losses. These cells include photo-receptive regions that are doped less densely than adjacent selective emitter regions. The photo-receptive regions contain multiple four-sided pyramids that decrease the amount of light lost to the solar cell by reflection. The smaller doping density in the photo-receptive regions results in less blue light that is lost by electron-hole recombination. The higher doping density in the selective emitter region allows for better contacts with the metallic grid coupled to the multiple emitter regions. Preferably, the selective emitter and photo-receptive regions are both implanted using a narrow ion beam containing the dopants.
    Type: Grant
    Filed: June 11, 2009
    Date of Patent: April 15, 2014
    Assignee: Intevac, Inc
    Inventors: Babak Adibi, Edward S. Murrer
  • Patent number: 8697556
    Abstract: A semiconductor device is formed having a trench adjacent to a current carrying region of the device. The trench is formed having a depth greater than the depth of a tub region of the device. Increasing the trench depth moves a region of higher field strength from the tub region to a region along the trench. The region along the trench does not have a junction and may withstand the higher field strength.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: April 15, 2014
    Assignee: Estivation Properties LLC
    Inventor: Robert Bruce Davies
  • Patent number: 8691640
    Abstract: One illustrative method disclosed herein includes forming a plurality of trenches in a semiconductor substrate to thereby define an initial fin structure, forming sidewall spacers adjacent the initial fin structure, wherein the spacers cover a first portion of the initial fin structure and expose a second a portion of the initial fin structure, performing a doping process to form N-type doped regions in at least the exposed portion of the initial fin structure, and performing an etching process to remove at least a portion of the doped regions and thereby define a final fin structure that is vertically spaced apart from the substrate.
    Type: Grant
    Filed: January 21, 2013
    Date of Patent: April 8, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Nicholas V. LiCausi, Jeremy A. Wahl
  • Patent number: 8679928
    Abstract: The present invention includes methods for stressing transistor channels of semiconductor device structures. Such methods include the formation of so-called near-surface “nanocavities” adjacent to the source/drain regions, forming extensions of the source/drain regions adjacent to and including the nanocavities, and implanting matter of a type that will expand or contract the volume of the nanocavities, depending respectively upon whether compressive strain is desirable in transistor channels between the nanocavities, as in PMOS field effect transistors, or tensile strain is wanted in transistor channels, as in NMOS field effect transistors, to enhance carrier mobility and transistor speed. Semiconductor device structures and semiconductor devices including these features are also disclosed.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: March 25, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Arup Bhattacharyya, Leonard Forbes, Paul A. Farrar
  • Publication number: 20140077342
    Abstract: Semiconductor devices having a buried layer and methods for forming the same are disclosed. In an exemplary method, a hard mask layer can be provided on a semiconductor substrate. The hard mask layer can have a plurality of through-openings. A plurality of deep trenches can be formed in the semiconductor substrate using the hard mask layer as a mask. A bottom of each of the plurality of deep trenches in the semiconductor substrate can be doped to form a plurality of heavily-doped regions. One or more of the plurality of heavily-doped regions can be connected to form the buried layer in the semiconductor substrate. There is thus no need to use an epitaxial process to form active regions. In addition, lateral isolation structures can be simultaneously formed in the semiconductor substrate.
    Type: Application
    Filed: September 7, 2013
    Publication date: March 20, 2014
    Applicant: Semiconductor Manufacturing International Corp.
    Inventors: JIWEI HE, GANGNING WANG, SHANNON PU, MIKE TANG, AMY FENG
  • Patent number: 8647945
    Abstract: A semiconductor structure is provided that includes a material stack including an epitaxially grown semiconductor layer on a base semiconductor layer, a dielectric layer on the epitaxially grown semiconductor layer, and an upper semiconductor layer present on the dielectric layer. A capacitor is present extending from the upper semiconductor layer through the dielectric layer into contact with the epitaxially grown semiconductor layer. The capacitor includes a node dielectric present on the sidewalls of the trench and an upper electrode filling at least a portion of the trench. A substrate contact is present in a contact trench extending from the upper semiconductor layer through the dielectric layer and the epitaxially semiconductor layer to a doped region of the base semiconductor layer. A substrate contact is also provided that contacts the base semiconductor layer through the sidewall of a trench. Methods for forming the above-described structures are also provided.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: February 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Geng Wang, Roger A. Booth, Jr., Kangguo Cheng, Joseph Ervin, Chengwen Pei, Ravi M. Todi
  • Patent number: 8642427
    Abstract: A semiconductor device including a semiconductor substrate of a first conductivity type and an epitaxial layer of the first conductivity type disposed thereon is disclosed. Pluralities of first and second trenches are alternately arranged in the epitaxial layer. First and second doped regions of the first conductivity type are formed in the epitaxial layer and surrounding each first trench. A third doped region of a second conductivity type is formed in the epitaxial layer and surrounding each second trench. A first dopant in the first doped region has diffusivity larger than that of a second dopant in the second doped region. A method for fabricating a semiconductor device is also disclosed.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: February 4, 2014
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Rudy Octavius Sihombing, Chia-Hao Lee, Tsung-Hsiung Lee, Shang-Hui Tu
  • Publication number: 20130334649
    Abstract: In a semiconductor body, a semiconductor device has an active region with a vertical drift section of a first conduction type and a near-surface lateral well of a second, complementary conduction type. An edge region surrounding this active region comprises a variably laterally doped doping material zone (VLD zone). This VLD zone likewise has the second, complementary conduction type and adjoins the well. The concentration of doping material of the VLD zone decreases to the concentration of doping material of the drift section along the VLD zone towards a semiconductor chip edge. Between the lateral well and the VLD zone, a transitional region is provided which contains at least one zone of complementary doping located at a vertically lower point than the well in the semiconductor body.
    Type: Application
    Filed: August 14, 2013
    Publication date: December 19, 2013
    Applicant: Infineon Technologies Austria AG
    Inventor: Gerhard Schmidt
  • Patent number: 8598023
    Abstract: There is disclosed a substrate processing apparatus including a processing chamber housing a substrate, pipes for supplying gas into the processing chamber, and heaters provided in the middle of the pipes, and heating the gas. In the substrate processing apparatus, the heaters heat the gas to a temperature lower than a temperature at which exhaust gas is generated from the pipes to dry the substrate in the heated gas.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: December 3, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Tomokazu Kawamoto
  • Patent number: 8563381
    Abstract: A power semiconductor device with improved avalanche capability structures is disclosed. By forming at least an avalanche capability enhancement doped regions with opposite conductivity type to epitaxial layer underneath an ohmic contact doped region which surrounds at least bottom of trenched contact filled with metal plug between two adjacent gate trenches, avalanche current is enhanced with the disclosed structures.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: October 22, 2013
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 8557662
    Abstract: A method for fabricating a semiconductor device is provided, the method includes forming a double trench including a first trench and a second trench formed below the first trench and having surfaces covered with insulation layers, and removing portions of the insulation layers to form a side contact exposing one sidewall of the second trench.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: October 15, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang-Oh Lee
  • Patent number: 8501602
    Abstract: Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an oxide. Cavities may be formed in the oxide and filled with a conductive material, such a doped polysilicon. Vertical junctions are formed between the polysilicon and the exposed substrate at the trench edges such that during a thermal cycle, the doped polysilicon will out-diffuse doping elements into the adjacent single crystal silicon advantageously forming a diode extension having desirable properties.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: August 6, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Fernando Gonzalez, Chandra Mouli
  • Publication number: 20130196491
    Abstract: A method of preventing dopant from diffusing into atmosphere in a BiCMOS process is disclosed. The BiCMOS process includes the steps of: depositing a first silicon oxide layer and a silicon nitride layer over surface of a silicon substrate; etching the silicon substrate to form a plurality of shallow trenches therein; depositing a second silicon oxide layer over surface of the silicon substrate and forming silicon oxide sidewalls over inner side faces of each of the plurality of shallow trenches; forming a heavily doped pseudo buried layer under a bottom of one of the plurality of shallow trenches by implanting a dopant with a high concentration; performing an annealing process to promote diffusion of the dopant contained in the pseudo buried layer, wherein the method includes growing, by thermal oxidation, a silicon oxide layer over a bottom of each of the plurality of shallow trenches during the annealing process.
    Type: Application
    Filed: January 30, 2013
    Publication date: August 1, 2013
    Applicant: SHANGHAI HUA HONG NEC ELECTRONICS CO., LTD.
    Inventor: Shanghai Hua Hong Nec Electronics Co., Ltd.
  • Patent number: 8492221
    Abstract: A method for fabricating a power semiconductor device is provided. A substrate with a first conductivity type is prepared. A semiconductor layer with a second conductivity type is formed on the substrate. A hard mask pattern having at least an opening is formed on the semiconductor layer. A first trench etching is performed to form a first recess in the semiconductor layer via the opening. A first ion implantation is performed to vertically implant dopants into the bottom of the first recess via the opening, thereby forming a first doping region. A second trench etching is performed to etch through the first doping region, thereby forming a second recess.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: July 23, 2013
    Assignee: Anpec Electronics Corporation
    Inventors: Yung-Fa Lin, Shou-Yi Hsu, Meng-Wei Wu, Chia-Hao Chang
  • Patent number: 8486782
    Abstract: Flash memory devices and methods for fabricating the same are provided. In accordance with an exemplary embodiment of the invention, a method for fabricating a memory device comprises the steps of fabricating a first gate stack and a second gate stack overlying a substrate. A trench is etched into the substrate between the first gate stack and the second gate stack and a first impurity doped region is formed within the substrate underlying the trench. The trench is filled at least partially with a conductive material.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: July 16, 2013
    Assignee: Spansion LLC
    Inventors: Ning Cheng, Fred Cheung, Ashot Melik-Martirosian, Kyunghoon Min, Michael Brennan, Hiroyuki Kinoshita
  • Publication number: 20130171812
    Abstract: A method of fabricating a plurality of features of a semiconductor device includes providing a dielectric layer over a silicon layer, and etching the dielectric layer and the silicon layer to form a plurality of first apertures in the dielectric layer and the silicon layer, wherein adjacent apertures of the plurality of first apertures are set apart by a first pitch. The method further includes etching a plurality of second apertures in the dielectric layer, each aperture of the plurality of second apertures having a greater width than and centered about a respective aperture of the plurality of first apertures, implanting a plurality of dopants into the silicon layer aligned through the plurality of second apertures in the dielectric layer, wherein doped portions of the silicon layer are set apart by a second pitch less than the first pitch, and removing undoped portions of the silicon layer.
    Type: Application
    Filed: December 30, 2011
    Publication date: July 4, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Tzu-Yen Hsieh
  • Publication number: 20130161741
    Abstract: A semiconductor device according an aspect of the present disclosure may include an isolation layer formed within a substrate and formed to define an active region, a junction formed in the active region, well regions formed under the isolation layer, and a plug embedded within the substrate between the junction and the well regions and formed extend to a greater depth than the well regions.
    Type: Application
    Filed: August 6, 2012
    Publication date: June 27, 2013
    Applicant: SK HYNIX INC.
    Inventor: Wan Cheul SHIN
  • Patent number: 8470657
    Abstract: An ion implantation method for semiconductor sidewalls includes steps of: forming a trench on a substrate, and the trench having a lower reflecting layer and two sidewalls adjacent to a bottom section; performing a plasma doping procedure to sputter conductive ions to the lower reflecting layer and the conductive ions being rebounded from the lower reflecting layer to adhere to the sidewalls to respectively form an adhesion layer thereon; and performing an annealing procedure to diffuse the conductive ions of the adhesion layer into the substrate to form a conductive segment. Thus, without damaging the substrate, the conductive segment having a high conductive ion doping concentration is formed at a predetermined region to satisfy semiconductor design requirements.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: June 25, 2013
    Assignee: Rexchip Electronics Corporation
    Inventor: Chih-Hsin Lo
  • Patent number: 8466017
    Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs) or diodes such as junction barrier Schottky (JBS) diodes or PiN diodes. The devices are made using selective ion implantation using an implantation mask. The devices have implanted sidewalls formed by scattering of normal or near normal incident ions from the implantation mask. Vertical junction field-effect transistors with long channel length are also described. The devices can be made from a wide-bandgap semiconductor material such as silicon carbide (SiC) and can be used in high temperature and high power applications.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: June 18, 2013
    Assignee: Power Integrations, Inc.
    Inventors: David C. Sheridan, Andrew Ritenour
  • Patent number: 8455339
    Abstract: A method for fabricating a semiconductor device, including etching a substrate to form a trench, forming a junction region in the substrate under the trench, etching the bottom of the trench to a certain depth to form a side junction, and forming a bit line coupled to the side junction.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: June 4, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Yun-Hyuck Ji
  • Patent number: 8450194
    Abstract: A method of modifying a shape of a cavity in a substrate. The method includes forming one or more cavities on a surface of the substrate between adjacent relief structures. The method also includes directing ions toward the substrate at a non-normal angle of incidence, wherein the ions strike an upper portion of a cavity sidewall, and wherein the ions do not strike a lower portion of the cavity sidewall. The method further includes etching the one or more cavities wherein the upper portion of a cavity sidewall etches more slowly than the lower portion of the sidewall cavity.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: May 28, 2013
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Andrew Waite, Younki Kim, Stanislav Todorov
  • Patent number: 8420495
    Abstract: This invention disclosed a manufacturing approach of collector and buried layer of a bipolar transistor. One aspect of the invention is that a pseudo buried layer, i.e, collector buried layer, is manufactured by ion implantation and thermal anneal. This pseudo buried layer has a small area, which makes deep trench isolation to divide pseudo buried layer unnecessary in subsequent process. Another aspect is, the doped area, i.e, collector, is formed by ion implantation instead of high cost epitaxy process. This invention simplified the manufacturing process, as a consequence, saved manufacturing cost.
    Type: Grant
    Filed: December 28, 2010
    Date of Patent: April 16, 2013
    Assignee: Shanghai Hua Hong Nec Electronics Company, Limited
    Inventors: Tzuyin Chiu, TungYuan Chu, YungChieh Fan, Wensheng Qian, Fan Chen, Jiong Xu, Haifang Zhang
  • Patent number: 8404546
    Abstract: A semiconductor device system, structure, and method of manufacture of a source/drain to retard dopant out-diffusion from a stressor are disclosed. An illustrative embodiment comprises a semiconductor substrate, device, and method to retard sidewall dopant out-diffusion in source/drain regions. A semiconductor substrate is provided with a gate structure, and a source and drain on opposing sides of the gate structure. Recessed regions are etched in a portion of the source and drain. Doped stressors are embedded into the recessed regions. A barrier dopant is incorporated into a remaining portion of the source and drain.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: March 26, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yen Woon, Chun-Feng Nieh, Ching-Yi Chen, Hsun Chang, Chung-Ru Yang, Li-Te S. Lin
  • Patent number: 8394702
    Abstract: A semiconductor device and fabrication methods are disclosed. The device includes a plurality of gate electrodes formed in trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the substrate and electrically connected to the gate electrodes, wherein the first gate runner surrounds the active region. A second gate runner is connected to the first gate runner and located between the active region and a termination region. A termination structure surrounds the first and second gate runners and the active region. The termination structure includes a conductive material in an insulator-lined trench in the substrate, wherein the termination structure is electrically shorted to a source or body layer of the substrate thereby forming a channel stop for the device.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: March 12, 2013
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Sung-Shan Tai, Sik Lui, Xiaobin Wang
  • Patent number: 8394689
    Abstract: A semiconductor memory device includes a first active region, a second active region, a first element isolating region and a second element isolating region. The first active region is formed in a semiconductor substrate. The second active region is formed in the semiconductor substrate. The first element isolating region electrically separates the first active regions adjacent to each other. The second element isolating region electrically separates the second active regions adjacent to each other. An impurity concentration in a part of the second active region in contact with a side face of the second element isolating region is higher than that in the central part of the second active region, and a impurity concentration in a part of the first active region in contact with a side face of the first element isolating region is equal to that in the first active region.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: March 12, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiko Kato, Mitsuhiro Noguchi
  • Patent number: 8394720
    Abstract: A plasma processing method includes modifying a resist pattern of the substrate; and trimming the modified resist pattern through a plasma etching. The modifying includes: supplying the processing gas for modification from the processing gas supply unit to the inside of the processing chamber while the substrate having a surface on which the resist pattern is formed is mounted on the lower electrode; supplying the high frequency power from the high frequency power supply to generate a plasma of the processing gas for modification; and supplying the negative DC voltage from the DC power supply to the upper electrode.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: March 12, 2013
    Assignee: Tokyo Electron Limited
    Inventor: Jin Fujihara
  • Publication number: 20130034952
    Abstract: A semiconductor device is formed having a trench adjacent to a current carrying region of the device. The trench is formed having a depth greater than the depth of a tub region of the device. Increasing the trench depth moves a region of higher field strength from the tub region to a region along the trench. The region along the trench does not have a junction and may withstand the higher field strength.
    Type: Application
    Filed: June 28, 2012
    Publication date: February 7, 2013
    Inventor: Robert Bruce Davies
  • Publication number: 20130001698
    Abstract: A method of modifying a shape of a cavity in a substrate. The method includes forming one or more cavities on a surface of the substrate between adjacent relief structures. The method also includes directing ions toward the substrate at a non-normal angle of incidence, wherein the ions strike an upper portion of a cavity sidewall, and wherein the ions do not strike a lower portion of the cavity sidewall. The method further includes etching the one or more cavities wherein the upper portion of a cavity sidewall etches more slowly than the lower portion of the sidewall cavity.
    Type: Application
    Filed: July 1, 2011
    Publication date: January 3, 2013
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Andrew Waite, Younki Kim, Stanislav Todorov
  • Publication number: 20120319299
    Abstract: A semiconductor diode has a first semiconductor layer (102) of a first conductivity type and a second semiconductor layer of a second conductivity type having a doping. The second semiconductor layer has a vertical electrical via region (106) which is connected to the first semiconductor layer and in which the doping is modified in such a way that the electrical via region (106) has the first conductivity type. A method for producing such a semiconductor diode is described.
    Type: Application
    Filed: February 10, 2011
    Publication date: December 20, 2012
    Inventors: Tony Albrecht, Markus Maute, Martin Reufer, Heribert Zull
  • Patent number: 8329566
    Abstract: The present invention relates to a method of manufacturing a semiconductor device, wherein the method comprises: providing a substrate; forming a source region, a drain region, a dummy gate structure, and a gate dielectric layer on the substrate, wherein the dummy gate structure is between the source region and the drain region on the substrate, and the gate dielectric layer is between the substrate and the dummy gate structure; annealing the source region and the drain region; removing the dummy gate structure to form an opening; implanting dopants into the substrate from the opening to form a steep retrograded well; annealing to activate the dopants; and forming a metal gate on the gate dielectric layer by deposition.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: December 11, 2012
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Wenwu Wang
  • Patent number: 8318558
    Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes vertical pillars formed by etching a semiconductor substrate and junction regions which are located among the neighboring vertical pillars and spaced apart from one another in a zigzag pattern. As a result, the semiconductor device easily guarantees an electrical passage between the semiconductor substrate and the vertical pillars, such that it substantially prevents the floating phenomenon from being generated, resulting in the prevention of deterioration of the semiconductor device.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: November 27, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung Hwan Lee
  • Publication number: 20120295429
    Abstract: There is disclosed a substrate processing apparatus including a processing chamber housing a substrate, pipes for supplying gas into the processing chamber, and heaters provided in the middle of the pipes, and heating the gas. In the substrate processing apparatus, the heaters heat the gas to a temperature lower than a temperature at which exhaust gas is generated from the pipes to dry the substrate in the heated gas.
    Type: Application
    Filed: July 31, 2012
    Publication date: November 22, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Tomokazu KAWAMOTO
  • Patent number: RE47887
    Abstract: Laser lit flat panel displays are disclosed including edge-lit and direct lit backlights. In certain embodiments, laser assemblies are selected to obtain bandwidth distributions to reduce speckle.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: March 3, 2020
    Assignee: Dolby Laboratories Licensing Corporation
    Inventor: Masayuki Karakawa