Abstract: A first semiconductor region and a second semiconductor region separated by a shallow trench isolation region are formed in a semiconductor substrate. A photoresist is applied and patterned so that the first semiconductor region is exposed, while the second semiconductor region is covered. Depending on the setting of parameters for the location of an edge of the patterned photoresist, the slope of sidewalls of the photoresist, the thickness of the photoresist, and the direction of ion implantation, ions may, or may not, be implanted into the entirety of the surface portion of the first semiconductor region by shading or non-shading of the first semiconductor region. The semiconductor substrate may further comprise a third semiconductor region into which the dopants are implanted irrespective of the shading or non-shading of the first semiconductor region. The selection of shading or non-shading may be changed from substrate to substrate in manufacturing.

Abstract: A method of forming an electronic device including forming a first trench in a workpiece including a substrate, the first trench having side walls and a bottom surface extending for a width between the side walls and forming a charge-storage layer along the side walls and bottom surface of the first trench. The method further includes implanting ions within the substrate underlying the bottom surface of the first trench to form an implant region and annealing the implant region, wherein after annealing, the implant region extends the width of the bottom surface and along a portion of the side walls.

Abstract: A semiconductor device includes unlined and sealed trenches and methods for forming the unlined and sealed trenches. More particularly, a superjunction semiconductor device includes unlined, and sealed trenches. The trench has sidewalls formed of the semiconductor material. The trench is sealed with a sealing material such that the trench is air-tight. First and second regions are separated by the trench. The first region may include a superjunction Schottky diode or MOSFET. In an alternative embodiment, a plurality of regions are separated by a plurality of unlined and sealed trenches.

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor wafer and forming at least one first trench in the wafer having first and second sidewalls and a first orientation on the wafer. The first sidewall of the at least one first trench is implanted with a dopant of a first conductivity at a first implantation direction. The first sidewall of the at least one first trench is implanted with the dopant of the first conductivity at a second implantation direction. The second implantation direction is orthogonal to the first implantation direction. The first and second implantation directions are non-orthogonal to the first sidewall.

Abstract: A method for selectively relieving channel stress for n-channel transistors with recessed, epitaxial SiGe source and drain regions is described. This increases the electron mobility for the n-channel transistors without affecting the strain in p-channel transistors. The SiGe provides lower resistance when a silicide is formed.

Abstract: A boron ion stream may be used to implant ions, such as boron ions, into the sidewalls of an active area, such as an NFET active area. The boron ion stream has both vertical tilt and horizontal rotation components relative to the sidewalls and/or the silicon device, to provide a better line of sight onto the sidewalls. This may allow components of the silicon device to be moved closer together without unduly reducing the effectiveness of boron doping of NFET active area sidewalls, and provides an improved line of sight of a boron ion stream onto the sidewalls of an NFET active area prior to filling the surrounding trench with STI material.

Abstract: An embodiment of an integrated circuit includes a semiconductor layer, a well, first and second source/drain regions, and a guard region. The semiconductor layer has a first conductivity, and the well is disposed in the layer and has a second conductivity. The first source/drain region is formed in the well and has the first conductivity, and the second source/drain region is formed in the layer outside of the well and has the second conductivity. The guard region is disposed in the layer between the well and the second source/drain region and has the second conductivity. The guard region may prevent latch up by inhibiting the triggering of a silicon-controlled rectifier (SCR) having one of the first and second source/drain regions as an anode and the other of the first and second source/drain regions as a cathode.

Abstract: A field effect transistor is formed as follows. Trenches are formed in a semiconductor region of a first conductivity type. A gate electrode recessed in each trench is formed. Using a first mask, a body region of a second conductivity type is formed in the semiconductor region by implanting dopants. Using the first mask, source regions of the first conductivity type are formed in the body region by implanting dopants.

Abstract: A method for using ion implantation to create a precision trench in a mask or semiconductor substrate and to alter the optical properties of a mask or semiconductor substrate. In one embodiment, the method may include providing a semiconductor substrate or a mask, forming a damage layer in semiconductor substrate or the mask via ion implantation; wherein the damage layer is formed to a desired depth of the trench; etching the semiconductor substrate or mask to create the trench to the desired depth. In another embodiment, ion implantation is used to alter the optical properties of a mask.

Abstract: A semiconductor device is manufactured by defining a groove in a semiconductor substrate, where the groove includes an upper portion and a lower portion, among other steps. A sacrificial layer is then formed to selectively fill the lower portion of the groove. Impurity ions are implanted into the semiconductor substrate while the lower portion of the groove is filled with the sacrificial layer. The sacrificial layer is then removed, and a gate is formed on the groove. In the method for manufacturing the semiconductor device, impurities can be doped at a uniform concentration in the channel area of the semiconductor device.

Abstract: A method of fabricating a recess channel transistor is provided. First, a hard mask is formed on a doped-semiconductor layer and a substrate. The doped-semiconductor layer and the substrate are etched to form a trench and define a source/drain in the doped-semiconductor layer. An implantation process is performed with a tilt angle on sidewalls of the trench to form an implant area. A thermal oxidation process is performed to form an oxide layer. The oxide layer comprises a first thickness on the source/drain in the sidewalls of the trench and a second thickness on the other portion in the sidewalls of the trench.

Abstract: A recessed-gate transistor device includes a gate electrode embedded in a gate trench formed in a semiconductor substrate, wherein the gate trench includes a vertical sidewall and a U-shaped bottom. A source region is provided at one side of the gate trench within the semiconductor substrate. A drain region is provided at the other side thereof. An asymmetric gate dielectric layer is formed between the gate electrode and the semiconductor substrate. The asymmetric gate dielectric layer has a first thickness between the gate electrode and the drain region and a second thickness between the gate electrode and the source region, wherein the first thickness is thicker than the second thickness.

Abstract: A method for manufacturing a semiconductor device which minimizes the line width of a pattern and allows a low temperature oxide film and a thinly formed photoresist film to serve as ion blockers when performing an ion implantation process on the semiconductor substrate.

Abstract: A method for forming the passivation layer for silicon-isolation interface between photosensitive regions of an image sensor, the method includes providing a substrate having a plurality of spaced apart photosensitive regions that collect charge in response to incident light; etching trenches in the substrate between the photosensitive regions; forming a plurality of masks over the photosensitive regions so that trenches between the photosensitive regions are not covered by the masks; implanting the image sensor with a first low dose to passivate the trenches; filling the trenches with a dielectric to form isolation between the photosensitive regions; forming a plurality of masks which cover the photosensitive regions but does not cover a surface corner of the isolation trench to permit passivation implantation at the surface corner of the trench isolation; and implanting the image sensor at a second low dose to passivate the surface corner of trenched isolation region.

Abstract: A method for fabricating a MOSFET having an active area and an edge termination area is disclosed. The method includes forming a first plurality of implants at the bottom of trenches located in the active area and in the edge termination area. A second plurality of implants is formed at the bottom of the trenches located in the active area. The second plurality of implants formed at the bottom of the trenches located in the active area causes the implants formed at the bottom of the trenches located in the active area to reach a predetermined concentration. In so doing, the breakdown voltage of both the active and edge termination areas can be made similar and thereby optimized while maintaining advantageous RDson.

Abstract: A non-volatile memory device, and method of forming the same, increases or maximizes the performance of an ultramicro-structured device.

Abstract: A method and system for integrated circuit (IC) processing combines an ion implantation tool and a laser anneal tool in a single unit with a shared precision X-Y scanner. A semiconductor wafer is loaded onto a the X-Y table of the scanner. Data defining the desired ion implantation is used to first customize circuit areas on the semiconductor wafer by gating ON and OFF the ion beam while semiconductor wafer is scanned. Any inadvertent ion beam interruptions are noted by storing the locations of the interruptions. The wafer is then reprocessed to correct faults caused by the interruptions. The laser anneal tool positions the laser beam over the semiconductor wafer it is then scanned while gating the laser beam ON and OFF to custom anneal the wafer devices. Again, any inadvertent laser beam interruptions are detected and the locations of the interruptions are stored for reprocessing to correct faults.

Abstract: A method of manufacturing a semiconductor device of the present invention consists of forming a trench in a trench-type cell transistor region; forming a gate insulating film and a gate material layer on a semiconductor substrate; forming a photoresist layer on the semiconductor substrate so as to expose extension region formation portions of the trench-type cell transistor region and a high breakdown voltage transistor region; forming extension regions in each region by performing ion implantation in the semiconductor substrate surface of the trench-type cell transistor region and the high breakdown voltage transistor region and then patterning gates, and forming extension regions of an ordinary breakdown voltage transistor by covering the trench-type cell transistor region and the high breakdown voltage transistor region with a photoresist layer and implanting ions in the ordinary breakdown voltage transistor region.

Abstract: Several embodiments of flash EEPROM split-channel cell arrays are described that position the channels of cell select transistors along sidewalls of trenches in the substrate, thereby reducing the cell area. Select transistor gates are formed as part of the word lines and extend downward into the trenches with capacitive coupling between the trench sidewall channel portion and the select gate. In one embodiment, trenches are formed between every other floating gate along a row, the two trench sidewalls providing the select transistor channels for adjacent cells, and a common source/drain diffusion is positioned at the bottom of the trench. A third gate provides either erase or steering capabilities. In another embodiment, trenches are formed between every floating gate along a row, a source/drain diffusion extending along the bottom of the trench and upwards along one side with the opposite side of the trench being the select transistor channel for a cell.

Abstract: Post-laser annealing dopant deactivation is minimized by performing certain low temperature process steps prior to laser annealing.

Abstract: A method for fabricating a semiconductor memory device includes forming a channel region in a substrate, selectively etching the substrate to form a first trench, performing an impurity ion implantation process on the channel region, and etching a lower portion of the first trench to form a second trench.

Abstract: A method of forming an isolation structure of a semiconductor device includes implanting dopants of a first type into a semiconductor substrate to form a doped region in the substrate. A mask layer is provided over the substrate and the doped region of the substrate. The mask layer is patterned to expose an isolation region of the substrate, the isolation region defining an active region, the isolation region and the active region being defined at least partly within the doped region. Dopants of a second type are implanted at an edge of the active region as defined by the isolation region. The isolation region of the semiconductor substrate is etched to form an isolation trench having a depth that extends below a depth of the doped region. Dopants of a third type are implanted on sidewalls of the trench in order to minimize the dopants of the second type provided on the sidewalls of the isolation trench from migrating away from the sidewalls.

Abstract: A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semiconductor material. A reachthrough region to the far subcollector is formed by outdiffusing a dopant from a doped material layer deposited in the at least one deep trench that adjoins the far subcollector. The reachthrough region may be formed surrounding the at least one deep trench or only on one side of the at least one deep trench. If the inside of the at least one trench is electrically connected to the reachthrough region, a metal contact may be formed on the doped fill material within the at least one trench. If not, a metal contact is formed on a secondary reachthrough region that contacts the reachthrough region.

Abstract: A recessed-gate thin-film transistor (RG-TFT) with a self-aligned lightly doped drain (LDD) is provided, along with a corresponding fabrication method. The method deposits an insulator overlying a substrate and etches a trench in the insulator. The trench has a bottom and sidewalls. An active silicon (Si) layer is formed overlying the insulator and trench, with a gate oxide layer over the active Si layer. A recessed gate electrode is then formed in the trench. The TFT is doped and LDD regions are formed in the active Si layer overlying the trench sidewalls. The LDD regions have a length that extends from a top of the trench sidewall, to the trench bottom, with a doping density that decreases in response to the LDD length. Alternately stated, the LDD length is directly related to the depth of the trench.

Abstract: A field effect transistor is formed as follows. Trenches are formed in a semiconductor region of a first conductivity type. Each trench is partially filled with one or more materials. A dual-pass angled implant is carried out to implant dopants of a second conductivity type into the semiconductor region through an upper surface of the semiconductor region and through upper trench sidewalls not covered by the one or more material. A high temperature process is carried out to drive the implanted dopants deeper into the mesa region thereby forming body regions of the second conductivity type between adjacent trenches. Source regions of the first conductivity type are then formed in each body region.

Abstract: A partially manufactured semiconductor device includes a semiconductor substrate. The device includes a first oxide layer formed on the substrate, with a mask placed over the oxide-covered substrate, a plurality of first trenches and at least one second trench etched through the oxide layer forming mesas. The at least one second trench is deeper and wider than each of the first trenches. The device includes a second oxide layer that is disposed over an area of mesas and the plurality of first trenches. The device includes a layer of masking material that is deposited over a an area of an edge termination region adjacent to an active region. The area of mesas and first trenches not covered by the masking layer is etched to remove the oxidant seal. The device includes an overhang area that is formed by a wet process etch.

Abstract: A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A photoresist plug is formed in the shallow trench and is recessed below the top of the substrate to expose the top portion of the oxide liner. An angled indium implant through the oxide liner into the substrate is then performed. The plug is removed and an insulator is deposited to fill the trenches. After planarization and wet etch steps, formation of a gate dielectric layer and a patterned gate layer, the NMOS transistor exhibits an improved Vt roll-off of 40 to 45 mVolts for both long and short channels. The improvement is achieved with no degradation in junction or isolation performance. The indium implant dose and angle may be varied to provide flexibility to the process.

Abstract: A CMOS device structure, and a method of fabricating the CMOS device, featuring a gate insulator layer comprised of a high k metal oxide layer, has been developed. The process features formation of recessed, heavily doped source/drain regions, and of vertical, polysilicon LDD spacers, prior to deposition of the high k metal oxide layer. Removal of a silicon nitride shape, previously used as a mask for definition of the recessed regions, which in turn are used for accommodation of the heavily doped source/drain regions, provides the space to be occupied by the high k metal oxide layer. The integrity of the high k, gate insulator layer, butted by the vertical polysilicon spacers, and overlying a channel region provided by the non-recessed portion of the semiconductor substrate, is preserved via delayed deposition of the metal oxide layer, performed after high temperature anneals such as the activation anneal for heavily doped source/drain regions, as well as the anneal used for metal silicide formation.

Abstract: A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a second conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one terraced trench in the epitaxial layer. The terraced trench has a plurality of portions that differ in width to define at least one annular ledge therebetween. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material lining the annular ledge and said trench bottom and into adjacent portions of the epitaxial layer. The dopant is diffused to form at least one annular doped region in the epitaxial layer and at least one other region located below the annular doped region.

Abstract: Substrate isolation trench (224) are formed in a semiconductor substrate (120). Dopant (e.g. boron) is implanted into the trench sidewalls by ion implantation to suppress the current leakage along the sidewalls. During the ion implantation, the transistor gate dielectric (520) faces the ion stream, but damage to the gate dielectric is annealed in subsequent thermal steps. In some embodiments, the dopant implantation is an angled implant. The implant is performed from the opposite sides of the wafer, and thus from the opposite sides of each active area. Each active area includes a region implanted from one side and a region implanted from the opposite side. The two regions overlap to facilitate threshold voltage adjustment.

Abstract: A method forms a semiconductor device comprising a modifiable strain inducing layer. A semiconductor body is provided. First and second regions of the semiconductor body are identified. A modifiable tensile strain inducing layer is formed over the device within the first and second regions. A mask is then formed that exposes the second region and covers the first region. A material is selected for a modification implant and the selected material is implanted into the second region thereby converting a portion of the modifiable tensile strain inducing layer into a compressive strain inducing layer within the PMOS region.

Abstract: A semiconductor device with improved source/drain junctions and methods for fabricating the device are disclosed. A preferred embodiment comprises a MOS transistor with a gate structure overlying a substrate, lightly doped source/drain regions formed in the substrate aligned to the gate structure, sidewall spacers formed on the sidewalls of the gate structure and overlying the lightly doped source/drain regions, deeper source/drain diffusions formed into the substrate aligned to the sidewall spacers and additional pocket implants of source/drain dopants formed at the boundary of the deeper source/drain diffusions and the substrate. In a preferred method, the additional pocket implants are formed using an angled ion implant with the angle being between 4 and 45 degrees from vertical. Additional embodiments include recesses formed in the source/drain regions and methods for forming the recesses.

Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor device. In the method, a field oxide layer can be formed in a semiconductor substrate so as to define and active electrode including a gate oxide layer and a gate poly is formed in the active region. An etch groove is formed between the gate electrode and the field oxide layer. Dopant ions are implanted between the gate electrode and the field oxide layer so as to form a source/drain region.

Abstract: A method of fabricating a high-performance planar back-gate CMOS structure having superior short-channel characteristics and reduced capacitance using processing steps that are not too lengthy or costly is provided. Also provided is a high-performance planar back-gate CMOS structure that is formed utilizing the method of the present invention. The method includes forming an opening in an upper surface of a substrate. Thereafter, a dopant region is formed in the substrate through the opening. In accordance with the inventive method, the dopant region defines a back-gate conductor of the inventive structure. Next, a front gate conductor having at least a portion thereof is formed within the opening.

Abstract: A semiconductor device having a recess gate is formed by first forming a recess below the upper surface of the substrate. A spacer is formed at each sidewall of the recess. An impurity doping area is formed in a source area. A first LDD area is formed in a drain area. A gate comprising a gate insulating layer and a gate conductive layer is then formed in the recess. A second LDD area is formed on the upper surface of the semiconductor substrate. A gate spacer is formed at each sidewall of the gate. Then a source/drain area having an asymmetrical structure is formed on each side of the gate.

Abstract: A method and structure is disclosed for a transistor having a gate, a channel region below the gate, a source region on one side of the channel region, a drain region on an opposite side of the channel region from the source region, a shallow trench isolation (STI) region in the substrate between the drain region and the channel region, and a drain extension below the STI region. The drain extension is positioned along a bottom of the STI region and along a portion of sides of the STI. Portions of the drain extension along the bottom of the STI may comprise different dopant implants than the portions of the drain extensions along the sides of the STI. Portions of the drain extensions along sides of the STI extend from the bottom of the STI to a position partially up the sides of the STI. The STI region is below a portion of the gate. The drain extension provides a conductive path between the drain region and the channel region around a lower perimeter of the STI.

Abstract: A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the semi-conductive layer. At least a portion of the semi-conductive layer is doped by implanting through the conductive layer. The semi-conductive layer and the conductive layer may then be annealed.

Abstract: A CMOS image sensor includes a first conductive type semiconductor substrate having an active region and a device isolation region, a device isolation film formed in the device isolation region of the semiconductor substrate, a second conductive type diffusion region formed in the active region of the semiconductor substrate, and an ion implantation prevention layer formed in the vicinity of the device isolation film, including a boundary portion between the device isolation film and the second conductive type diffusion region.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, on which a semiconductor layer having a trench extending in the depth direction toward the semiconductor substrate is formed. A first region of the first conductivity type is formed in the depth direction along one side of the trench in the semiconductor layer and contacts the semiconductor substrate. A second region of the first conductivity type is formed in a surface area of the semiconductor layer and close to the trench and contacts the first region. A third region of the second conductivity type is formed in the surface area of the semiconductor layer. A fourth region of the first conductivity type is formed in a surface area of the third region. A gate insulation film and a gate electrode are provided on the surface of the third region between the second region and the fourth region.

Abstract: A silicon oxide film (12) and a silicon nitride film (13) are sequentially formed over a silicon substrate (11) having a plane orientation (100). A trench (14) is formed with the patterned silicon nitride (13) as a mask. Argon is ion-implanted from the direction normal to a plane orientation (111) of the interior of the trench (14), followed by formation of an oxide film.

Abstract: A method for forming a mechanically strengthened feature in a low-k dielectric film on a substrate includes using either spin-on-dielectric (SOD) techniques, or chemical vapor deposition (CVD) techniques to form a low-k dielectric film on the substrate. A sidewall of the feature in the low-k dielectric film is then treated in order to increase the film's mechanical strength. Treatment of the sidewall of the feature in the low-k dielectric film comprises forming a hardened layer by subjecting the low-k dielectric film to low energy, high flux ion implantation. Process parameters of the ion implantation are selected such that the implantation process does not cause a substantial change in the dielectric constant of the low-k dielectric film.

Abstract: An electronic component has a semiconductor chip and microscopically small flip-chip contacts belonging to a rewiring plate, on which macroscopically large elastic external contacts are arranged. The rewiring plate has a wiring support made of polycrystalline silicon, amorphous glass, or metal. Furthermore, the present invention relates to a method for the production of a suitable wiring support and of the electronic component.

Abstract: A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate structure and in portions of the semiconductor substrate not occupied by the gate structure or by dummy spacers located on the sides of the conductive gate structure. The selectively defined recesses will be used to subsequently accommodate silicon-germanium shapes, with the silicon-germanium shapes located in the recesses in the semiconductor substrate inducing the desired strained channel region. The recessing of the conductive gate structure and of semiconductor substrate portions reduces the risk of silicon-germanium bridging across the surface of sidewall spacers during epitaxial growth of the alloy layer, thus reducing the risk of gate to substrate leakage or shorts.

Abstract: A plurality of trenches, about 1 ?m long in the Z-direction that crosses the X-direction (source-drain direction), are formed in a semiconductor substrate, arranged in the Z-direction. Ion implantation is performed obliquely with respect to side faces of each trench that cross the X-direction. Then, ion implantation is performed perpendicularly to the bottom face of each trench. Then, oxidation and drive-in are performed, whereby semiconductor portions between adjacent trenches are oxidized and each trench is thereby filled with an oxide to establish a wide trench region as would be obtained by connecting the trenches. At the same time, the impurity ions implanted around the trenches are diffused also in the Z-direction, whereby a uniform offset drain region is formed around the trench so that an optimum concentration and diffusion of the impurity ions is obtained, and an oxide or the like is buried in a wide trench region.

Abstract: A capacitive microsensor formed on a wafer, including a conductive detection area arranged on a first surface or front surface of the wafer; a conductive via crossing the wafer and emerging on said area; and a structure to ensure contact with said via on the second surface or rear surface of the wafer.

Abstract: The present invention provides a method of fabricating a patterned silicon-on-insulator substrate which includes dual depth SOI regions or both SOI and non-SOI regions within the same substrate. The method of the present invention includes forming a silicon mask having at least one opening on a surface of Si-containing material, recessing the Si-containing material through the at least one opening using an etching process to provide a structure having at least one recess region and a non-recessed region, and forming a first buried insulating region in the non-recessed region and a second buried insulating region in the recessed region. In accordance with the present invention, the first buried insulating region in the non-recessed region is located above the second buried isolation region in the recessed region. A lift-off step can be employed to remove the first buried insulating region and the material that lies above to provide a substrate containing both SOI and non-SOI regions.

Abstract: A semiconductor device includes: an n+ type drain region; an n type drift region that connects with the n+ type drain region; a p type body region; a n+ type source region that connects with the p type body region; and a gate electrode that is provided, with being covered by a gate insulation film, in a gate trench that penetrates the p type body region. The semiconductor further includes: a p type silicon region that adjoins the n type drift region; and an n type silicon region provided in a region almost including a carrier passage that connects the n type drift region and the p type body region. Here, the p type silicon region and the p type body region directly connect with each other.

Abstract: Several embodiments of flash EEPROM split-channel cell arrays are described that position the channels of cell select transistors along sidewalls of trenches in the substrate, thereby reducing the cell area. Select transistor gates are formed as part of the word lines and extend downward into the trenches with capacitive coupling between the trench sidewall channel portion and the select gate. In one embodiment, trenches are formed between every other floating gate along a row, the two trench sidewalls providing the select transistor channels for adjacent cells, and a common source/drain diffusion is positioned at the bottom of the trench. A third gate provides either erase or steering capabilities. In another embodiment, trenches are formed between every floating gate along a row, a source/drain diffusion extending along the bottom of the trench and upwards along one side with the opposite side of the trench being the select transistor channel for a cell.

Abstract: A method for fabricating a gate structure of a FET, having: (a) deposition and patterning of a sacrificial layer sequence on a semiconductor substrate and uncovering of a gate section; (b) implantation of a channel doping into the gate section; (c) deposition and patterning of spacers at the sidewalls of the sacrificial layer sequence with the formation of a gate section that is not covered by the spacers; (d) introduction of a mask material into the gate section that is not covered by the spacers; (e) removal of the spacers selectively with respect to the sacrificial layer sequence and mask material); (f) implantation of a halo doping in regions uncovered by the removed spacers; (g) removal of the mask material; (h) formation of a gate on the gate section; and (j) removal of the sacrificial layer sequence selectively with respect to the gate.

Abstract: A semiconducting processing method for making electrical contacts with an active area in sub-micron geometries includes: (a) providing a pair of conductive runners on a semiconductor wafer; (b) providing insulative spacers on the sides of the conductive runners wherein adjacent spacers are spaced a selected distance apart at a selected location on the wafer; (c) providing an active area between the conductive runners at the selected location; (d) providing an oxide layer over the active area and conductive runners; (e) providing a planarized nitride layer atop the oxide layer; (f) patterning and etching the nitride layer selectively relative to the oxide layer to define a first contact opening therethrough, wherein the first contact opening has an aperture width at the nitride layer upper surface which is greater than the selected distance between the insulative spacers; (g) etching the oxide layer within the first contact opening to expose the active area; (h) providing a polysilicon plug within the first co