Into Grooved Semiconductor Substrate Region Patents (Class 438/524)
-
Patent number: 8304314Abstract: In one embodiment, a method of forming an MOS transistor includes forming the MOS transistor to have an active region and a termination region. Within the termination region the method includes forming a plurality of trenches having a conductor within the plurality of trenches. The method also includes forming another conductor to make electrical contact to one of the conductors within the plurality of trenches.Type: GrantFiled: September 24, 2008Date of Patent: November 6, 2012Assignee: Semiconductor Components Industries, LLCInventors: Jeffrey Pearse, Prasad Venkatraman, James Sellers, Hemanshu D. Bhatt
-
Patent number: 8293611Abstract: The present invention includes methods for stressing transistor channels of semiconductor device structures. Such methods include the formation of so-called near-surface “nanocavities” adjacent to the source/drain regions, forming extensions of the source/drain regions adjacent to and including the nanocavities, and implanting matter of a type that will expand or contract the volume of the nanocavities, depending respectively upon whether compressive strain is desirable in transistor channels between the nanocavities, as in PMOS field effect transistors, or tensile strain is wanted in transistor channels, as in NMOS field effect transistors, to enhance carrier mobility and transistor speed. Semiconductor device structures and semiconductor devices including these features are also disclosed.Type: GrantFiled: May 8, 2007Date of Patent: October 23, 2012Assignee: Micron Technology, Inc.Inventors: Arup Bhattacharyya, Leonard Forbes, Paul A Farrar
-
Patent number: 8258032Abstract: A power semiconductor device that realizes high-speed turnoff and soft switching at the same time has an n-type main semiconductor layer that includes lightly doped n-type semiconductor layers and extremely lightly doped n-type semiconductor layers arranged alternately and repeatedly between a p-type channel layer and an n+-type field stop layer, in a direction parallel to the first major surface of the n-type main semiconductor layer. A substrate used for manufacturing the semiconductor device is fabricated by forming trenches in an n-type main semiconductor layer 1 and performing ion implantation and subsequent heat treatment to form an n+-type field stop layer in the bottom of the trenches. The trenches are then filled with a semiconductor doped more lightly than the n-type main semiconductor layer for forming extremely lightly doped n-type semiconductor layers. The manufacturing method is applicable with variations to various power semiconductor devices such as IGBT's, MOSFET's and PIN diodes.Type: GrantFiled: August 11, 2009Date of Patent: September 4, 2012Assignee: Fuji Electric Co., Ltd.Inventor: Koh Yoshikawa
-
Patent number: 8236648Abstract: Provided is a semiconductor device formed with a trench portion for providing a concave portion having a continually varying depth in a gate width direction and with a gate electrode provided within the trench portion and on a top surface thereof via a gate insulating film. Before the formation of the gate electrode, an impurity is added to at least a part of the source region and the drain region by ion implantation from an inner wall of the trench portion, and then heat treatment is performed for diffusion and activation to form a diffusion region from the surface of the trench portion down to a bottom portion thereof. Current flowing through a top surface of the concave portion of the gate electrode at high concentration can flow uniformly through the entire trench portion.Type: GrantFiled: July 23, 2008Date of Patent: August 7, 2012Assignee: Seiko Instruments Inc.Inventor: Masayuki Hashitani
-
Patent number: 8216925Abstract: A semiconductor device is formed having a trench adjacent to a current carrying region of the device. The trench is formed having a depth greater than the depth of a tub region of the device. Increasing the trench depth moves a region of higher field strength from the tub region to a region along the trench. The region along the trench does not have a junction and may withstand the higher field strength.Type: GrantFiled: November 1, 2010Date of Patent: July 10, 2012Assignee: HVVi Semiconductors, Inc.Inventor: Robert Bruce Davies
-
Patent number: 8202790Abstract: A semiconductor device in accordance with one embodiment of the invention can include a semiconductor substrate having a groove, a bit line, a pocket implantation region, a bottom insulating membrane, and a charge accumulation region. The bit line is formed on a side of the groove in the semiconductor substrate and acts as a source and a drain. The pocket implantation region is formed to touch (or contact) the bit line, has a similar conductivity type as the semiconductor substrate, and has a dopant concentration higher than that of the semiconductor substrate. The bottom insulating membrane is formed on and touches (or contacts) a side surface of the groove. The charge accumulation layer is formed on and touches (or contacts) a side surface of the bottom insulating membrane.Type: GrantFiled: February 5, 2008Date of Patent: June 19, 2012Assignee: Spansion LLCInventor: Yukihiro Utsuno
-
Patent number: 8173517Abstract: The present invention relates to methods for forming microelectronic structures in a semiconductor substrate. The method includes selectively removing dielectric material to expose a portion of an oxide overlying a semiconductor substrate. Insulating material may be formed substantially conformably over the oxide and remaining portions of the dielectric material. Spacers may be formed from the insulating material. An isolation trench etch follows the spacer etch. An optional thermal oxidation of the surfaces in the isolation trench may be performed, which may optionally be followed by doping of the bottom of the isolation trench to further isolate neighboring active regions on either side of the isolation trench. A conformal material may be formed substantially conformably over the spacer, over the remaining portions of the dielectric material, and substantially filling the isolation trench. Planarization of the conformal material may follow.Type: GrantFiled: July 1, 2010Date of Patent: May 8, 2012Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, David L. Chapek, Randhir P. S. Thakur
-
Patent number: 8168494Abstract: Trench portions (10) are formed in a well (5) in order to provide unevenness in the well (5). A gate electrode (2) is formed via an insulating film (7) on the upper surface and inside of the trench portions (10). A source region (3) is formed on one side of the gate electrode (2) in a gate length direction while a drain region (4) on another side. Both of the source region (3) and the drain region (4) are formed down to near the bottom portion of the gate electrode (2). By deeply forming the source region (3) and the drain region (4), current uniformly flows through the whole trench portions (10), and the unevenness formed in the well (5) increase the effective gate width to decrease the on-resistance of a semiconductor device 1 and to enhance the drivability thereof.Type: GrantFiled: February 7, 2008Date of Patent: May 1, 2012Assignee: Seiko Instruments Inc.Inventors: Tomomitsu Risaki, Jun Osanai
-
Patent number: 8168501Abstract: A semiconductor device and method of manufacture thereof wherein a PMOS source/drain region of a transistor within the substrate includes a first strained layer in the PMOS source/drain region and a first capping layer in contact with the first strained layer. Further, the semiconductor device and method provide for an NMOS source/drain region of a transistor within the substrate including a second strained layer in the NMOS source/drain region and a second capping layer in contact with the second strained layer.Type: GrantFiled: May 27, 2011Date of Patent: May 1, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Hua Yu, Ling-Yen Yeh, Tze-Liang Lee
-
Publication number: 20120094457Abstract: A method is provided that utilizes the shallow trench isolation (STI) process to incorporate a self-aligned drift implant into the extrinsic drain of a laterally diffused MOS (LDMOS) device. Since the location of the implant edge with respect to the edge of the STI is determined by the shallow trench etch, the edge location is extremely consistent and can significantly reduce the standard deviation of device parameters dependent upon the location of the implant. This, in turn, allows for a more compact device design with optimized performance.Type: ApplicationFiled: October 14, 2010Publication date: April 19, 2012Inventor: Ann Gabrys
-
Publication number: 20120061795Abstract: A device includes a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate comprises a first surface and a second surface opposite the first surface. A through-substrate via (TSV) extends from the first surface to the second surface of the semiconductor substrate. A well region of a second conductivity type opposite the first conductivity type encircles the TSV, and extends from the first surface to the second surface of the semiconductor substrate.Type: ApplicationFiled: September 9, 2010Publication date: March 15, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiao-Tsung Yen, Hsien-Pin Hu, Chin-Wei Kuo, Sally Liu
-
Patent number: 8133781Abstract: A mask layer formed over a semiconductor substrate is lithographically patterned to form an opening therein. Ions are implanted at an angle that is normal to the surface of the semiconductor substrate through the opening and into an upper portion of the semiconductor substrate. Straggle of the implanted ions form a doped region that laterally extends beyond a horizontal cross-sectional area of the opening. A deep trench is formed by performing an anisotropic etch of a semiconductor material underneath the opening to a depth above a deep end of an implanted region. Ion implantation steps and anisotropic etch steps are alternately employed to extend the depth of the doped region and the depth of the deep trench, thereby forming a doped region around a deep trench that has narrow lateral dimensions. The doped region can be employed as a buried plate for a deep trench capacitor.Type: GrantFiled: February 15, 2010Date of Patent: March 13, 2012Assignee: International Business Machines CorporationInventors: Joseph Ervin, Geng Wang
-
Publication number: 20120056247Abstract: The present invention discloses a pseudo buried layer, a deep hole contact and a bipolar transistor, and also discloses a manufacturing method of a pseudo buried layer, including: etching a silicon substrate to form an active region and shallow trenches; sequentially implanting phosphorous ion and arsenic ion into the bottom of the shallow trenches to form phosphorus impurity regions and arsenic impurity regions; conducting thermal annealing to the phosphorus impurity regions and arsenic impurity regions. The implantation of the pseudo buried layer, adopting phosphorous with rapid thermal diffusion and arsenic with slow thermal diffusion, can improve the impurity concentration on the surface of the pseudo buried layers, reduce the sheet resistance of the pseudo buried layer, form a good ohmic contact between the pseudo buried layer and a deep hole and reduce the contact resistance, and improve the frequency characteristic and current output of triode devices.Type: ApplicationFiled: September 7, 2011Publication date: March 8, 2012Inventors: Donghua Liu, Wensheng Qian
-
Patent number: 8124507Abstract: A fin-type semiconductor region (103) is formed on a substrate (101), and then a resist pattern (105) is formed on the substrate (101). An impurity is implanted into the fin-type semiconductor region (103) by a plasma doping process using the resist pattern (105) as a mask, and then at least a side of the fin-type semiconductor region (103) is covered with a protective film (107). Thereafter, the resist pattern (105) is removed by cleaning using a chemical solution, and then the impurity implanted into the fin-type semiconductor region (103) is activated by heat treatment.Type: GrantFiled: March 4, 2010Date of Patent: February 28, 2012Assignee: Panasonic CorporationInventors: Yuichiro Sasaki, Katsumi Okashita, Bunji Mizuno
-
Patent number: 8114743Abstract: An integrated circuit device with a semiconductor body and a method for the production of a semiconductor device a provided. The semiconductor body comprises a cell field with a drift zone of a first conduction type. In addition, the semiconductor device comprises an edge region surrounding the cell field. Field plates with a trench gate structure are arranged in the cell field, and an edge trench surrounding the cell field is provided in the edge region. The front side of the semiconductor body is in the edge region provided with an edge zone of a conduction type complementing the first conduction type with doping materials of body zones of the cell field. The edge zone of the complementary conduction type extends both within and outside the edge trench.Type: GrantFiled: December 7, 2010Date of Patent: February 14, 2012Assignee: Infineon Technologies Austria AGInventors: Uli Hiller, Oliver Blank, Ralf Siemieniec, Maximilian Roesch
-
Patent number: 8084340Abstract: A method of manufacturing a semiconductor device whereby, even in cases where ions are implanted into a shallow region of a semiconductor substrate when a deep well is formed, the influence of the ions on a MOSFET can be removed, thereby eliminating the need for increasing the chip area. A photoresist with a thickness matching the wavelength of exposure light is formed over the semiconductor substrate and then is exposed to the exposure light to form a photoresist pattern with an opening corresponding to a region for forming a first well. Subsequently, using the photoresist pattern as a mask, ions are implanted to form the first well, and after the photoresist pattern is removed, an epitaxial layer is grown over the semiconductor substrate. Consequently, the deep well is virtually located deeper in level than at the time of the ion implantation by an amount corresponding to the thickness of the epitaxial layer.Type: GrantFiled: October 3, 2006Date of Patent: December 27, 2011Assignee: Fujitsu Semiconductor LimitedInventor: Satoshi Nakai
-
Patent number: 8080472Abstract: A metal line having a MoxSiy/Mo diffusion barrier of a semiconductor device and corresponding methods of fabricating the same are presented. The metal line includes an insulation layer, a diffusion barrier, and a metal layer. The insulation layer is formed on a semiconductor substrate and has a metal line forming region. The diffusion barrier is formed on a surface of the metal line forming region of the insulation layer and has a stack structure composed of a MoxSiy layer and a Mo layer. The metal layer is formed on the diffusion barrier which fills in the metal line forming region of the insulation layer.Type: GrantFiled: May 27, 2009Date of Patent: December 20, 2011Assignee: Hynix Semiconductor Inc.Inventors: Joon Seok Oh, Seung Jin Yeom, Baek Mann Kim, Dong Ha Jung, Nam Yeal Lee, Jae Hong Kim
-
Publication number: 20110256697Abstract: A recessed-gate transistor device includes a gate electrode embedded in a gate trench formed in a semiconductor substrate, wherein the gate trench includes a vertical sidewall and a U-shaped bottom. A source region is provided at one side of the gate trench within the semiconductor substrate. A drain region is provided at the other side thereof. An asymmetric gate dielectric layer is formed between the gate electrode and the semiconductor substrate. The asymmetric gate dielectric layer has a first thickness between the gate electrode and the drain region and a second thickness between the gate electrode and the source region, wherein the first thickness is thicker than the second thickness.Type: ApplicationFiled: June 28, 2011Publication date: October 20, 2011Inventors: Jer-Chyi Wang, Tieh-Chiang Wu, Chung-Yuan Lee, Jeng-Ping Lin
-
Patent number: 8017482Abstract: The invention provides a method of manufacturing a semiconductor device at low cost in which the gate insulation film having a trench structure is not damaged by arsenic ions when the emitter layer or the like is formed and the insulation breakdown voltage is enhanced. A gate electrode made of polysilicon formed in a trench is thermally oxidized in a high temperature furnace or the like to form a thick polysilicon thermal oxide film on the gate electrode. Impurity ions are then ion-implanted to form an N type semiconductor layer that is to be an emitter layer or the like. At this time, the polysilicon thermal oxide film is formed thicker than the projected range Rp of impurity ions in the silicon oxide film for forming the N type semiconductor layer as the emitter layer or the like by ion implantation. This prevents a gate insulation film between the gate electrode and the N type semiconductor layer from being damaged by the impurity ions.Type: GrantFiled: December 21, 2010Date of Patent: September 13, 2011Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLCInventors: Toshikazu Matsui, Yasuyuki Sayama, Hiroki Eto, Takumi Hosoya
-
Patent number: 8008153Abstract: Nonvolatile memory devices are provided including an integrated circuit substrate and a charge storage pattern on the integrated circuit substrate. The charge storage pattern has a sidewall and a tunnel insulating layer is provided between the charge storage pattern and the integrated circuit substrate. A gate pattern is provided on the charge storage pattern. A blocking insulating layer is provided between the charge storage pattern and the gate pattern. The sidewall of the charge storage pattern includes a first nitrogen doped layer. Related methods of fabricating nonvolatile memory devices are also provided herein.Type: GrantFiled: June 19, 2009Date of Patent: August 30, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Hyun Lee, Dong-Gun Park
-
Patent number: 7999312Abstract: A semiconductor 100 has a P? body region and an N? drift region in the order from an upper surface side thereof. A gate trench and a terminal trench passing through the P? body region are formed. The respective trenches are surrounded with P diffusion regions at the bottom thereof. The gate trench builds a gate electrode therein. A P?? diffusion region, which is in contact with the end portion in a lengthwise direction of the gate trench and is lower in concentration than the P? body region and the P diffusion region, is formed. The P?? diffusion region is depleted prior to the P diffusion region when the gate voltage is off. The P?? diffusion region serves as a hole supply path to the P diffusion region when the gate voltage is on.Type: GrantFiled: January 26, 2007Date of Patent: August 16, 2011Assignee: Toyota Jidosha Kabushiki KaishaInventors: Hidefumi Takaya, Kimimori Hamada, Kyosuke Miyagi
-
Patent number: 7981781Abstract: A metal line of a semiconductor device includes an insulation layer formed on a semiconductor substrate. The insulation layer has a metal line forming region. A diffusion barrier is formed on a surface of the metal line forming region of the insulation layer. The diffusion barrier includes a stack structure including an MoxSiyNz layer and an Mo layer. A metal layer is formed on the diffusion barrier to fill the metal line forming region of the insulation layer.Type: GrantFiled: May 26, 2009Date of Patent: July 19, 2011Assignee: Hynix Semiconductor Inc.Inventors: Joon Seok Oh, Seung Jin Yeom, Jae Hong Kim
-
Patent number: 7981747Abstract: A technology is provided to reduce ON-resistance, and the prevention of punch through is achieved with respect to a trench gate type power MISFET. Input capacitance and a feedback capacitance are reduced by forming a groove in which a gate electrode is formed so as to have a depth as shallow as about 1 ?m or less, a p?type semiconductor region is formed to a depth so as not to cover the bottom of the groove, and a p-type semiconductor region higher in impurity concentration than the p?type semiconductor region is formed under a n+type semiconductor region serving as a source region of the trench gate type power MISFET, causing the p-type semiconductor region to serve as a punch-through stopper layer of the trench gate type power MISFET.Type: GrantFiled: April 27, 2009Date of Patent: July 19, 2011Assignee: Renesas Electronics CorporationInventors: Masaki Shiraishi, Yoshito Nakazawa
-
Publication number: 20110159672Abstract: This invention disclosed a manufacturing approach of collector and buried layer of a bipolar transistor. One aspect of the invention is that a pseudo buried layer, i.e, collector buried layer, is manufactured by ion implantation and thermal anneal. This pseudo buried layer has a small area, which makes deep trench isolation to divide pseudo buried layer unnecessary in subsequent process. Another aspect is, the doped area, i.e, collector, is formed by ion implantation instead of high cost epitaxy process. This invention simplified the manufacturing process, as a consequence, saved manufacturing cost.Type: ApplicationFiled: December 28, 2010Publication date: June 30, 2011Inventors: Tzuyin CHIU, TungYuan Chu, YungChieh Fan, Wensheng Qian, Fan Chen, Jiong Xu, Haifang Zhang
-
Publication number: 20110147843Abstract: A semiconductor component includes at least one field effect transistor disposed along a trench in a semiconductor region and has at least one locally delimited dopant region in the semiconductor region. The at least one locally delimited dopant region extends from or over a pn junction between the source region and the body region of the transistor or between the drain region and the body region of the transistor into the body region as far as the gate electrode, such that a gap between the pn junction and the gate electrode in the body region is bridged by the locally delimited dopant region.Type: ApplicationFiled: December 15, 2010Publication date: June 23, 2011Applicant: INFINEON TECHNOLOGIES AGInventors: Andrew Wood, Rudolf Zelsacher, Markus Zundel
-
Publication number: 20110129975Abstract: A method for fabricating a semiconductor device is provided, the method includes forming a double trench including a first trench and a second trench formed below the first trench and having surfaces covered with insulation layers, and removing portions of the insulation layers to form a side contact exposing one sidewall of the second trench.Type: ApplicationFiled: December 30, 2009Publication date: June 2, 2011Inventor: Sang-Oh LEE
-
Patent number: 7929321Abstract: A DC-to-DC converter includes a high-side transistor and a low-side transistor wherein the high-side transistor is implemented with a high-side enhancement mode MOSFET. The low side-transistor further includes a low-side enhancement MOSFET shunted with a depletion mode transistor having a gate shorted to a source of the low-side enhancement mode MOSFET. A current transmitting in the DC-to-DC converter within a time-period between T2 and T3 passes through a channel region of the depletion mode MOSFET instead of a built-in diode D2 of the low-side MOSFET transistor. The depletion mode MOSFET further includes trench gates surrounded by body regions with channel regions immediately adjacent to vertical sidewalls of the trench gates wherein the channel regions formed as depletion mode channel regions by dopant ions having electrical conductivity type opposite from a conductivity type of the body regions.Type: GrantFiled: August 22, 2008Date of Patent: April 19, 2011Assignee: Force-Mos Technology CorpInventor: Fwu-Iuan Hshieh
-
Patent number: 7927989Abstract: A transistor structure is formed by providing a semiconductor substrate and providing a gate above the semiconductor substrate. The gate is separated from the semiconductor substrate by a gate insulating layer. A source and a drain are provided adjacent the gate to define a transistor channel underlying the gate and separated from the gate by the gate insulating layer. A barrier layer is formed by applying nitrogen or carbon on opposing outer vertical sides of the transistor channel between the transistor channel and each of the source and the drain. In each of the nitrogen and the carbon embodiments, the vertical channel barrier retards diffusion of the source/drain dopant species into the transistor channel. There are methods for forming the transistor structure.Type: GrantFiled: July 27, 2007Date of Patent: April 19, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Da Zhang, Ning Liu, Mohamed S. Moosa
-
Publication number: 20110068440Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor wafer and forming at least one first trench in the wafer having first and second sidewalls and a first orientation on the wafer. The first sidewall of the at least one first trench is implanted with a dopant of a first conductivity at a first implantation direction. The first sidewall of the at least one first trench is implanted with the dopant of the first conductivity at a second implantation direction. The second implantation direction is orthogonal to the first implantation direction. The first and second implantation directions are non-orthogonal to the first sidewall.Type: ApplicationFiled: October 28, 2010Publication date: March 24, 2011Applicant: Icemos Technology Ltd.Inventors: Takeshi Ishiguro, Hugh J. Griffin, Kenji Sugiura
-
Publication number: 20110045664Abstract: A semiconductor device is formed having a trench adjacent to a current carrying region of the device. The trench is formed having a depth greater than the depth of a tub region of the device. Increasing the trench depth moves a region of higher field strength from the tub region to a region along the trench. The region along the trench does not have a junction and may withstand the higher field strength.Type: ApplicationFiled: November 1, 2010Publication date: February 24, 2011Applicant: HVVI SEMICONDUCTORS, INC.Inventor: Robert Bruce Davies
-
Patent number: 7863144Abstract: Embodiments relate to a semiconductor device and a method for manufacturing the device, which suppresses off-current by improving the problem of leakage current due to hump characteristics, making it possible to maximize the reliability of the device. Embodiments relate to a method for manufacturing a semiconductor device including forming a well having two ends in a semiconductor substrate. A shallow trench isolation (STI) is formed by etching both ends of the well and the semiconductor substrate adjacent both ends of the well. A gate oxide film and a photoresist film are formed over the upper surface of the semiconductor substrate including the STI. The photoresist film is patterned for an impurity ion implant into one side area including the edge of the side wall of the STI. A barrier area is formed by implanting an impurity ion into one side area including the side wall edge of the STI using the patterned photoresist film as a mask.Type: GrantFiled: August 29, 2007Date of Patent: January 4, 2011Assignee: Dongbu HiTek Co., Ltd.Inventor: Hyeong-Gyun Jeong
-
Patent number: 7851291Abstract: A method for selectively relieving channel stress for n-channel transistors with recessed, epitaxial SiGe source and drain regions is described. This increases the electron mobility for the n-channel transistors without affecting the strain in p-channel transistors. The SiGe provides lower resistance when a silicide is formed.Type: GrantFiled: May 26, 2009Date of Patent: December 14, 2010Assignee: Intel CorporationInventors: Lucian Shifren, Jack T. Kavalieros, Steven M. Cea, Cory E. Weber, Justin K. Brask
-
Patent number: 7839693Abstract: An electrically erasable programmable read-only memory (“CMOS NON-VOLATILE MEMORY”) cell is fabricated using standard CMOS fabrication processes. First and second polysilicon gates are patterned over an active area of the cell between source and drain regions. Thermal oxide is grown on the polysilicon gates to provide an isolating layer. Silicon nitride is deposited between the first and second polysilicon gates to form a lateral programming layer.Type: GrantFiled: January 7, 2010Date of Patent: November 23, 2010Assignee: Xilinix, Inc.Inventors: Sunhom Paak, Boon Y. Ang, Hsung J. Im, Daniel Gitlin
-
Patent number: 7829446Abstract: A method for dividing a wafer into a plurality of chips is provided. The method includes providing recesses in a surface of the wafer at positions along boundaries between regions to become the individual chips, providing fragile portions having a predetermined width inside the wafer at positions along the boundaries by irradiation of the other surface of the wafer with a laser beam whose condensing point is placed inside the wafer, the fragile portions including connected portions at least at one of the surfaces of the wafer, and dividing the wafer at the fragile portions into the individual chips by applying an external force to the wafer.Type: GrantFiled: November 8, 2007Date of Patent: November 9, 2010Assignee: Seiko Epson CorporationInventors: Wataru Takahashi, Yoshinao Miyata, Kazushige Umetsu, Yutaka Yamazaki
-
Patent number: 7824982Abstract: The invention includes a method of forming a semiconductor construction. Dopant is implanted into the upper surface of a monocrystalline silicon substrate. The substrate is etched to form a plurality of trenches and cross-trenches which define a plurality of pillars. After the etching, dopant is implanted within the trenches to form a source/drain region that extends less than an entirety of the trench width. The invention includes a semiconductor construction having a bit line disposed within a semiconductor substrate below a first elevation. A wordline extends elevationally upward from the first elevation and substantially orthogonal relative to the bit line. A vertical transistor structure is associated with the wordline. The transistor structure has a channel region laterally surrounded by a gate layer and is horizontally offset relative to the bit line.Type: GrantFiled: December 12, 2007Date of Patent: November 2, 2010Assignee: Micron Technology, Inc.Inventor: Leonard Forbes
-
Patent number: 7803701Abstract: A method for fabricating the semiconductor device comprises providing a semiconductor substrate having a device region and a testkey region. A first trench is formed in the device region and a second trench is formed in the testkey region. A conductive layer with a first etching selectivity is formed in the first and second trenches. A first implantation process is performed in a first direction to form a first doped region with a first impurity and an undoped region in the conductive layer simultaneously and respectively in the device region and in the testkey region. A second implantation process is performed in the second trench to form a second doped region with a second impurity in the conductive layer, wherein the conductive layer in the second trench has a second etching selectivity higher than the first etching selectivity.Type: GrantFiled: December 26, 2007Date of Patent: September 28, 2010Assignee: Nanya Technology CorporationInventors: Shian-Jyh Lin, Shun-Fu Chen, Tse-Chuan Kuo, An-Hsiung Liu
-
Publication number: 20100224932Abstract: A semiconductor 100 has a P? body region and an N? drift region in the order from an upper surface side thereof. A gate trench and a terminal trench passing through the P? body region are formed. The respective trenches are surrounded with P diffusion regions at the bottom thereof. The gate trench builds a gate electrode therein. A P?? diffusion region, which is in contact with the end portion in a lengthwise direction of the gate trench and is lower in concentration than the P? body region and the P diffusion region, is formed. The P?? diffusion region is depleted prior to the P diffusion region when the gate voltage is off. The P?? diffusion region serves as a hole supply path to the P diffusion region when the gate voltage is on.Type: ApplicationFiled: January 26, 2007Publication date: September 9, 2010Inventors: Hidefumi Takaya, Kimimori Hamada, Kyosuke Miyagi
-
Patent number: 7759174Abstract: A semiconductor device includes a substrate including a semiconductor and a trench, and an electrically rewritable semiconductor memory cell on the substrate, the semiconductor memory cell comprising a charge storage layer including an upper surface and a lower surface, an area of the lower surface being smaller than an area of the upper surface, and at least a part of the charge storage layer being provided in the trench, first insulating layer between the lower surface of the charge storage layer and a bottom surface of the trench, second insulating layer between a side surface of the trench and a side surface of the charge storage layer and between the side surface of the trench and a side surface of the first insulating layer, third insulating layer on the charge storage layer, and a control gate electrode on the third insulating layer.Type: GrantFiled: January 24, 2007Date of Patent: July 20, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Katsuhiko Hieda
-
Patent number: 7750405Abstract: A method of fabricating a high-performance planar back-gate CMOS structure having superior short-channel characteristics and reduced capacitance using processing steps that are not too lengthy or costly is provided. Also provided is a high-performance planar back-gate CMOS structure that is formed utilizing the method of the present invention. The method includes forming an opening in an upper surface of a substrate. Thereafter, a dopant region is formed in the substrate through the opening. In accordance with the inventive method, the dopant region defines a back-gate conductor of the inventive structure. Next, a front gate conductor having at least a portion thereof is formed within the opening.Type: GrantFiled: October 24, 2007Date of Patent: July 6, 2010Assignee: International Business Machines CorporationInventor: Edward J. Nowak
-
Patent number: 7749860Abstract: The present invention relates to a method for forming an isolation trench structure in a semiconductor substrate without causing deleterious topographical depressions in the upper surface thereof which cause current and charge leakage to an adjacent active area. The inventive method forms a pad oxide upon a semiconductor substrate, and then forms a nitride layer on the pad oxide. The nitride layer is patterned with a mask and etched to expose a portion of the pad oxide layer and to protect an active area in the semiconductor substrate that remains covered with the nitride layer. A second dielectric layer is formed substantially conformably over the pad oxide layer and the remaining portions of the first dielectric layer. A spacer etch is then carried out to form a spacer from the second dielectric layer. The spacer is in contact with the remaining portion of the first dielectric layer. An isolation trench etch follows the spacer etch.Type: GrantFiled: September 8, 1999Date of Patent: July 6, 2010Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, David Chapek, Ranshir P. S. Thakur
-
Patent number: 7700468Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor device. In the method, a field oxide layer can be formed in a semiconductor substrate so as to define and active electrode including a gate oxide layer and a gate poly is formed in the active region. An etch groove is formed between the gate electrode and the field oxide layer. Dopant ions are implanted between the gate electrode and the field oxide layer so as to form a source/drain region.Type: GrantFiled: August 7, 2007Date of Patent: April 20, 2010Assignee: Dongbu Hitek Co., Ltd.Inventor: Ji Houn Jung
-
Publication number: 20100090219Abstract: A method of fabrication of a semiconductor device having low resistance in an interconnection line and the same coefficient of thermal expansion as a semiconductor substrate is disclosed. The method includes forming a nitride film over a semiconductor substrate including a bottom metal line and a top metal line connected to each other through a plurality of vias, forming a trench at a through-silicon via (TSV) region of the semiconductor substrate, filling the trench with a predetermined material to form a silicon film, exposing the silicon film using a photoresist pattern, ion-implanting a dopant into the exposed silicon film, and selectively performing laser annealing to the silicon film to diffuse only the dopant implanted into the silicon film.Type: ApplicationFiled: September 29, 2009Publication date: April 15, 2010Inventor: Oh-Jin Jung
-
Patent number: 7696051Abstract: A MOSFET includes a semiconductor substrate with a first region having a relatively thick first thickness and a second region having a relatively thin second thickness; a gate insulating layer pattern formed on the first region of the semiconductor substrate; a gate conductive layer pattern formed on the gate insulating layer pattern; an epitaxial layer formed on the second region of the semiconductor substrate so as to have a predetermined thickness; spacers formed on sidewalls of the gate conductive layer pattern and part of the surface of the epitaxial layer; a lightly-doped first impurity region formed in the semiconductor substrate disposed below the spacers and in the epitaxial layer; and a heavily-doped second impurity region formed in a portion of the semiconductor substrate, exposed by the spacers.Type: GrantFiled: July 7, 2005Date of Patent: April 13, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: You-seung Jin, Jong-hyon Ahn
-
Publication number: 20100044796Abstract: A DC-to-DC converter includes a high-side transistor and a low-side transistor wherein the high-side transistor is implemented with a high-side enhancement mode MOSFET. The low side-transistor further includes a low-side enhancement MOSFET shunted with a depletion mode transistor having a gate shorted to a source of the low-side enhancement mode MOSFET. A current transmitting in the DC-to-DC converter within a time-period between T2 and T3 passes through a channel region of the depletion mode MOSFET instead of a built-in diode D2 of the low-side MOSFET transistor. The depletion mode MOSFET further includes trench gates surrounded by body regions with channel regions immediately adjacent to vertical sidewalls of the trench gates wherein the channel regions formed as depletion mode channel regions by dopant ions having electrical conductivity type opposite from a conductivity type of the body regions.Type: ApplicationFiled: August 22, 2008Publication date: February 25, 2010Inventor: Fwu-Iuan Hshieh
-
Publication number: 20100035388Abstract: Provided is a method for fabricating a semiconductor device. The method includes: forming a photoresist pattern having a first opening over a substrate; forming a first impurity region inside the substrate exposed to the first opening; partially etching the photoresist pattern by a plasma ashing process using oxygen (O2) gas to form a second opening having a width broader than that of the first opening; and forming a second impurity region inside the substrate exposed through the second opening, wherein the width of the second opening varies according to a plasma ashing time.Type: ApplicationFiled: May 27, 2009Publication date: February 11, 2010Inventors: Kee-Joon CHOI, Il-Kyoo PARK
-
Patent number: 7651930Abstract: A method of manufacturing a semiconductor storage device includes providing an opening portion in a plurality of positions in an insulating film formed on a silicon substrate, and thereafter forming an amorphous silicon film on the insulating film, in which the opening portions are formed, and in the opening portions. Then, trenches are formed to divide the amorphous silicon film, in the vicinity of a midpoint between adjacent opening portions, into a portion on one opening portion side and a portion on the other opening portion side. Next, the amorphous silicon film, in which the trenches are formed, is annealed and subjected to solid-phase crystallization to form a single crystal with the opening portions used as seeds, and thereby a silicon single-crystal layer is formed. Then, a memory cell array is formed on the silicon single-crystal layer.Type: GrantFiled: June 26, 2008Date of Patent: January 26, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Suzuki, Hirokazu Ishida, Ichiro Mizushima, Yoshio Ozawa, Fumiki Aiso, Katsuyuki Sekine, Takashi Nakao, Yoshihiko Saito
-
Patent number: 7652323Abstract: A semiconductor device having step gates includes a semiconductor substrate including first regions having relatively low steps at both ends of an active region defined by trench isolation films and a second region having a relatively high step at a central part of the active region, a groove having a predetermined depth being formed at the central part of the second region, step gate stacks formed on the boundary between the first region and second region while exposing the groove of the second region, first impurity regions formed in the first regions exposed by the step gate stacks, and a second impurity region formed in the second region exposed by the step gate stacks while enclosing the groove of the second region.Type: GrantFiled: December 1, 2005Date of Patent: January 26, 2010Assignee: Hynix Semiconductor Inc.Inventors: Byung Soo Eun, Jung Suk Lee
-
Patent number: 7638425Abstract: A metal line of a semiconductor device having a diffusion barrier including CrxBy and a method for forming the same is described. The metal line of a semiconductor device includes an insulation layer formed on a semiconductor substrate. The insulation layer is formed having a metal line forming region. A diffusion barrier including a CrxBy layer is subsequently formed on the surface of the metal line forming region and the insulation layer. A metal line is finally formed to fill the metal line forming region of the insulation layer on the diffusion barrier including a CrxBy layer.Type: GrantFiled: November 15, 2007Date of Patent: December 29, 2009Assignee: Hynix Semiconductor Inc.Inventors: Dong Ha Jung, Seung Jin Yeom, Baek Mann Kim, Young Jin Lee, Jeong Tae Kim
-
Patent number: 7629238Abstract: Disclosed are an isolation structure and a method for forming the same. The present isolation structure includes a substrate having a first semiconductor layer having a first lattice parameter, a second semiconductor layer having a second lattice parameter larger than the first lattice parameter, and a strained semiconductor layer; a well in the substrate; a plurality of isolation layers in the strained semiconductor layer and the second semiconductor layer, defining an active region; and a plurality of punch stop layers under the isolation layers.Type: GrantFiled: July 26, 2006Date of Patent: December 8, 2009Assignee: Dongbu Electronics Co., Ltd.Inventor: Myung Jin Jung
-
Publication number: 20090273030Abstract: A low cost integration method for a plurality of deep isolation trenches on the same chip is provided. The trenches have an additional n-type or p-type doped region surrounding the trench—silicon interface. Providing such variations of doping the trench interface is achieved by using implantation masking layers or doped glass films structured by a simple resist mask. By simple layout variation of the top dimension of the trench various trench depths at the same time can be ensured. Using this method, wider trenches will be deeper and smaller trenches will be shallower.Type: ApplicationFiled: May 15, 2007Publication date: November 5, 2009Applicant: AUSTRIAMICROSYSTEMS AGInventors: Martin Schrems, Jong Mun Park