Including Heat Treatment Patents (Class 438/530)
  • Patent number: 9905433
    Abstract: An ion implantation results in defects generated in a nitride semiconductor layer. If the nitride semiconductor layer is set at a particular temperature for a predetermined time period after the ion implantation, the defects may probably be clustering. Provided is a manufacturing method of a semiconductor device including a nitride semiconductor layer comprising: implanting impurities in the nitride semiconductor layer; and increasing a temperature of the nitride semiconductor layer from an initial temperature to a target temperature and annealing the nitride semiconductor layer at the target temperature for a predetermined time period; wherein in the annealing, in at least part of temperature regions below a first temperature between the initial temperature and the target temperature, the nitride semiconductor layer is annealed at a temperature increase speed lower than in a temperature region not lower than the first temperature.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: February 27, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shinya Takashima, Katsunori Ueno, Masaharu Edo, Akira Uedono
  • Patent number: 9583309
    Abstract: Apparatus and methods for the selective implanting of the outer portion of a workpiece are disclosed. A mask is disposed between the ion beam and the workpiece, having an aperture through which the ion beam passes. The aperture may have a concave first edge, forming using a radius equal to the inner radius of the outer portion of the workpiece. Further, the mask is affixed to a roplat such that the platen is free to rotate between a load/unload position and an operational position without moving the mask. In certain embodiments, the mask is affixed to the base of the roplat and has a first portion with an aperture that extends vertically upward from the base, and a second portion that is shaped so as not to interfere with the rotation of the platen. In other embodiments, the mask may be affixed to the arms of the roplat.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: February 28, 2017
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Jordan B. Tye, Mark R. Amato
  • Patent number: 9425047
    Abstract: A method of forming a wide line includes forming a portion of variable-fluidity material between opposing inner walls of a pair of adjacent line portions, the portion of variable-fluidity material patterned to have a lateral dimension that is smaller than a distance between the opposing inner walls of the pair of adjacent line portions, and subsequently applying process conditions that increase the fluidity of the portion of variable-fluidity material sufficiently to cause the portion of variable-fluidity material to extend to the opposing inner walls of the pair of adjacent line portions.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: August 23, 2016
    Assignee: SanDisk Technologies LLC
    Inventor: Akihiro Tobioka
  • Patent number: 9412832
    Abstract: In aspects of the invention, an n-type epitaxial layer that forms an n? type drift layer is formed on the upper surface of an n-type semiconductor substrate formed by being doped with a high concentration of antimony. A p-type anode layer is formed on a surface of the n? type drift layer. An n-type contact layer is formed with an impurity concentration in the same region as the impurity concentration of the n-type cathode layer, or higher than the impurity concentration of the n-type cathode layer, on the lower surface of the n-type cathode layer. A cathode electrode is formed so as to be in contact with the n-type contact layer. The n-type contact layer is doped with phosphorus and, without allowing complete recrystallization using a low temperature heat treatment of 500° C. or less, lattice defects are allowed to remain.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: August 9, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Mitsuaki Kirisawa
  • Patent number: 9171943
    Abstract: To provide a semiconductor device including an oxide semiconductor which is capable of having stable electric characteristics and achieving high reliability, by a dehydration or dehydrogenation treatment performed on a base insulating layer provided in contact with an oxide semiconductor layer, the water and hydrogen contents of the base insulating layer can be decreased, and by an oxygen doping treatment subsequently performed, oxygen which can be eliminated together with the water and hydrogen is supplied to the base insulating layer. By formation of the oxide semiconductor layer in contact with the base insulating layer whose water and hydrogen contents are decreased and whose oxygen content is increased, oxygen can be supplied to the oxide semiconductor layer while entry of the water and hydrogen into the oxide semiconductor layer is suppressed.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: October 27, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Naoto Yamade, Junichi Koezuka, Miki Suzuki, Yuichi Sato
  • Patent number: 9166096
    Abstract: A method for manufacturing a dopant layer of a solar cell according to an embodiment of the invention includes: ion-implanting a dopant to a substrate; and heat-treating for an activation of the dopant. In the heat-treating for the activation, the substrate is heat-treated at a first temperature after an anti-out-diffusion film is formed at a temperature lower than the first temperature under a first gas atmosphere.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 20, 2015
    Assignee: LG ELECTRONICS INC.
    Inventors: Juhwa Cheong, Yongduk Jin, Youngsung Yang, Manhyo Ha
  • Patent number: 9130112
    Abstract: A method for manufacturing a dopant layer of a solar cell according to an embodiment of the invention includes: ion-implanting a dopant to a substrate; and heat-treating for an activation of the dopant. In the heat-treating for the activation, the substrate is heat-treated at a first temperature after an anti-out-diffusion film is formed at a temperature lower than the first temperature under a first gas atmosphere.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 8, 2015
    Assignee: LG ELECTRONICS INC.
    Inventors: Juhwa Cheong, Yongduk Jin, Youngsung Yang, Manhyo Ha
  • Patent number: 9054056
    Abstract: A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: June 9, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hiroaki Niimi, Jarvis Benjamin Jacobs, Ajith Varghese
  • Patent number: 9041147
    Abstract: According to a semiconductor substrate (40), a space (A) between a plurality of Si thin film (16), which are provide apart from one another on the insulating substrate (30), is (I) larger than a difference between elongation of part of the insulating substrate which part corresponds to the space (A) and elongation of each of Si wafers (10) when a change is made from room temperature to 600° C. and (II) smaller than 5 mm. This causes an increase in a region of each of a plurality of semiconductor thin films which region has a uniform thickness, and therefore prevents transferred semiconductor layers and the insulating substrate from being fractured or chipped.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: May 26, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Masahiro Mitani
  • Patent number: 9029251
    Abstract: A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: May 12, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroaki Niimi, Jarvis Benjamin Jacobs, Ajith Varghese
  • Publication number: 20150108539
    Abstract: A fabrication method of a semiconductor device includes forming a mask insulating film having a specified thickness on the top surface of an n-type semiconductor substrate, forming an opening at a specified position in the mask insulating film, carrying out ion implantation with p-type impurity ions onto the top surface, removing a layer portion formed in the mask insulating film with the p-type impurities included by the ion implantation, and carrying out heat treatment to diffuse the p-type impurities implanted into the n-type semiconductor substrate from the opening to a depth, thereby forming the p-type isolation region.
    Type: Application
    Filed: September 12, 2014
    Publication date: April 23, 2015
    Inventor: Mitsuhiro KAKEFU
  • Patent number: 9012313
    Abstract: A semiconductor structure includes a substrate and a resistor provided over the substrate. The resistor includes a first material layer, a second material layer, a first contact structure and a second contact structure. The first material layer includes at least one of a metal and a metal compound. The second material layer includes a semiconductor material. The second material layer is provided over the first material layer and includes a first sub-layer and a second sub-layer. The second sub-layer is provided over the first sub-layer. The first sub-layer and the second sub-layer are differently doped. Each of the first contact structure and the second contact structure provides an electrical connection to the second sub-layer of the second material layer.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: April 21, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Alexandru Romanescu
  • Publication number: 20150099350
    Abstract: Embodiments of the present disclosure generally relate to doping and annealing substrates. The substrates may be doped during a hot implantation process, and subsequently annealed using a nanosecond annealing process. The combination of hot implantation and nanosecond annealing reduces lattice damage of the substrates and facilitates a higher dopant concentration near the surface of the substrate to facilitate increased electrical contact with the substrate. An optional capping layer may be placed over the substrate to reduce outgassing of dopants or to control dopant implant depth.
    Type: Application
    Filed: October 1, 2014
    Publication date: April 9, 2015
    Inventors: Swaminathan T. SRINIVASAN, Fareen Adeni KHAJA
  • Patent number: 8999800
    Abstract: In one embodiment a method of forming low contact resistance in a substrate includes forming a silicide layer on the substrate, the silicide layer and substrate defining an interface therebetween in a source/drain region, and performing a hot implant of a dopant species into the silicide layer while the substrate is at a substrate temperature greater than 150° C., where the hot implant is effective to generate an activated dopant layer containing the dopant species, and the activated dopant layer extends from the interface into the source/drain region.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: April 7, 2015
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Fareen Adeni Khaja, Benjamin Colombeau
  • Patent number: 8999825
    Abstract: This invention relates to a method of healing defects at junctions of a semiconductor device, which includes growing a p-Ge layer on a substrate, performing ion implantation on the p-Ge layer to form an n+ Ge region or performing in-situ doping on the p-Ge layer and then etching to form an n+ Ge region or depositing an oxide film on the p-Ge layer and performing patterning, etching and in-situ doping to form an n+ Ge layer, forming a capping oxide film, performing annealing at 600˜700° C. for 1˜3 hr, and depositing an electrode, and in which annealing enables Ge defects at n+/p junctions to be healed and the depth of junctions to be comparatively reduced, thus minimizing leakage current, thereby improving properties of the semiconductor device and achieving high integration and fineness of the semiconductor device.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: April 7, 2015
    Assignees: Korea Advanced Nano Fab Center, Sungkyunkwan University Research & Business Foundation
    Inventors: Won Kyu Park, Jong Gon Heo, Dong Hwan Jun, Jin Hong Park, Jae Woo Shim
  • Patent number: 8993426
    Abstract: The invention provides a semiconductor device with a junction termination extension structure on a mesa and a method of fabricating the same. The device comprises: a type-I semiconductor substrate having a first surface and a second surface; a type-I epitaxial layer disposed on the first surface; at least one depression disposed on the type-I epitaxial layer; a mesa-type junction termination extension structure surrounding the at least one depression wherein the mesa-type junction termination extension structure is of type-II; and at least one semiconductor component formed one the depression.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: March 31, 2015
    Inventor: Chii-Wen Jiang
  • Patent number: 8993424
    Abstract: Provided is a transistor and a method for forming a transistor in a semiconductor device. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a very low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure so-formed includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile also includes the transistor channel having high dopant impurity concentration areas at opposed ends of the transistor channel.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Wen Liu, Tsung-Hsing Yu, Dhanyakumar Mahaveer Sathaiya, Wei-Hao Wu, Ken-Ichi Goto, Tzer-Min Shen, Zhiqiang Wu
  • Patent number: 8975156
    Abstract: A method of sealing a first wafer and a second wafer each made of semiconducting materials, including: implanting a metallic species in at least the first wafer, assembling the first wafer and the second wafer by molecular bonding, and after the molecular bonding, forming a metallic ohmic contact including alloys formed between the implanted metallic species and the semiconducting materials of the first wafer and the second wafer, the metallic ohmic contact being formed at an assembly interface between the first wafer and the second wafer, wherein the forming includes causing the implanted metallic species to diffuse towards the interface between the first wafer with the second wafer and beyond the interface.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: March 10, 2015
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Stephane Pocas, Hubert Moriceau, Jean-Francois Michaud
  • Patent number: 8956937
    Abstract: The present invention discloses to a method of depositing the metal barrier layer comprising silicon dioxide. It is applied in the transistor device comprising a silicon substrate, a gate and a gate side wall. The method comprises the following steps: ions are implanted into the silicon substrate to form an active region in the said silicon substrate; a first dense silicon dioxide film is deposited; a second normal silicon dioxide film is deposited; the said transistor device is high temperature annealed. The present invention ensures that the implanted ion is not separated out of the substrate during the annealing. And it prevents the warping and fragment of the silicon surface.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: February 17, 2015
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: GuoFang Xuan, Fei Luo
  • Patent number: 8956907
    Abstract: There is provided a method of fabricating a field effect transistor including: forming a first oxide semiconductor film on a gate insulation layer disposed on a gate electrode; forming a second oxide semiconductor film on the first oxide semiconductor film, the second oxide semiconductor film differing in cation composition from the first oxide semiconductor film and being lower in electrical conductivity than the first oxide semiconductor film; applying a heat treatment at over 300° C. in an oxidizing atmosphere; forming a third oxide semiconductor film on the second oxide semiconductor film, the third oxide semiconductor film differing in cation composition from the first oxide semiconductor film and being lower in electrical conductivity than the first oxide semiconductor film; applying a heat treatment in an oxidizing atmosphere; and, forming a source electrode and a drain electrode on the third oxide semiconductor film.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: February 17, 2015
    Assignee: FUJIFILM Corporation
    Inventors: Masashi Ono, Masahiro Takata, Fumihiko Mochizuki, Atsushi Tanaka, Masayuki Suzuki
  • Patent number: 8951895
    Abstract: Improved complementary doping methods are described herein. The complementary doping methods generally involve inducing a first and second chemical reaction in at least a first and second portion, respectively, of a dopant source, which has been disposed on a thin film of a semiconductor or semimetal material. The chemical reactions result in the introduction of an n-type dopant, a p-type dopant, or both from the dopant source to each of the first and second portions of the thin film of the semiconductor or semimetal. Ultimately, the methods produce at least one n-type and at least one p-type region in the thin film of the semiconductor or semimetal.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: February 10, 2015
    Assignee: Georgia Tech Research Corporation
    Inventors: Kevin Andrew Brenner, Raghunath Murali
  • Patent number: 8951896
    Abstract: According to a method herein, a first side of a substrate is implanted with a first material to change a crystalline structure of the first side of the substrate from a first crystalline state to a second crystalline state, after the first material is implanted. A second material is deposited on the first side of the substrate, after the first material is implanted. A first side of an insulator layer is bonded to the second material on the first side of the substrate. Integrated circuit devices are formed on a second side of the insulator layer, opposite the first side of the insulator layer, after the insulator layer is bonded to the second material. The integrated circuit devices are thermally annealed. The first material maintains the second crystalline state of the first side of the substrate during the annealing.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Alan B. Botula, Jeffrey E. Hanrahan, Mark D. Jaffe, Alvin J. Joseph, Dale W. Martin, Gerd Pfeiffer, James A. Slinkman
  • Patent number: 8951899
    Abstract: To provide a semiconductor device including an oxide semiconductor which is capable of having stable electric characteristics and achieving high reliability, by a dehydration or dehydrogenation treatment performed on a base insulating layer provided in contact with an oxide semiconductor layer, the water and hydrogen contents of the base insulating layer can be decreased, and by an oxygen doping treatment subsequently performed, oxygen which can be eliminated together with the water and hydrogen is supplied to the base insulating layer. By formation of the oxide semiconductor layer in contact with the base insulating layer whose water and hydrogen contents are decreased and whose oxygen content is increased, oxygen can be supplied to the oxide semiconductor layer while entry of the water and hydrogen into the oxide semiconductor layer is suppressed.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: February 10, 2015
    Assignee: Semiconductor Energy Laboratory
    Inventors: Naoto Yamade, Junichi Koezuka, Miki Suzuki, Yuichi Sato
  • Patent number: 8946006
    Abstract: A disposable dielectric spacer is formed on sidewalls of a disposable material stack. Raised source/drain regions are formed on planar source/drain regions by selective epitaxy. The disposable dielectric spacer is removed to expose portions of a semiconductor layer between the disposable material stack and the source/drain regions including the raised source/drain regions. Dopant ions are implanted to form source/drain extension regions in the exposed portions of the semiconductor layer. A gate-level dielectric layer is deposited and planarized. The disposable material stack is removed and a gate stack including a gate dielectric and a gate electrode fill a cavity formed by removal of the disposable material stack. Optionally, an inner dielectric spacer may be formed on sidewalls of the gate-level dielectric layer within the cavity prior to formation of the gate stack to tailor a gate length of a field effect transistor.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Shom Ponoth, David V. Horak, Chih-Chao Yang
  • Patent number: 8937005
    Abstract: A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: January 20, 2015
    Assignee: SuVolta, Inc.
    Inventors: Lance S. Scudder, Pushkar Ranade, Charles Stager, Urupattur C. Sridharan, Dalong Zhao
  • Publication number: 20150011080
    Abstract: The method includes the steps of a) Providing a stack having a support substrate and a film of GaN having dopant species, b) Directly bonding a shielding layer having a thickness higher than 2 micrometers to the surface of the film of GaN, so as to form an activation structure, and c) Applying a thermal budget to the activation structure according to conditions allowing to electrically activate at least one portion of the dopant species.
    Type: Application
    Filed: June 25, 2014
    Publication date: January 8, 2015
    Inventor: Claire AGRAFFEIL
  • Patent number: 8927375
    Abstract: Embodiment of the present invention provides a method of forming a semiconductor device. The method includes providing a semiconductor substrate; epitaxially growing a silicon-carbon layer on top of the semiconductor substrate; amorphizing the silicon-carbon layer; covering the amorphized silicon-carbon layer with a stress liner; and subjecting the amorphized silicon-carbon layer to a solid phase epitaxy (SPE) process to form a highly substitutional silicon-carbon film. In one embodiment, the highly substitutional silicon-carbon film is formed to be embedded stressors in the source/drain regions of an nFET transistor, and provides tensile stress to a channel region of the nFET transistor for performance enhancement.
    Type: Grant
    Filed: October 8, 2012
    Date of Patent: January 6, 2015
    Assignees: International Business Machines Corporation, STMicroelectronics
    Inventors: Emre Alptekin, Abhishek Dube, Henry K. Utomo, Reinaldo A. Vega, Bei Liu
  • Publication number: 20140374793
    Abstract: A p+ collector layer is provided in a rear surface of a semiconductor substrate which will be an n? drift layer and an n+ field stop layer is provided in a region which is deeper than the p+ collector layer formed on the rear surface side. A front surface element structure is formed on the front surface of the semiconductor substrate and then protons are radiated to the rear surface of the semiconductor substrate at an acceleration voltage corresponding to the depth at which the n+ field stop layer is formed. A first annealing process is performed at an annealing temperature corresponding to the proton irradiation to change the protons into donors, thereby forming a field stop layer. Then, annealing is performed using annealing conditions suitable for the conditions of a plurality of proton irradiation processes to recover each crystal defect formed by each proton irradiation process.
    Type: Application
    Filed: March 29, 2013
    Publication date: December 25, 2014
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Masayuki Miyazaki, Takashi Yoshimura, Hiroshi Takishita, Hidenao Kuribayashi
  • Publication number: 20140357026
    Abstract: A method for producing a semiconductor device includes an implantation step of performing proton implantation from a rear surface of a semiconductor substrate of a first conductivity type and a formation step of performing an annealing process for the semiconductor substrate in an annealing furnace to form a first semiconductor region of the first conductivity type which has a higher impurity concentration than the semiconductor substrate after the implantation step. In the formation step, the furnace is in a hydrogen atmosphere and the volume concentration of hydrogen is in the range of 6% to 30%. Therefore, it is possible to reduce crystal defects in the generation of donors by proton implantation. In addition, it is possible to improve the rate of change into a donor.
    Type: Application
    Filed: March 18, 2013
    Publication date: December 4, 2014
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke Kobayashi, Takashi Yoshimura
  • Patent number: 8895387
    Abstract: According to one embodiment, a method includes forming first and second gate patterns each including a structure stacked in order of a first insulating layer, a floating gate layer, a charge trap layer, a second insulating layer and a dummy layer on a semiconductor layer, implanting impurities in the semiconductor layer by an ion implantation using the first and second gate patterns as a mask, forming a third insulating layer on the semiconductor layer, the third insulating layer covering side surfaces of the first and second gate patterns, and forming first and second concave portions, the first concave portion formed by removing the dummy layer of the first gate pattern, the second concave portion formed by removing the dummy layer, the second insulating layer, the charge trap layer and the floating gate layer of the second gate pattern.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: November 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Motoyuki Sato
  • Publication number: 20140342538
    Abstract: An ion implantation system and method, providing cooling of dopant gas in the dopant gas feed line, to combat heating and decomposition of the dopant gas by arc chamber heat generation, e.g., using boron source materials such as B2F4 or other alternatives to BF3. Various arc chamber thermal management arrangements are described, as well as modification of plasma properties, specific flow arrangements, cleaning processes, power management, eqillibrium shifting, optimization of extraction optics, detection of deposits in flow passages, and source life optimization, to achieve efficient operation of the ion implantation system.
    Type: Application
    Filed: August 5, 2014
    Publication date: November 20, 2014
    Applicant: Advanced Technology Materials, Inc.
    Inventors: Edward E. Jones, Sharad N. Yedave, Ying Tang, Barry Lewis Chambers, Robert Kaim, Joseph D. Sweeney, Oleg Byl, Peng Zou
  • Patent number: 8874254
    Abstract: An object of the present invention is to perform temperature setting of a heating plate so that a wafer is uniformly heated in an actual heat processing time. The temperature of a wafer is measured during a heat processing period from immediately after a temperature measuring wafer is mounted on the heating plate to the time when the actual heat processing time elapses. Whether the uniformity in temperature within the wafer is allowable or not is determined from the temperature of the wafer in the heat processing period, and if the determination result is negative, a correction value for a temperature setting parameter of the heating plate is calculated using a correction value calculation model from the measurement result, and the temperature setting parameter is changed.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: October 28, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Shuji Iwanaga, Nobuyuki Sata
  • Patent number: 8859409
    Abstract: A semiconductor component includes a semiconductor body having a first side and a second side opposite the first side. In the semiconductor body, a dopant region is formed by a dopant composed of an oxygen complex. The dopant region extends over a section L having a length of at least 10 ?m along a direction from the first side to the second side. The dopant region has an oxygen concentration in a range of 1×1017 cm?3 to 5×1017 cm?3 over the section L.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: October 14, 2014
    Assignee: Infineon Technologies AG
    Inventors: Thomas Neidhart, Franz Josef Niedernostheide, Hans-Joachim Schulze, Werner Schustereder, Alexander Susiti
  • Patent number: 8859408
    Abstract: Generally, the present disclosure is directed to methods of stabilizing metal silicide contact regions formed in a silicon-germanium active area of a semiconductor device, and devices comprising stabilized metal silicides. One illustrative method disclosed herein includes performing an activation anneal to activate dopants implanted in an active area of a semiconductor device, wherein the active area comprises germanium. Additionally, the method includes, among other things, performing an ion implantation process to implant ions into the active area after performing the activation anneal, forming a metal silicide contact region in the active area, and forming a conductive contact element to the metal silicide contact region.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: October 14, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Clemens Fitz, Tom Herrmann
  • Publication number: 20140291723
    Abstract: A method of producing a seminconductor device is disclosed in which, after proton implantation is performed, a hydrogen-induced donor is formed by a furnace annealing process to form an n-type field stop layer. A disorder generated in a proton passage region is reduced by a laser annealing process to form an n-type disorder reduction region. As such, the n-type field stop layer and the n-type disorder reduction region are formed by the proton implantation. Therefore, it is possible to provide a stable and inexpensive semiconductor device which has low conduction resistance and can improve electrical characteristics, such as a leakage current, and a method for producing the semiconductor device.
    Type: Application
    Filed: June 11, 2014
    Publication date: October 2, 2014
    Inventors: Masayuki MIYAZAKI, Takashi YOSHIMURA, Hiroshi TAKISHITA, Hidenao KURIBAYASHI
  • Publication number: 20140273328
    Abstract: A semiconductor device is fabricated by performing the steps of: (a) implanting dopant ions into a semiconductor base member, which is made of single-crystal Si, to define at least one of an n-type region and a p-type region in the semiconductor base member; (b) conducting a first heat treatment on the semiconductor base member, in which the n-type or p-type region has been defined, at a temperature rise/fall rate of 40° C./sec or more and with the highest temperature to reach set within the range of 1000° C. to 1200° C.; and (c) conducting a second heat treatment on the semiconductor base member, which has gone through the first heat treatment, at a lower temperature rise/fall rate than in the first heat treatment.
    Type: Application
    Filed: May 16, 2013
    Publication date: September 18, 2014
    Inventors: Akihiko Sagara, Satoshi Shibata
  • Publication number: 20140273421
    Abstract: A high throughput system for warming a wafer to a desired temperature after undergoing a low-temperature implantation process includes an implantation chamber, a wafer warming chamber configured to uniformly warm a single wafer, and a plurality of robotic arms to transfer wafers throughout the system. At each stage in the fabrication process, the robotic arms simultaneously work with multiple wafers and, therefore, the system provides a high throughput process. Also, the warming chamber may be a vacuum environment, thus eliminating the mist-condensation problem that results in wafer spotting.
    Type: Application
    Filed: March 11, 2014
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: TSUN-JEN CHAN, CHENG-HUNG HU, YI-HANN CHEN, KANG HUA CHANG, MING-TE CHEN
  • Patent number: 8835288
    Abstract: A method of manufacturing a silicon carbide semiconductor device of an embodiment includes: implanting ions in a silicon carbide substrate; performing first heating processing of the silicon carbide substrate in which the ions are implanted; and performing second heating processing of the silicon carbide substrate for which the first heating processing is performed, at a temperature lower than the first heating processing.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: September 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Johji Nishio, Masaru Furukawa, Hiroshi Kono, Takashi Shinohe
  • Patent number: 8835291
    Abstract: Embodiments of the invention provide a semiconductor device and a method of manufacture. MOS devices along with their polycrystalline or amorphous gate electrodes are fabricated such that the intrinsic stress within the gate electrode creates a stress in the channel region between the MOS source/drain regions. Embodiments include forming an NMOS device and a PMOS device after having converted a portion of the intermediate NMOS gate electrode layer to an amorphous layer and then recrystallizing it before patterning to form the electrode. The average grain size in the NMOS recrystallized gate electrode is smaller than that in the PMOS recrystallized gate electrode. In another embodiment, the NMOS device comprises an amorphous gate electrode.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: September 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Chao Huang, Fu-Liang Yang
  • Patent number: 8828855
    Abstract: A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: September 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroaki Niimi, Jarvis Benjamin Jacobs, Ajith Varghese
  • Patent number: 8822315
    Abstract: A method is disclosed for treating a silicon carbide substrate for improved epitaxial deposition thereon and for use as a precursor in the manufacture of devices such as light emitting diodes. The method includes the steps of implanting dopant atoms of a first conductivity type into the first surface of a conductive silicon carbide wafer having the same conductivity type as the implanting ions at one or more predetermined dopant concentrations and implant energies to form a dopant profile, annealing the implanted wafer, and growing an epitaxial layer on the implanted first surface of the wafer.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: September 2, 2014
    Assignee: Cree, Inc.
    Inventors: Davis Andrew McClure, Alexander Suvorov, John Adam Edmond, David Beardsley Slater, Jr.
  • Patent number: 8816448
    Abstract: A semiconductor device including a semiconductor substrate, an interface layer formed on the semiconductor substrate including at least 1×1020 atoms/cm3 of S (Sulfur), a metal-semiconductor compound layer formed on the interface layer, the metal-semiconductor compound layer including at least 1×1020 atoms/cm3 of S in the its whole depth, and a metal electrode formed on the metal-semiconductor compound layer.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: August 26, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshifumi Nishi, Atsuhiro Kinoshita
  • Patent number: 8796771
    Abstract: A method of forming a transistor device includes implanting a diffusion inhibiting species in a semiconductor-on-insulator substrate comprising a bulk substrate, a buried insulator layer, and a semiconductor-on-insulator layer, the semiconductor-on-insulator substrate having one or more gate structures formed thereon such that the diffusion inhibiting species is disposed in portions of the semiconductor-on-insulator layer corresponding to a channel region, and disposed in portions of the buried insulator layer corresponding to source and drain regions. A transistor dopant species is introduced in the source and drain regions. An anneal is performed so as to diffuse the transistor dopant species in a substantially vertical direction while substantially preventing lateral diffusion of the transistor dopant species into the channel region.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: Brian J. Greene, Jeffrey B. Johnson, Qingqing Liang, Edward P. Maciejewski
  • Publication number: 20140209927
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type made of silicon carbide; and a second semiconductor layer of a second conductivity type made of silicon carbide, placed in junction with the first semiconductor layer, and containing an electrically inactive element.
    Type: Application
    Filed: January 29, 2014
    Publication date: July 31, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Johji NISHIO, Tatsuo SHIMIZU, Chiharu OTA, Takashi SHINOHE
  • Patent number: 8778786
    Abstract: Silicon loss prevention in a substrate during transistor device element manufacture is achieved by limiting a number of photoresist mask and chemical oxide layer stripping opportunities during the fabrication process. This can be achieved through the use of a protective layer that remains on the substrate during formation and stripping of photoresist masks used in identifying the implant areas into the substrate. In addition, undesirable reworking steps due to photoresist mask misalignment are eliminated or otherwise have no effect on consuming silicon from the substrate during fabrication of device elements. In this manner, device elements with the same operating characteristics and performance can be consistently made from lot to lot.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: July 15, 2014
    Assignee: SuVolta, Inc.
    Inventors: Lance Scudder, Pushkar Ranade, Dalong Zhao, Teymur Bakhishev, Urupattur C. Sridharan, Taiji Ema, Toshifumi Mori, Mitsuaki Hori, Junji Oh, Kazushi Fujita, Yasunobu Torii
  • Patent number: 8778766
    Abstract: A field effect transistor of an embodiment of the present invention includes, a semiconductor substrate containing Si atoms; a protruding structure formed on the semiconductor substrate; a channel region formed in the protruding structure and containing Ge atoms; an under channel region formed under the channel region in the protruding structure and containing Si and Ge atoms, the Ge composition ratio among Si and Ge atoms contained in the under channel region continuously changing from the channel region side to the semiconductor substrate side; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film on the channel region.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: July 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsutomu Tezuka, Toshifumi Irisawa
  • Patent number: 8772094
    Abstract: A highly reliable semiconductor device that includes a transistor including an oxide semiconductor is provided. In a manufacturing process of a semiconductor device that includes a bottom-gate transistor including an oxide semiconductor, an insulating film which is in contact with an oxide semiconductor film is subjected to dehydration or dehydrogenation treatment by heat treatment and oxygen doping treatment in this order. The insulating film which is in contact with the oxide semiconductor film refers to a gate insulating film provided under the oxide semiconductor film and an insulating film which is provided over the oxide semiconductor film and functions as a protective insulating film. The gate insulating film and/or the insulating film are/is subjected to dehydration or dehydrogenation treatment by heat treatment and oxygen doping treatment in this order.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: July 8, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Naoto Yamade, Junichi Koezuka, Shunpei Yamazaki
  • Publication number: 20140187027
    Abstract: Provided are methods of forming an ion implanted region in a semiconductor device. The methods comprise: (a) providing a semiconductor substrate having a plurality of regions to be ion implanted; (b) forming a photoresist pattern on the semiconductor substrate, wherein the photoresist pattern is formed from a chemically amplified photoresist composition comprising a matrix polymer having acid labile groups, a photoacid generator and a solvent; (c) coating a descumming composition over the photoresist pattern, wherein the descumming composition comprises: a matrix polymer; a free acid; and a solvent; (d) heating the coated semiconductor substrate; (e) contacting the coated semiconductor substrate with a rinsing agent to remove residual descumming composition and scum from the substrate; and (f) ion implanting the plurality of regions of the semiconductor substrate using the photoresist pattern as an implant mask. The methods find particular applicability in the manufacture of semiconductor devices.
    Type: Application
    Filed: December 31, 2013
    Publication date: July 3, 2014
    Inventors: Cheng-Bai XU, Cheng Han WU, Dong Won CHUNG, Yoshihiro YAMAMOTO
  • Patent number: 8765617
    Abstract: A method of manufacturing a MOSFET includes the steps of preparing a substrate with an epitaxial growth layer made of silicon carbide, performing ion implantation into the substrate with the epitaxial growth layer, forming a protective film made of silicon nitride on the substrate with the epitaxial growth layer into which the ion implantation was performed, and heating the substrate with the epitaxial growth layer on which the protective film was formed to a temperature range of 1600° C. or more in an atmosphere containing gas including a nitrogen atom.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: July 1, 2014
    Assignee: Sumitomo Electric Industries, Inc.
    Inventor: Takeyoshi Masuda
  • Publication number: 20140159150
    Abstract: In aspects of the invention, an n-type epitaxial layer that forms an n? type drift layer is formed on the upper surface of an n-type semiconductor substrate formed by being doped with a high concentration of antimony. A p-type anode layer is formed on a surface of the n? type drift layer. An n-type contact layer is formed with an impurity concentration in the same region as the impurity concentration of the n-type cathode layer, or higher than the impurity concentration of the n-type cathode layer, on the lower surface of the n-type cathode layer. A cathode electrode is formed so as to be in contact with the n-type contact layer. The n-type contact layer is doped with phosphorus and, without allowing complete recrystallization using a low temperature heat treatment of 500° C. or less, lattice defects are allowed to remain.
    Type: Application
    Filed: February 10, 2014
    Publication date: June 12, 2014
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Mitsuaki KIRISAWA