Abstract: A semiconductor device including a semiconductor substrate, an interface layer formed on the semiconductor substrate including at least 1×1020 atoms/cm3 of S (Sulfur), a metal-semiconductor compound layer formed on the interface layer, the metal-semiconductor compound layer including at least 1×1020 atoms/cm3 of S in the its whole depth, and a metal electrode formed on the metal-semiconductor compound layer.

Abstract: A method of forming a transistor device includes implanting a diffusion inhibiting species in a semiconductor-on-insulator substrate comprising a bulk substrate, a buried insulator layer, and a semiconductor-on-insulator layer, the semiconductor-on-insulator substrate having one or more gate structures formed thereon such that the diffusion inhibiting species is disposed in portions of the semiconductor-on-insulator layer corresponding to a channel region, and disposed in portions of the buried insulator layer corresponding to source and drain regions. A transistor dopant species is introduced in the source and drain regions. An anneal is performed so as to diffuse the transistor dopant species in a substantially vertical direction while substantially preventing lateral diffusion of the transistor dopant species into the channel region.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type made of silicon carbide; and a second semiconductor layer of a second conductivity type made of silicon carbide, placed in junction with the first semiconductor layer, and containing an electrically inactive element.

Abstract: Silicon loss prevention in a substrate during transistor device element manufacture is achieved by limiting a number of photoresist mask and chemical oxide layer stripping opportunities during the fabrication process. This can be achieved through the use of a protective layer that remains on the substrate during formation and stripping of photoresist masks used in identifying the implant areas into the substrate. In addition, undesirable reworking steps due to photoresist mask misalignment are eliminated or otherwise have no effect on consuming silicon from the substrate during fabrication of device elements. In this manner, device elements with the same operating characteristics and performance can be consistently made from lot to lot.

Abstract: A field effect transistor of an embodiment of the present invention includes, a semiconductor substrate containing Si atoms; a protruding structure formed on the semiconductor substrate; a channel region formed in the protruding structure and containing Ge atoms; an under channel region formed under the channel region in the protruding structure and containing Si and Ge atoms, the Ge composition ratio among Si and Ge atoms contained in the under channel region continuously changing from the channel region side to the semiconductor substrate side; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film on the channel region.

Abstract: A highly reliable semiconductor device that includes a transistor including an oxide semiconductor is provided. In a manufacturing process of a semiconductor device that includes a bottom-gate transistor including an oxide semiconductor, an insulating film which is in contact with an oxide semiconductor film is subjected to dehydration or dehydrogenation treatment by heat treatment and oxygen doping treatment in this order. The insulating film which is in contact with the oxide semiconductor film refers to a gate insulating film provided under the oxide semiconductor film and an insulating film which is provided over the oxide semiconductor film and functions as a protective insulating film. The gate insulating film and/or the insulating film are/is subjected to dehydration or dehydrogenation treatment by heat treatment and oxygen doping treatment in this order.

Abstract: Provided are methods of forming an ion implanted region in a semiconductor device. The methods comprise: (a) providing a semiconductor substrate having a plurality of regions to be ion implanted; (b) forming a photoresist pattern on the semiconductor substrate, wherein the photoresist pattern is formed from a chemically amplified photoresist composition comprising a matrix polymer having acid labile groups, a photoacid generator and a solvent; (c) coating a descumming composition over the photoresist pattern, wherein the descumming composition comprises: a matrix polymer; a free acid; and a solvent; (d) heating the coated semiconductor substrate; (e) contacting the coated semiconductor substrate with a rinsing agent to remove residual descumming composition and scum from the substrate; and (f) ion implanting the plurality of regions of the semiconductor substrate using the photoresist pattern as an implant mask. The methods find particular applicability in the manufacture of semiconductor devices.

Abstract: A method of manufacturing a MOSFET includes the steps of preparing a substrate with an epitaxial growth layer made of silicon carbide, performing ion implantation into the substrate with the epitaxial growth layer, forming a protective film made of silicon nitride on the substrate with the epitaxial growth layer into which the ion implantation was performed, and heating the substrate with the epitaxial growth layer on which the protective film was formed to a temperature range of 1600° C. or more in an atmosphere containing gas including a nitrogen atom.

Abstract: In aspects of the invention, an n-type epitaxial layer that forms an n? type drift layer is formed on the upper surface of an n-type semiconductor substrate formed by being doped with a high concentration of antimony. A p-type anode layer is formed on a surface of the n? type drift layer. An n-type contact layer is formed with an impurity concentration in the same region as the impurity concentration of the n-type cathode layer, or higher than the impurity concentration of the n-type cathode layer, on the lower surface of the n-type cathode layer. A cathode electrode is formed so as to be in contact with the n-type contact layer. The n-type contact layer is doped with phosphorus and, without allowing complete recrystallization using a low temperature heat treatment of 500° C. or less, lattice defects are allowed to remain.

Abstract: According to one embodiment, a semiconductor device includes a substrate, a first stacked body, a memory film, a first channel body, a second stacked body, a gate insulating film and a second channel body. A step part is formed between a side face of the select gate and the second insulating layer. A film thickness of a portion covering the step part of the second channel body is thicker than a film thickness of a portion provided between the second insulating layers of the second channel body.

Abstract: A description is given of a method for doping a semiconductor body, and a semiconductor body produced by such a method. The method comprises irradiating the semiconductor body with protons and irradiating the semiconductor body with electrons. After the process of irradiating with protons and after the process of irradiating with electrons, the semiconductor body is subjected to heat treatment in order to attach the protons to vacancies by means of diffusion.

Abstract: The invention provides a semiconductor device with a junction termination extension structure on a mesa and a method of fabricating the same. The device comprises: a type-I semiconductor substrate having a first surface and a second surface; a type-I epitaxial layer disposed on the first surface; at least one depression disposed on the type-I epitaxial layer; a mesa-type junction termination extension structure surrounding the at least one depression wherein the mesa-type junction termination extension structure is of type-II; and at least one semiconductor component formed one the depression.

Abstract: A method for fabricating an NMOS transistor includes providing a substrate; forming a gate dielectric layer structure on the substrate and forming a gate electrode on the gate dielectric layer structure. The method further includes performing a fluorine ion implantation below the gate dielectric layer and an annealing process in an atmosphere comprising hydrogen or hydrogen plasma. The method also includes forming a source region and a drain region on both sides of the gate electrode before or after the fluorine ion implantation.

Abstract: To provide a temperature control method capable of equivalently maintaining qualities of substrates even when treated substrates are continuously carried in a treatment container in the case in which activation annealing treatment is performed by an electron impact heating method.

Abstract: According to one embodiment, the manufacturing method for the semiconductor device according to the embodiment includes carrying out ion implantation to the semiconductor layer and forming an amorphous layer on the surface of the semiconductor layer, and a heat treatment process using microwave annealing at a temperature higher than or equal to 200° C. and lower than or equal to 700° C. and single crystallizes the amorphous layer.

Abstract: The present invention relates generally to methods for high throughput and controllable creation of high performance semiconductor substrates for use in devices such as high sensitivity photodetectors, imaging arrays, high efficiency solar cells and the like, to semiconductor substrates prepared according to the methods, and to an apparatus for performing the methods of the invention.

Abstract: Ions of silicon are implanted into source/drain regions in a semiconductor wafer to amorphize an ion implantation region in the semiconductor wafer. A nickel film is deposited on the amorphized ion implantation region. First irradiation from a flash lamp is performed on the semiconductor wafer with the nickel film deposited thereon to increase the temperature of a front surface of the semiconductor wafer from a preheating temperature to a target temperature for a time period in the range of 1 to 20 milliseconds. Subsequently, second irradiation from the flash lamp is performed to maintain the temperature of the front surface of the semiconductor wafer within a ±25° C. range around the target temperature for a time period in the range of 1 to 100 milliseconds. This causes nickel silicide to grow preferentially in a direction perpendicular to the semiconductor wafer.

Abstract: An integrated circuit includes an NMOS SCR in which a p-type body well of the NMOS transistor provides a base layer for a vertical NPN layer stack. The base layer is formed by implanting p-type dopants using an implant mask which has a cutout mask element over the base area, so as to block the p-type dopants from the base area. The base layer is implanted concurrently with p-type body wells under NMOS transistors in logic components in the integrated circuit. Subsequent anneals cause the p-type dopants to diffuse into the base area, forming a base with a lower doping density that adjacent regions of the body well of the NMOS transistor in the NMOS SCR. The NMOS SCR may have a symmetric transistor, a drain extended transistor, or may be a bidirectional NMOS SCR with a symmetric transistor integrated with a drain extended transistor.

Abstract: A method for transferring InP film onto a stiffener substrate, the method including: providing a structure comprising an InP surface layer and an underlying doped thin InP layer; implanting hydrogen ions through the surface layer so as to create a weakened plane in the doped thin layer, delimiting a film comprising the surface layer; placing the surface layer in close contact with a stiffener substrate; and applying heat treatment to obtain splitting at the weakened plane and transfer of the film onto the stiffener substrate.

Abstract: According to one embodiment, a semiconductor device includes a substrate, a first stacked body, a memory film, a first channel body, a second stacked body, a gate insulating film and a second channel body. A step part is formed between a side face of the select gate and the second insulating layer. A film thickness of a portion covering the step part of the second channel body is thicker than a film thickness of a portion provided between the second insulating layers of the second channel body.

Abstract: A method of forming a transistor device includes implanting a diffusion inhibiting species in a semiconductor-on-insulator substrate comprising a bulk substrate, a buried insulator layer, and a semiconductor-on-insulator layer, the semiconductor-on-insulator substrate having one or more gate structures formed thereon such that the diffusion inhibiting species is disposed in portions of the semiconductor-on-insulator layer corresponding to a channel region, and disposed in portions of the buried insulator layer corresponding to source and drain regions. A transistor dopant species is introduced in the source and drain regions. An anneal is performed so as to diffuse the transistor dopant species in a substantially vertical direction while substantially preventing lateral diffusion of the transistor dopant species into the channel region.

Abstract: Multiple transistor types are formed in a common epitaxial layer by differential out-diffusion from a doped underlayer. Differential out-diffusion affects the thickness of a FET channel, the doping concentration in the FET channel, and distance between the gate dielectric layer and the doped underlayer. Differential out-diffusion may be achieved by differentially applying a dopant migration suppressor such as carbon; differentially doping the underlayer with two or more dopants having the same conductivity type but different diffusivities; and/or differentially applying thermal energy.

Abstract: Methods of improving the anti-reflection properties of one or more dielectric layers and reducing surface recombination of generated carriers of a solar cell are disclosed. In some embodiments, dopants are introduced into the dielectric layers to improve their anti-reflection properties. In other embodiments, species are introduced into the dielectric layers to create electrical fields which repel the minority carriers away from the surface and toward the contacts. In another embodiment, mobiles species are introduced to the anti-reflective coating, which cause carrier to be repelled from the surface of the solar cell. By creating a barrier at the surface of the solar cell, undesired recombination at the surface may be reduced.

Abstract: A process for forming diffused region less than 20 nanometers deep with an average doping dose above 1014 cm?2 in an IC substrate, particularly LDD region in an MOS transistor, is disclosed. Dopants are implanted into a source dielectric layer using gas cluster ion beam (GCIB) implantation, molecular ion implantation or atomic ion implantation resulting in negligible damage in the IC substrate. A spike anneal or a laser anneal diffuses the implanted dopants into the IC substrate. The inventive process may also be applied to forming source and drain (S/D) regions. One source dielectric layer may be used for forming both NLDD and PLDD regions.

Abstract: Field effect transistors and method for forming filed effect transistors. The field effect transistors including: a gate dielectric on a channel region in a semiconductor substrate; a gate electrode on the gate dielectric; respective source/drains in the substrate on opposite sides of the channel region; sidewall spacers on opposite sides of the gate electrode proximate to the source/drains; and wherein the sidewall spacers comprise a material having a dielectric constant lower than that of silicon dioxide and capable of absorbing laser radiation.

Abstract: According to one embodiment, a semiconductor device includes a substrate, a first stacked body, a memory film, a first channel body, a second stacked body, a gate insulating film and a second channel body. A step part is formed between a side face of the select gate and the second insulating layer. A film thickness of a portion covering the step part of the second channel body is thicker than a film thickness of a portion provided between the second insulating layers of the second channel body.

Abstract: A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.

Abstract: A spin-on formulation that is useful in stripping an ion implanted photoresist is provided that includes an aqueous solution of a water soluble polymer containing at least one acidic functional group, and at least one lanthanide metal-containing oxidant. The spin-on formulation is applied to an ion implanted photoresist and baked to form a modified photoresist. The modified photoresist is soluble in aqueous, acid or organic solvents. As such one of the aforementioned solvents can be used to completely strip the ion implanted photoresist as well as any photoresist residue that may be present. A rinse step can follow the stripping of the modified photoresist.

Abstract: A method of forming a low resistance contact structure in a semiconductor device includes forming a doped semiconductor region in a semiconductor substrate; forming a deep level impurity region at an upper portion of the doped semiconductor region; activating dopants in both the doped semiconductor region and the deep level impurity region by annealing; and forming a metal contact over the deep level impurity region so as to create a metal-semiconductor interface therebetween.

Abstract: A semiconductor device is disclosed. In a surface layer of a front surface of an n-type semiconductor substrate, an anode layer is provided in an element activation portion and an annular p-type guard ring and an n-type high-concentration surface region are provided in an annular termination breakdown voltage region which surrounds the outer circumference of the anode layer. The impurity concentration of the n-type high-concentration surface region is higher than that of the semiconductor substrate and is lower than that of the p-type guard ring. The depth of the n-type high-concentration surface region is less than that of the guard ring. The anode layer and the guard ring are formed while the oxygen concentration of the semiconductor substrate is set to be equal to or more than 1×1016/cm3 and equal to or less than 1×1018/cm3.

Abstract: A pulsed-laser anneal technique includes performing an implant of a selected region of a semiconductor wafer. A co-constituent implant of the selected region is performed, and the pulsed-laser anneal of the selected region performed. A pre-amorphizing implant of the selected region can also be performed. In one embodiment, the implant of the selected region is performed as an insitu implant. In another embodiment, the co-constituent implant is performed as an insitu non-donor implant. In yet another embodiment, the implant and the co-constituent implant of the selected region are performed as an insitu donor and co-constituent implant.

Abstract: A method of manufacturing a semiconductor device includes performing heat treatment for activating impurities of a transistor having a gate electrode over a gate insulating film with a higher relative permittivity than a silicon oxynitride film or a silicon oxide film. In the heat treatment, a first heat treatment, in which a wafer surface is heated at a temperature of 800 to 1000° C. in 5 to 50 milliseconds by low-output flash lamp annealing or laser annealing, and a second heat treatment, in which the wafer surface is heated at a temperature equal to or more than of 1100° C. in 0.1 to 10 milliseconds by flash lamp annealing or laser annealing with a higher output than in the first heat treatment, are performed in this order.

Abstract: A method for fabricating a semiconductor device includes ion-implanting germanium into a monocrystalline silicon-containing substrate; forming a gate oxide layer over a surface of the monocrystalline silicon-containing substrate and forming, under the gate oxide layer, a germanium-rich region in which the germanium is concentrated, by performing a plasma oxidation process; and crystallizing the germanium-rich region by performing an annealing process.

Abstract: Silicon-on-insulator (SOI) structures and related methods of forming such structures. In one case, a method includes providing a silicon-on-insulator (SOI) handle substrate having: a substantially uniform resistivity profile along a depth of the handle substrate; and an interstitial oxygen (Oi) concentration of less than approximately 10 parts per million atoms (ppma). The method further includes counter-doping a surface region of the handle, causing the surface region to have a resistivity greater than approximately 3 kOhm-cm, and joining the surface region of the handle substrate with a donor wafer.

Abstract: Disclosed herein are various methods of forming stressed silicon-carbon areas in an NMOS transistor device. In one example, a method disclosed herein includes forming a layer of amorphous carbon above a surface of a semiconducting substrate comprising a plurality of N-doped regions and performing an ion implantation process on the layer of amorphous carbon to dislodge carbon atoms from the layer of amorphous carbon and to drive the dislodged carbon atoms into the N-doped regions in the substrate.

Abstract: In according with the present invention, a semiconductor device is formed as follows. A contact insulation layer is deposited on the top surface of said silicon layer. A contact mask is applied and following with a dry oxide etching to remove the contact insulation layer from contact open areas. The silicon layer is implanted with a source dopant through the contact open areas and the source dopant is diffused to form source regions, thereby a source mask is saved. A dry silicon etch is carried out to form trenched source-body contacts in the contact open areas, penetrating through the source regions and extending into the body regions.

Abstract: A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an analog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.

Abstract: Methods of forming a passivation layer on a workpiece are disclosed. These methods utilize a SiC forming polymer to form the passivation layer. In addition, while the polymer is being heated to form SiC, a second result, such as annealing of the underlying workpiece, or firing of the metal contacts is achieved. For example, the workpiece may be implanted prior to coating it with the polymer. When the workpiece is heated, SiC is formed and the workpiece is annealed. In another embodiment, a workpiece is coating with the SiC forming polymer and metal pattern is applied to the polymer. The firing of workpiece causes the metal contacts to form and also forms SiC on the workpiece.

Abstract: A semiconductor device having a trench gate structure is formed by self alignment. The manufacturing method of the semiconductor device includes: forming a control electrode in an interior of trenches, etching a semiconductor layer between adjacent trenches to form an opening having a depth that is about level with an upper end of the control electrode with a portion of the semiconductor layer remaining between the opening and the control electrode, forming a first semiconductor region of the second conductive type from the surface of the semiconductor layer to a depth above the lower end of the control electrode, forming a single crystallized conductive layer from the first semiconductor region and the portion of the semiconductor layer, and forming a second semiconductor region, the second semiconductor region including the portion of the semiconductor layer and the single crystallized portion of the conductive layer.

Abstract: A method for producing an integrated circuit, including, in this order: a) producing at least one MOS electronic circuit and/or at least one level of electrical interconnections on a substrate; b) uniformly implantating dopants in at least a portion of a layer of crystalline semiconductor; c) thermally activating the dopants implanted in the portion of the crystalline semiconductor layer; d) rigidly connecting the crystalline semiconductor layer to the substrate; and e) producing at least one junctionless depletion-mode FET device including a part of the portion of the crystalline semiconductor layer.

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device provide improved control over a shape of a trench for forming the source and drain features of integrated circuit device, by forming a second doped region in a first doped region and removing the first and the second doped regions by a first and a second wet etching processes.

Abstract: Silicon-on-insulator (SOI) structures and related methods of forming such structures. In one case, a method includes providing a silicon-on-insulator (SOI) handle substrate having: a substantially uniform resistivity profile along a depth of the handle substrate; and an interstitial oxygen (Oi) concentration of less than approximately 10 parts per million atoms (ppma). The method further includes counter-doping a surface region of the handle, causing the surface region to have a resistivity greater than approximately 3 kOhm-cm, and joining the surface region of the handle substrate with a donor wafer.

Abstract: In an embodiment of the present invention, a semiconductor layer having regions into which a p-type impurity, an n-type impurity and a (p+n) impurity are respectively introduced is formed as a surface layer by being heat-treated. An impurity segregation layer on these regions is removed, and a film of a metallic material is thereafter formed on the regions and is heat-treated, thereby forming a silicide film on the semiconductor layer. In another embodiment, an impurity is introduced into the impurity segregation layer, and a film of a metallic material is thereafter formed on the impurity segregation layer and is heat-treated to form a silicide film.

Abstract: A vertical semiconductor device with improved junction profile and a method of manufacturing the same are provided. The vertical semiconductor device includes a pillar vertically extended from a surface of a semiconductor substrate, a silicon layer formed in a bit line contact region of one sidewall of the pillar, and a junction region formed within a portion of the pillar contacting with the silicon layer.

Abstract: A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.

Abstract: A method of manufacturing flash memory device is provided and includes the following steps. First, a substrate is provided. Then, a stacked gate structure is formed on the substrate. Subsequently, a first oxide layer is formed on the stacked gate structure. Following that, a nitride spacer is formed on the first oxide layer, wherein a nitrogen atom-introducing treatment is performed after the forming of the first oxide layer and before the forming of the nitride spacer. Accordingly, the nitrogen atom-introducing treatment of the presentation invention can improve the data retention reliability of the flash memory device.

Abstract: An integrated circuit containing a dual drift layer extended drain MOS transistor with an upper drift layer contacting a lower drift layer along at least 75 percent of a common length of the two drift layers. An average doping density in the lower drift layer is between 2 and 10 times an average doping density in the upper drift layer. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, using an epitaxial process. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, on a monolithic substrate.

Abstract: A method of manufacturing a semiconductor device that includes a semiconductor substrate is provided. The method includes: exposing a photoresist coated on the semiconductor substrate using a photomask including a plurality of regions having different light transmittances; developing the photoresist to form a resist pattern including a plurality of regions having different thicknesses that depend on an exposure amount of the photoresist; and implanting impurity ions into the semiconductor substrate through the plurality of regions of the resist pattern having different thicknesses to form a plurality of impurity regions whose depths from a surface of the semiconductor substrate to peak positions are different from each other. The depths to the peak positions depend on the thickness of the resist pattern through which the implanted impurity ions pass.

Abstract: Methods for enhancing strain in an integrated circuit are provided. Embodiments of the invention include using a localized implant into an active region prior to a gate etch. In another embodiment, source/drain regions adjacent to the gates are recessed to allow the strain to expand to full potential. New source/drain regions are allowed to grow back to maximize stress in the active region.

Abstract: A method for making a thin-film structure includes a thin film stabilized on a substrate. The structure of the thin film is defined by a material which includes at least one first chemical species. The method includes a step of inputting particles of the first chemical species into the thin film so as to compensate for the flow of vacancies from the surface of the film.