Into Polycrystalline Region Patents (Class 438/532)
  • Patent number: 9704758
    Abstract: An approach to forming a semiconductor structure with improved negative bias temperature instability includes diffusing fluorine atoms into a semiconductor structure by an anneal in a fluorine containing gas. The approach includes removing a pFET work function metal layer from an area above an nFET wherein the area above the nFET includes at least the area over the nFET. Additionally, the approach includes depositing a layer of nFET work function metal on a remaining portion of the pFET work function metal and depositing a gate metal over the nFET work function metal layer. Furthermore, the method includes performing an anneal in a reducing environment followed by a high temperature anneal.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: July 11, 2017
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Siddarth A. Krishnan
  • Patent number: 9513172
    Abstract: An infrared detector useful in, e.g., infrared cameras, includes a substrate having an array of infrared detectors and a readout integrated circuit interconnected with the array disposed on an upper surface thereof, for one or more embodiments. A generally planar window is spaced above the array, the window being substantially transparent to infrared light. A mesa is bonded to the window. The mesa has closed marginal side walls disposed between an outer periphery of a lower surface of the window and an outer periphery of the upper surface of the substrate and defines a closed cavity between the window and the array that encloses the array. A solder seal bonds the mesa to the substrate so as to seal the cavity.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: December 6, 2016
    Assignee: FLIR Systems, Inc.
    Inventors: Gregory A. Carlson, Alex Matson, Andrew Sharpe, Davey Beard, Paul Schweikert, Robert Simes
  • Patent number: 9484425
    Abstract: According to one disclosed embodiment, an electrical contact for use on a semiconductor device comprises an electrode stack including a plurality of metal layers and a capping layer formed over the plurality of metal layers. The capping layer comprises a refractory metal nitride. In one embodiment, a method for fabricating an electrical contact for use on a semiconductor device comprises forming an electrode stack including a plurality of metal layers over the semiconductor device, and depositing a refractory metal nitride capping layer of the electrode stack over the plurality of metal layers. The method may further comprise annealing the electrode stack at a temperature of less than approximately 875° C. In some embodiments, the method may additionally include forming one of a Schottky metal layer and a gate insulator layer between the electrode stack and the semiconductor device.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: November 1, 2016
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Sadiki Jordan
  • Patent number: 9111861
    Abstract: An embodiment of the current disclosure includes a method of providing a substrate, forming a polysilicon layer over the substrate, forming a first photoresist layer on the polysislicon layer, creating a first pattern on the first photoresist layer, wherein some portions of the polysilicon layer are covered by the first photoresist layer and some portions of the polysilicon layer are not covered by the first photoresist layer, implanting ions into the portions of the polysilicon layer that are not covered by the first photoresist layer, removing the first photoresist layer from the polysilicon layer, forming a second photoresist layer on the polysilicon layer, creating a second pattern on the second photoresist layer, and implanting ions into the portions of the polysilicon layer that are not covered by the second photoresist layer, removing the second photoresist layer from the polysilicon layer, and removing portions of the polysilicon layer using an etchant.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: August 18, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Yen Hsieh, Ming-Ching Chang, Chia-Wei Chang, Chao-Cheng Chen, Chun-Hung Lee, Dai-Lin Wu
  • Patent number: 9023695
    Abstract: The present disclosure provides a method of semiconductor device fabrication including forming a mandrel on a semiconductor substrate is provided. The method continues to include oxidizing a region the mandrel to form an oxidized region, wherein the oxidized region abuts a sidewall of the mandrel. The mandrel is then removed from the semiconductor substrate. After removing the mandrel, the oxidized region is used to pattern an underlying layer formed on the semiconductor substrate.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: May 5, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chao Chiu, Nian-Fuh Cheng, Chen-Yu Chen, Ming-Feng Shieh, Chih-Ming Lai, Wen-Chun Huang, Ru-Gun Lin
  • Patent number: 8921181
    Abstract: Methods for forming an electronic device having a fluorine-stabilized semiconductor substrate surface are disclosed. In an exemplary embodiment, a layer of a high-? dielectric material is formed together with a layer containing fluorine on a semiconductor substrate. Subsequent annealing causes the fluorine to migrate to the surface of the semiconductor (for example, silicon, germanium, or silicon-germanium). A thin interlayer of a semiconductor oxide may also be present at the semiconductor surface. The fluorine-containing layer can comprise F-containing WSix formed by ALD from WF6 and SiH4 precursor gases. A precise amount of F can be provided, sufficient to bind to substantially all of the dangling semiconductor atoms at the surface of the semiconductor substrate and sufficient to displace substantially all of the hydrogen atoms present at the surface of the semiconductor substrate.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: December 30, 2014
    Assignee: Intermolecular, Inc.
    Inventor: Dipankar Pramanik
  • Patent number: 8890279
    Abstract: A trench Schottky rectifier device includes a substrate having a first conductivity type, a plurality of trenches formed in the substrate, and an insulating layer formed on sidewalls of the trenches. The trenches are filled with conductive structure. There is an electrode overlying the conductive structure and the substrate, and thus a Schottky contact forms between the electrode and the substrate. A plurality of embedded doped regions having a second conductivity type are formed in the substrate and located under the trenches. Each doped region and the substrate form a PN junction to pinch off current flowing toward the Schottky contact so as to suppress current leakage.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: November 18, 2014
    Assignee: PFC Device Corp.
    Inventors: Kou-Liang Chao, Mei-Ling Chen, Tse-Chuan Su, Hung-Hsin Kuo
  • Patent number: 8846508
    Abstract: Methods to implant ions into the sidewall of a three dimensional high aspect ratio feature, such as a trench or via, are disclosed. The methods utilize a phenomenon known as knock-in, which causes a first species of ions, already disposed in the fill material, to become implanted in the sidewall when these ions are struck by ions of a second species being implanted into the fill material. In some embodiments, these first species and second species have similar masses to facilitate knock-in. In some embodiments, the entire hole is not completely filled with fill material. Rather, some fill material is deposited, an ion implant is performed to cause knock-in to the sidewall adjacent to the deposited fill material, and the process is repeated until the hole is filled.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: September 30, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Jonathan Gerald England, Andrew M. Waite, Simon Ruffell
  • Patent number: 8637385
    Abstract: According to one exemplary embodiment, a method for fabricating a high voltage durability transistor comprises forming a gate over a gate oxide layer formed over a substrate, aligning an exposure mask with the gate, and selectively blocking exposure of the gate during gate implant doping, by exposure shields formed in the exposure mask, thereby producing the high voltage durability transistor. In one embodiment, an exemplary high voltage durability transistor comprises a gate formed over a gate oxide layer, the gate oxide layer being situated over a semiconductor substrate, where the gate has a reduced doping implant due to selective implant blocking provided by exposure shields formed in an exposure mask. The selective implant blocking results in an enhanced dielectric barrier so as to produce a high voltage durability transistor. The enhanced dielectric barrier has a depletion region with an increased thickness.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: January 28, 2014
    Assignee: Broadcom Corporation
    Inventors: Akira Ito, Henry KuoShun Chen
  • Patent number: 8623748
    Abstract: A method for reducing the effective thickness of a gate oxide using nitrogen implantation and anneal subsequent to dopant implantation and activation is provided. More particularly, the present invention provides a method for fabricating semiconductor devices, for example, transistors, which include a hardened gate oxide and which may be characterized by a relatively large nitrogen concentration at the polysilicon/gate oxide interface and a relatively small nitrogen concentration within the gate oxide and at the gate oxide/substrate interface. Additionally, the present invention provides a method for fabricating a semiconductor device having a metal gate strap (e.g., a metal silicide layer) disposed over the polysilicon layer thereof, which device includes a hardened gate oxide and which may be characterized by a relatively large nitrogen concentration at the silicide/polysilicon interface to substantially prevent cross-diffusion.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: January 7, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Zhongze Wang
  • Patent number: 8618626
    Abstract: A trench Schottky rectifier device includes a substrate having a first conductivity type, a plurality of trenches formed in the substrate, and an insulating layer formed on sidewalls of the trenches. The trenches are filled with conductive structure. There is an electrode overlying the conductive structure and the substrate, and thus a Schottky contact forms between the electrode and the substrate. A plurality of embedded doped regions having a second conductivity type are formed in the substrate and located under the trenches. Each doped region and the substrate form a PN junction to pinch off current flowing toward the Schottky contact so as to suppress current leakage.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: December 31, 2013
    Assignee: PFC Device Corporation
    Inventors: Kou-Liang Chao, Mei-Ling Chen, Tse-Chuan Su, Hung-Hsin Kuo
  • Publication number: 20130149849
    Abstract: An integrated circuit containing a PMOS transistor may be formed by implanting boron in the p-channel source drain (PSD) implant step at a dose consistent with effective channel length control, annealing the PSD implant, and subsequently concurrently implanting boron into a polysilicon resistor with a zero temperature coefficient of resistance using an implant mask which also exposes the PMOS transistor, followed by a millisecond anneal.
    Type: Application
    Filed: December 10, 2012
    Publication date: June 13, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: TEXAS INSTRUMENTS INCORPORATED
  • Publication number: 20130122695
    Abstract: A trench Schottky diode and its manufacturing method are provided. The trench Schottky diode includes a semiconductor substrate having therein a plurality of trenches, a gate oxide layer, a polysilicon structure, a guard ring and an electrode. At first, the trenches are formed in the semiconductor substrate by an etching step. Then, the gate oxide layer and the polysilicon structure are formed in the trenches and protrude above a surface of the semiconductor substrate. The guard ring is formed to cover a portion of the resultant structure. At last, the electrode is formed above the guard ring and the other portion not covered by the guard ring. The protruding gate oxide layer and the protruding polysilicon structure can avoid cracks occurring in the trench structure.
    Type: Application
    Filed: January 7, 2013
    Publication date: May 16, 2013
    Applicant: PFC DEVICE CORP.
    Inventor: PFC DEVICE CORP.
  • Patent number: 8405088
    Abstract: A thin film transistor includes a substrate, a buffer layer on the substrate, a semiconductor layer on the buffer layer, source and drain electrodes directly on the semiconductor layer, each of the source and drain electrodes including at least one hole therethrough, a gate insulating layer on the substrate, and a gate electrode on the gate insulating layer and corresponding to the semiconductor layer.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: March 26, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ji-Su Ahn, Hoon-Kee Min
  • Patent number: 8361866
    Abstract: A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: January 29, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Yi Lee, Harry Chuang, Ping-Wei Wang, Kong-Beng Thei
  • Publication number: 20120289036
    Abstract: The invention generally relates to pre-implant and post-implant treatments to promote the retention of dopants near the surface of an implanted substrate. The pre-implant treatments include forming a plasma from an inert gas and implanting the inert gas into the substrate to render an upper portion of the substrate amorphous. The post-implant treatment includes forming a passivation layer on the upper surface of the substrate after doping the substrate in order to retain the dopant during a subsequent activation anneal.
    Type: Application
    Filed: April 17, 2012
    Publication date: November 15, 2012
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Kartik Santhanam, Manoj Vellaikal, Yen B. Ta, Matthew D. Scotney-Castle, Peter I. Porshnev
  • Patent number: 8288262
    Abstract: A method for fabricating a semiconductor device is described. A polysilicon layer is formed on a substrate. The polysilicon layer is doped with an N-type dopant. A portion of the polysilicon layer is then removed to form a plurality of dummy patterns. Each dummy pattern has a top, a bottom, and a neck arranged between the top and the bottom, where the width of the neck is narrower than that of the top. A dielectric layer is formed on the substrate to cover the substrate disposed between adjacent dummy patterns, and the top of each dummy pattern is exposed. Thereafter, the dummy patterns are removed to form a plurality of trenches in the dielectric layer. A plurality of gate structures is formed in the trenches, respectively.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: October 16, 2012
    Assignee: United Microelectronics Corp.
    Inventor: Chun-Hsien Lin
  • Patent number: 8247286
    Abstract: One embodiment of inventive concepts exemplarily described herein may be generally characterized as a semiconductor device including an isolation region within a substrate. The isolation region may define an active region. The active region may include an edge portion that is adjacent to an interface of the isolation region and the active region and a center region that is surrounded by the edge portion. The semiconductor device may further include a gate electrode on the active region and the isolation region. The gate electrode may include a center gate portion overlapping a center portion of the active region, an edge gate portion overlapping the edge portion of the active region, and a first impurity region of a first conductivity type within the center gate portion and outside the edge portion. The semiconductor device may further include a gate insulating layer disposed between the active region and the gate electrode.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: August 21, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dong-Ryul Chang
  • Patent number: 8236603
    Abstract: A semiconductor structure may include a polycrystalline substrate comprising a metal, the polycrystalline substrate having substantially randomly oriented grains, as well as a buffer layer disposed thereover. The buffer layer may comprise a plurality of islands having an average island spacing therebetween. A polycrystalline semiconductor layer is disposed over the buffer layer.
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: August 7, 2012
    Assignees: Solexant Corp., Rochester Institute of Technology
    Inventors: Leslie G. Fritzemeier, Ryne P. Raffaelle, Christopher Leitz
  • Patent number: 8222119
    Abstract: A method for temperature control during a process of cleaving a plurality of free-standing thick films from a bulk material includes clamping a bulk material using a mechanical clamp device adapted to engage the bottom region of the bulk material through a seal with a planar surface of a stage to form a cavity with a height between the bottom region and the planar surface. The planar surface includes a plurality of gas passageways allowing a gas filled in the cavity with adjustable pressure. The method also includes maintaining the temperature of the surface region by processing at least input data and executing a control scheme utilizing at least one or more of: particle bombardment to heat the surface region; radiation to heat the surface region; and gas-assisted conduction between the bottom region and the stage.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: July 17, 2012
    Assignee: Silicon Genesis Corporation
    Inventor: Francois J. Henley
  • Publication number: 20120088357
    Abstract: A method of manufacturing a semiconductor device is disclosed. The method forms a semiconductor device including a workpiece structure having a first region and second region located adjacent to the first region formed therein. The first region includes a first pattern and the second region includes a second pattern having at least a greater pattern width or a smaller aspect ratio than the first pattern. The method includes forming the first pattern by providing a first film having a first contact angle at a top portion thereof and the second pattern by providing a second film having a second contact angle less than the first contact angle at a top portion thereof; cleaning the first and the second regions by a chemical liquid; rinsing the cleaned first and the second regions by a rinse liquid; and drying the rinsed first and the second regions.
    Type: Application
    Filed: September 21, 2011
    Publication date: April 12, 2012
    Inventors: Yoshihiro OGAWA, Tatsuhiko Koide, Shinsuke Kimura
  • Patent number: 8110454
    Abstract: A transistor comprises a source region of a first conductivity type and electrically communicating with a first semiconductor region. The transistor also comprises a drain region of the first conductivity type and electrically communicating with a second semiconductor region that differs from the first semiconductor region. An interface exists between the first semiconductor region and the second semiconductor region. The transistor also comprises a voltage tap region comprising at least a portion located in a position that is closer to the interface than the drain region. A mixed technology circuit is also described.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: February 7, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Sameer P. Pendharkar
  • Patent number: 8039377
    Abstract: Some embodiments include methods of forming capacitors. A first section of a capacitor may be formed to include a first storage node, a first dielectric material, and a first plate material. A second section of the capacitor may be formed to include a second storage node, a second dielectric material, and a second plate material. The first and second sections may be formed over a memory array region, and the first and second plate materials may be electrically connected to first and second interconnects, respectively, that extend to over a region peripheral to the memory array region. The first and second interconnects may be electrically connected to one another to couple the first and second plate materials to one another. Some embodiments include capacitor structures, and some embodiments include methods of forming DRAM arrays.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: October 18, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Todd Jackson Plum
  • Patent number: 8008171
    Abstract: Disclosed is a method of providing a poly-Si layer used in fabricating poly-Si TFT's or devices containing poly-Si layers. Particularly, a method utilizing at least one metal plate covering the amorphous silicon layer or the substrate, and applying RTA (Rapid Thermal Annealing) for light illuminating process, then the light converted into heat by the metal plate will further be conducted to the amorphous silicon layer to realize rapid thermal crystallization. Thus the poly-Si layer of the present invention is obtained.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: August 30, 2011
    Assignees: Tatung Company, Tatung University
    Inventors: Chiung-Wei Lin, Yi-Liang Chen
  • Patent number: 7981817
    Abstract: A production method for a semiconductor device includes providing a semiconductor substrate having semiconductor layer of a first conductivity type formed on a surface thereof; forming a first mask so as to cover a predetermined region of the semiconductor layer; (c) forming a well region of a second conductivity type by implanting impurity ions of the second conductivity type into the semiconductor layer having the first mask formed thereon; reducing the thickness of the first mask by removing a portion of the first mask; forming a second mask covering a portion of the well region by using photolithography; and forming a source region of the first conductivity type by implanting impurity ions of the first conductivity type into the semiconductor layer having the first mask with the reduced thickness and the second mask formed thereon.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: July 19, 2011
    Assignee: Panasonic Corporation
    Inventors: Koichi Hashimoto, Shin Hashimoto, Kyoko Egashira
  • Patent number: 7972947
    Abstract: In a method for fabricating a semiconductor element in a substrate, first implantation ions are implanted into the substrate, whereby micro-cavities are produced in a first partial region of the substrate. Furthermore, pre-amorphization ions are implanted into the substrate, whereby a second partial region of the substrate is at least partly amorphized, and whereby crystal defects are produced in the substrate. Furthermore, second implantation ions are implanted into the second partial region of the substrate. Furthermore, the substrate is heated, such that at least some of the crystal defects are eliminated using the second implantation ions. Furthermore, dopant atoms are implanted into the second partial region of the substrate, wherein the semiconductor element is formed using the dopant atoms.
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: July 5, 2011
    Assignees: Infineon Technologies AG, IMEC VZW.
    Inventors: Luis-Felipe Giles, Thomas Hoffmann, Chris Stapelmann
  • Patent number: 7906413
    Abstract: A structure and method of forming an abrupt doping profile is described incorporating a substrate, a first epitaxial layer of Ge less than the critical thickness having a P or As concentration greater than 5×1019 atoms/cc, and a second epitaxial layer having a change in concentration in its first 40 from the first layer of greater than 1×1019 P atoms/cc. Alternatively, a layer of SiGe having a Ge content greater than 0.5 may be selectively amorphized and recrystalized with respect to other layers in a layered structure. The invention overcomes the problem of forming abrupt phosphorus profiles in Si and SiGe layers or films in semiconductor structures such as CMOS, MODFET's, and HBT's.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: March 15, 2011
    Assignee: International Business Machines Corporation
    Inventors: Frank Cardone, Jack Oon Chu, Khalid EzzEldin Ismail
  • Patent number: 7888194
    Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device is provided. A first conductive type MOS transistor including a source/drain region using a semiconductor compound as major material is formed in a first region of a substrate. A second conductive type MOS transistor is formed in a second region of the substrate. Next, a pre-amorphous implantation (PAI) process is performed to amorphize a gate conductive layer of the second conductive type MOS transistor. Thereafter, a stress-transfer-scheme (STS) is formed on the substrate in the second region to generate a stress in the gate conductive layer. Afterwards, a rapid thermal annealing (RTA) process is performed to activate the dopants in the source/drain region. Then, the STS is removed.
    Type: Grant
    Filed: March 5, 2007
    Date of Patent: February 15, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Li-Shian Jeng, Cheng-Tung Huang, Shyh-Fann Ting, Wen-Han Hung, Kun-Hsien Lee, Meng-Yi Wu, Tzyy-Ming Cheng
  • Patent number: 7875518
    Abstract: A method for forming a semiconductor device includes, in order, consecutively depositing a gate insulating film and a silicon layer on a semiconductor substrate, implanting boron into the silicon layer, diffusing the boron by heat-treating the silicon layer, implanting phosphorous into the silicon layer, diffusing at least the phosphorous by heat-treating the silicon layer, and patterning the silicon layer by using a dry etching technique.
    Type: Grant
    Filed: May 20, 2009
    Date of Patent: January 25, 2011
    Assignee: Elpida Memory, Inc.
    Inventors: Satoru Yamada, Ryo Nagai
  • Patent number: 7833864
    Abstract: Embodiments prevent or substantially reduce diffusion of a P-type impurity into a channel region in a PMOS transistor having a dual gate. Some embodiments include forming a device isolation film on a semiconductor substrate, forming a channel impurity region in an active region of the semiconductor substrate, and forming a gate insulation layer including a silicon oxide layer and a silicon oxide nitride layer on the semiconductor substrate. Also, the embodiments can include forming a polysilicon layer containing an N-type impurity on the gate insulation layer, and forming a gate electrode by selectively ion-implanting a P-type impurity into the polysilicon layer formed in a PMOS transistor region of the circuit region. The embodiments further include forming a conductive metal layer and a gate upper insulation layer on the gate electrode, and forming a gate stack in a gate region.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: November 16, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Chul Oh, Wook-Je Kim, Nak-Jin Son, Se-Myeong Jang, Gyo-Young Jin
  • Patent number: 7825016
    Abstract: In a method for fabricating a semiconductor element in a substrate, micro-cavities are formed in the substrate. Furthermore, doping atoms are implanted into the substrate, whereby crystal defects are produced in the substrate. The substrate is heated, so that at least some of the crystal defects are eliminated using the micro-cavities, and the semiconductor element is formed using the doping atoms.
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: November 2, 2010
    Assignee: Infineon Technologies AG
    Inventor: Luis-Felipe Giles
  • Patent number: 7807513
    Abstract: Methods for manufacturing a semiconductor device are provided that reduces the thickness of an oxide layer formed on a polysilicon layer for bit line contacts. A reduced thickness oxide layer can prevent short circuits between adjoining bit lines. A reduced thickness oxide layer can also eliminate the need for overetching in a subsequent etching process, thereby preventing loss of an isolation layer in a peripheral region.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: October 5, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hyung Kyun Kim, Yong Soo Joung
  • Patent number: 7795121
    Abstract: A method for manufacturing a semiconductor device is provided, which includes forming a gate insulating film on a semiconductor substrate, forming a first layer on the gate insulating film, the first layer containing a first p-type impurity and, an amorphous or polycrystalline formed of Si1-xGex (0?x<0.25), subjecting the first layer to a first heat treatment wherein the first layer is heated for 1 msec or less at a temperature higher than 1100° C., forming a second layer on the first layer, the second layer containing a second p-type impurity and formed of amorphous silicon or polycrystalline silicon, the second p-type impurity having a smaller covalent bond radius than that of the first p-type impurity, and subjecting the second layer to a second heat treatment to heat the second layer at a temperature ranging from 800° C. to 1100° C.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: September 14, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsunehiro Ino, Akio Kaneko, Nobutoshi Aoki
  • Patent number: 7790588
    Abstract: A dual gate of a semiconductor device includes a semiconductor substrate divided into a cell region with a recessed gate forming area and a peripheral region with PMOS and NMOS forming areas; first and second conductive type SiGe layers, the first conductive type SiGe layer being formed over the cell region and the PMOS forming area of the peripheral region, and the second conductive type SiGe layer being formed over the NMOS forming area of the peripheral region; first and second conductive type polysilicon layers, the first conductive type polysilicon layer being formed over the first conductive type SiGe layer and the second conductive type polysilicon layer being formed over the second conductive type SiGe layer; and a metallic layer and a hard mask layer stacked over the first and second conductive type polysilicon layers.
    Type: Grant
    Filed: January 2, 2008
    Date of Patent: September 7, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Young Hoon Kim
  • Patent number: 7763531
    Abstract: The disclosure describes an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FETs.
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: July 27, 2010
    Assignee: International Business Machines Corporation
    Inventors: Wagdi W. Abadeer, Jeffrey S. Brown, Kiran V. Chatty, Robert J. Gauthler, Jr., Jed H. Rankin, William R. Tonti
  • Patent number: 7749874
    Abstract: A CMOS image sensor includes a pinned photodiode and a transfer gate that are formed using a thick mask that is self-aligned to at least one edge of the polysilicon gate structure to facilitate both the formation of a deep implant and to provide proper alignment between the photodiode implant and the gate. In one embodiment a drain side implant is formed concurrently with the deep n-type implant of the photodiode. After the deep implant, the mask is removed and a shallow p+ implant is formed to complete the photodiode. In another embodiment, the polysilicon is etched to define only a drain side edge, a shallow drain side implant is performed, and then a thick mask is provided and used to complete the gate structure, and is retained during the subsequent high energy implant. Alternatively, the high energy implant is performed prior to the shallow drain side implant.
    Type: Grant
    Filed: March 26, 2007
    Date of Patent: July 6, 2010
    Assignee: Tower Semiconductor Ltd.
    Inventors: Clifford I. Drowley, David Cohen, Assaf Lahav, Shai Kfir, Naor Inbar, Anatoly Sergienko, Vladimir Korobov
  • Patent number: 7696053
    Abstract: Embodiments relate to a semiconductor device that may include a gate stack formed on an upper portion of an active region in a semiconductor substrate, the gate stack including a gate insulating layer and a gate, a first shallow impurity region formed on both sides of the gate in the semiconductor substrate, a gate spacer layer formed on one side of the gate stack, and a second deep impurity region formed in the semiconductor substrate by using the gate spacer layer as a mask, in which the gate is formed by implanting p-type ions.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: April 13, 2010
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Tae Woo Kim
  • Patent number: 7687384
    Abstract: Provided is a method for fabricating a semiconductor device. In the method, a poly layer on a semiconductor substrate is etched to a predetermined depth. Ions are implanted into the poly layer at a predetermined angle. The poly layer is etched again to expose a portion of the semiconductor substrate. Therefore, stress is applied to the poly gate instead of the barrier layer, so that the barrier layer is not opened during contact etching because effects of the barrier layer thickness can be solved. Also, stress is applied to a poly gate directly contacting a channel region of the semiconductor substrate to allow tensile force caused by the stress of the poly gate to directly induce tensile force to the channel region, and thus increase mobility, so that device characteristics can be remarkably enhanced.
    Type: Grant
    Filed: July 13, 2007
    Date of Patent: March 30, 2010
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Jin Ha Park
  • Patent number: 7670885
    Abstract: A method of manufacturing a thin-film semiconductor device, including forming a crystallized region on a transparent insulating substrate, implanting an impurity into the crystallized region and an amorphous semiconductor layer to form a source diffusion region and a drain diffusion region in the crystallized region, subjecting the resultant structure to heat treatment, thereby not only activating the impurity implanted in the crystallized region and the amorphous semiconductor layer but also restoring crystallinity of only a portion of the amorphous semiconductor layer which is formed on the crystallized region to thereby turn the portion into a polycrystalline semiconductor layer, and subjecting the resultant surface to selective etching to thereby leave only the polycrystalline semiconductor layer and to remove the amorphous semiconductor layer formed on other regions, thereby forming, in a self-aligned manner, a stacked source diffusion layer and a stacked drain diffusion layer.
    Type: Grant
    Filed: February 5, 2009
    Date of Patent: March 2, 2010
    Assignee: Advanced LCD Technologies Development Center Co., Ltd.
    Inventor: Katsunori Mitsuhashi
  • Publication number: 20090325352
    Abstract: A transistor comprises a source region of a first conductivity type and electrically communicating with a first semiconductor region. The transistor also comprises a drain region of the first conductivity type and electrically communicating with a second semiconductor region that differs from the first semiconductor region. An interface exists between the first semiconductor region and the second semiconductor region. The transistor also comprises a voltage tap region comprising at least a portion located in a position that is closer to the interface than the drain region. A mixed technology circuit is also described.
    Type: Application
    Filed: September 2, 2009
    Publication date: December 31, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Sameer P. Pendharkar
  • Patent number: 7611976
    Abstract: Embodiments of the invention generally provide a method for forming a doped silicon-containing material on a substrate. In one embodiment, the method provides depositing a polycrystalline layer on a dielectric layer and implanting the polycrystalline layer with a dopant to form a doped polycrystalline layer having a dopant concentration within a range from about 1×1019 atoms/cm3 to about 1×1021 atoms/cm3, wherein the doped polycrystalline layer contains silicon or may contain germanium, carbon, or boron. The substrate may be heated to a temperature of about 800° C. or higher, such as about 1,000° C., during the rapid thermal anneal. Subsequently, the doped polycrystalline layer may be exposed to a laser anneal and heated to a temperature of about 1,000° C. or greater, such within a range from about 1,050° C. to about 1,400° C., for about 500 milliseconds or less, such as about 100 milliseconds or less.
    Type: Grant
    Filed: July 5, 2006
    Date of Patent: November 3, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Yi Ma, Khaled Z. Ahmed, Kevin L. Cunningham, Robert C. McIntosh, Abhilash J. Mayur, Haifan Liang, Mark Yam, Toi Yue Becky Leung, Christopher Olsen, Shulin Wang, Majeed Foad, Gary Eugene Miner
  • Patent number: 7611978
    Abstract: Provided is a method for forming a gate electrode of a semiconductor device which can form a gate electrode having a fine line width. Disclosed method steps include forming a gate oxide film, a polysilicon film for a gate electrode, and a first sacrificial layer on the entire surface of a semiconductor substrate and then forming an opening within the first sacrificial layer. The effective width of the hole is reduced, and an ion implantation layer is formed on the top surface of the polysilicon film in the region exposed through the hole. A gate electrode is formed under the ion implantation layer by using the ion implantation layer as a mask.
    Type: Grant
    Filed: May 20, 2008
    Date of Patent: November 3, 2009
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Eun Sang Cho
  • Publication number: 20090256172
    Abstract: A laser annealing method includes forming a nitrogen-doped layer on a semiconductor layer, the nitrogen-doped layer having a nitrogen concentration of at least 3×1020 atoms/cc, irradiating a first area of the nitrogen-doped layer in a low oxygen environment with a laser beam and irradiating a second area of the nitrogen-doped layer in a low oxygen environment with a laser beam, a part of the second area overlapping with the first area.
    Type: Application
    Filed: April 7, 2009
    Publication date: October 15, 2009
    Inventors: Kian Kiat Lim, Atsushi Nakamura, Kai Pheng Tan, Eng Soon Lim, Pho Ling Fu, Takaaki Kamimura
  • Patent number: 7601610
    Abstract: A process for the realization of a high integration density power MOS device includes the following steps of: providing a doped semiconductor substrate with a first type of conductivity; forming, on the substrate, a semiconductor layer with lower conductivity; forming, on the semiconductor layer, a dielectric layer of thickness comprised between 3000 and 13000 A (Angstroms); depositing, on the dielectric layer, a hard mask layer; masking the hard mask layer by means of a masking layer; etching the hard mask layers and the underlying dielectric layer for defining a plurality of hard mask portions to protect said dielectric layer; removing the masking layer; isotropically and laterally etching said dielectric layer forming lateral cavities in said dielectric layer below said hard mask portions; forming a gate oxide of thickness comprised between 150 and 1500 A (Angstroms) depositing a conductor material in said cavities and above the same to form a recess spacer, which is totally aligned with a gate structure c
    Type: Grant
    Filed: November 21, 2005
    Date of Patent: October 13, 2009
    Assignee: STMicroelectronics, S.r.L.
    Inventors: Giuseppe Arena, Giuseppe Ferla, Marco Camalleri
  • Patent number: 7598135
    Abstract: Provided is a method for fabricating CMOS image sensor. One method includes: preparing a semiconductor substrate in which a photodiode region and a transistor region are defined; sequentially forming an insulating layer and a conductive layer on an entire surface of the semiconductor substrate; forming a photoresist pattern for a gate electrode on the conductive layer; etching the conductive layer to a predetermined thickness using the photoresist pattern as a mask; performing an ion implantation process on the etched conductive layer to form a doped conductive layer; performing an oxidation process on the resultant structure including the doped conductive layer for oxidizing the doped conductive layer so as to form an oxide layer; and removing the oxide layer and the insulating layer disposed thereunder to define a gate electrode and a gate insulating layer.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: October 6, 2009
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Hee Sung Shim
  • Patent number: 7582537
    Abstract: A zener diode and methods for fabricating and packaging same are disclosed, whereby contact hole forming process exposing a diffusion layer is removed to enable to simplify the fabricating process, and the diffusion length not contacting the electrode line is determined by the crosswise length toward which the impurity is diffused to enable to reduce the zener impedance value. Furthermore, wet etching is used following the diffusion to remove the diffusion masks such that no damage is given to the diffusion layers to thereby enable to improve the zener diode characteristics.
    Type: Grant
    Filed: December 7, 2005
    Date of Patent: September 1, 2009
    Assignee: LG Electronics Inc.
    Inventors: Ki Chang Song, Geun Ho Kim
  • Patent number: 7575969
    Abstract: A high resistivity silicon for RF passive operation including CMOS structures with implanted CMOS wells and a buried layer under the wells formed by deep implants during well implantations.
    Type: Grant
    Filed: March 2, 2001
    Date of Patent: August 18, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Dirk Leipold
  • Patent number: 7560327
    Abstract: A method for fabricating a semiconductor device with a dual gate structure is provided. The method includes: forming a gate oxide layer over a substrate; forming a gate conductive layer over the gate oxide layer; forming an amorphous carbon layer over the gate conductive layer; forming a photosensitive pattern over the amorphous carbon layer; etching the amorphous carbon layer using the photosensitive pattern as an etch mask to form a patterned amorphous carbon layer; performing an ion implantation process using the patterned amorphous carbon layer as an ion implantation barrier to implant an impurity onto the gate conductive layer; removing the patterned amorphous carbon layer; and patterning the gate conductive layer to form a gate structure.
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: July 14, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kwang-Ok Kim, Young-Kyun Jung
  • Publication number: 20090170298
    Abstract: Processes and machines for producing large area sheets or films of crystalline, polycrystalline, or amorphous material are set forth; the production of such sheets being valuable for the manufacturing of solar photovoltaic cells, flat panel displays and the like. In one embodiment the surface of a rotating cylindrical workpiece (10) is implanted with an ion beam (30), whereby a layer of weakened material if formed below the surface, whereby sheet (20) may be detached and peeled off in an unrolling fashion, producing arbitrarily large, monolithic sheets. Optional annealing heater (40) may be used to improve the quality of the film. The sheet may also be optionally supported on a temporary or permanent handle (50) which may be rigid sheet such as glass, or a flexible sheet, such as a polymer film. Representative pinch roller (60) may assist in the lamination of handle (50) to sheet (20) before or after the point of separation of sheet (20) from workpiece (10).
    Type: Application
    Filed: February 18, 2008
    Publication date: July 2, 2009
    Applicant: VAXIS TECHNOLOGIES LLC
    Inventor: Adam Alexander Brailove
  • Patent number: 7550355
    Abstract: A boron ion stream may be used to implant ions, such as boron ions, into the sidewalls of an active area, such as an NFET active area. The boron ion stream has both vertical tilt and horizontal rotation components relative to the sidewalls and/or the silicon device, to provide a better line of sight onto the sidewalls. This may allow components of the silicon device to be moved closer together without unduly reducing the effectiveness of boron doping of NFET active area sidewalls, and provides an improved line of sight of a boron ion stream onto the sidewalls of an NFET active area prior to filling the surrounding trench with STI material.
    Type: Grant
    Filed: August 29, 2005
    Date of Patent: June 23, 2009
    Assignee: Toshiba America Electronic Components, Inc.
    Inventor: Yusuke Kohyama