Abstract: A linewidth measurement structure for determining linewidths of damascened metal lines formed in an insulator is provided. The linewidth measurement structure including: a damascene polysilicon line formed in the insulator, the polysilicon line having an doped region having a predetermined resistivity.

Abstract: The present invention relates to a method for fabricating a nitride read only memory (NROM), comprising: forming a doped polysilicon layer over a substrate, defining the doped polysilicon layer by using a patterned mask layer to form a plurality of doped polysilicon lines and expose a portion of the substrate. Afterwards, a thermal process is performed to form an oxide layer on the exposed substrate and sidewalls of the doped polysilicon lines. During the thermal process, the dopants are driven into the substrate to form a source/drain region, thus obtaining a plurality of bit lines including the doped polysilicon lines and the source/drain region. Following removal of the patterned mask layer, a self-aligned silicide layer is formed on the top surface of the bit lines. After removing the oxide layer, a silicon nitride stacked layer and a plurality of word lines are formed over the substrate.

Abstract: Within both a method for fabricating a bipolar transistor device and a method for fabricating a BiCMOS device there is: (1) formed contacting a base contact region a polysilicon base contact of a second polarity; and (2) formed contacting an emitter contact region a polysilicon emitter contact of a first polarity. Within the methods, there is then implanted into the polysilicon base contact a dose of a dopant of the second polarity while masking the polysilicon emitter contact. The methods provide for enhanced performance of the bipolar transistor device and the BiCMOS device.

Abstract: A process for formation of metal silicide on elements of an NMOS device and on elements of a PMOS device, wherein the metal silicide formed on elements of the PMOS device is thinner than the metal silicide simultaneously formed on elements of said NMOS device, has been developed. The process features the implantation of metal ions such as titanium, tantalum, vanadium, or rhenium, during the implantation procedure used for formation of the heavily doped P type source/drain region of the PMOS device. The presence of the implanted metal ions in PMOS regions retard the formation of metal silicide resulting in a thinner metal silicide layer on the heavily doped P type source/drain region, when compared to the thicker metal silicide counterparts simultaneously formed on elements of the NMOS device.

Abstract: A method is provided for processing a semiconductor topography. In particular, a method is provided for forming wells of opposite conductivity type using a single patterned layer. In addition, the method may include forming a silicon layer having first and second portions of opposite conductivity type. The formation of the silicon layer may include the use of the single patterned layer or an additional patterned layer. In addition, the method may include forming channel dopant regions within the wells of opposite conductivity type. The formation of such channel dopant regions may be incorporated into the method using the one or two patterned layers used for the formation of the wells and doped silicon layer. Such a method may include introducing impurities at varying energies and doses to compensate for the introduction of subsequent impurities. As such, the method may form a dual gate transistor pair, including n-channel and p-channel transistors.

Abstract: A method and structure for improving the gate activation of metal oxide semiconductor field effect transistor (MOSFET) structures are provided. The method of the present invention includes the steps of forming a structure having a plurality of patterned gate stacks atop a layer of gate dielectric material; forming a non-conformal film on the structure including the plurality of patterned gate stacks; blocking some of the plurality of patterned gate stacks with a first resist, while leaving other patterned gate stacks of said plurality unblocked; implanting first ions into the unblocked patterned gate stacks; removing the first resist and blocking the previously unblocked patterned gate stacks with a second resist; implanting second ions into the patterned gate stacks that are not blocked by the second resist; and removing the second resist and the non-conformal film.

Abstract: The invention provides a technology for reducing the direct contact resistance and for reducing the junction leak while maintaining the punch through margin. A semiconductor integrated circuit device is provided which comprises: a substrate; a transistor formed on the substrate, which comprises a source, a drain and a gate which controls a current flowing from said source to said drain; and a contact plug being electrically connected to at least one of the source and drain and made of a conductive material including a dopant. The contact plug is formed of at least a first layer and a second layer. The first layer contacts with one of the source and drain and is made of said material including the dopant of a first concentration. The second layer is formed of a layer of said material including the dopant of a second concentration, which is lower than the second concentration.

Abstract: A method of fabricating doped polysilicon structures comprising the following steps. A substrate is provided and an undoped polysilicon layer is formed over the substrate. The undoped polysilicon layer is patterned to form at least one undoped polysilicon structure within an N area and at least one undoped polysilicon structure within a P area. The at least one undoped polysilicon structure within the N area is masked, leaving exposed an upper portion of the other at least one undoped polysilicon structure within the P area. The exposed at least one undoped polysilicon structure within the P area is doped to form a P-doped polysilicon structure. An upper portion of the masked at least one undoped polysilicon structure within the N area is unmasked and exposed, and the P-doped polysilicon structure is masked. The exposed at least one undoped polysilicon structure within the N area is doped to form an N-doped polysilicon structure to complete fabrication of the doped polysilicon structures.

Abstract: In accordance with an aspect of the invention, a twin-well method of forming CMOS integrated circuitry having first and second conductivity type gates includes conducting a first conductivity type well implant, a second conductivity type well implant, a first conductivity type gate implant and a second conductivity type gate implant using no more than two masking steps. In another aspect of the invention, a twin well method of forming CMOS integrated circuitry having first and second conductivity type transistor gates includes conducting a first conductivity type well implant and a second conductivity type gate implant in a common masking step.

Abstract: A capacitively sensed micromachined component includes an electrically insulative substrate (120) having a first side (121) and a second side (122) opposite the first side. The component also includes a first layer (130) adjacent to the second side of the electrically insulative substrate where at least a first portion of the first layer located adjacent to the second side of the electrically insulative substrate is infra-red light absorbing and is also electrically conductive. The component further includes a diffusion and chemical barrier layer (240) encapsulating the first layer and the electrically insulative substrate. The component still further includes a capacitively sensed micromachined device (310) on the diffusion and chemical barrier layer.

Abstract: A method for fabricating a low temperature polysilicon thin film transistor incorporating a channel passivation step is described. The method achieves dopant ion activation in a polysilicon gate by using laser irradiation, however, with an additional insulating material layer such as SiOx or SixNy overlying and protecting the channel portion of the polysilicon gate. Any possible contamination by residual photoresist material after a photoresist removal step on the channel portion of the polysilicon gate can thus be avoided. Furthermore, deficiencies such as dopant ions out-diffusion and lateral diffusion can be avoided. The leakage current of the thin film transistors formed by the present invention method is significantly reduced when compared to those formed by a conventional method.

Abstract: A method for improving the gate activation of metal oxide semiconductor field effect transistor (MOSFET) structures are provided.

Abstract: A buried channel PMOS transistor for analog applications is integrated into a digital CMOS process. A third well region (105) is formed by implanting a region in the semiconductor substrate with all the n-type and p-type implants used to form the n-well and p-well regions for the digital CMOS process. A gate dielectric layer (50) and gate layer (109) are formed above the third well (105) and comprise the gate stack of the buried channel PMOS transistor. The implants used to form the drain extension regions and the source and drain regions of the CMOS transistors are used to complete the buried channel PMOS transistor.

Abstract: The present invention provides a method for forming an embedded memory MOS. The method involves first forming a first dielectric layer and an undoped polysilicon layer, respectively, on the surface of the semiconductor wafer with a defined memory array area and a periphery circuits region. Then, the undoped polysilicon layer in the memory array area is doped to become a doped polysilicon layer, followed by the formation of a protective layer on the surface of the semiconductor wafer. Thereafter, a first photolithographic and etching process(PEP) is used to etch the protective layer and the doped polysilicon layer in the memory array area to form a plurality of gates, and to form lightly doped drains(LDD) adjacent to each gate. A silicon nitride layer and a second dielectric layer are formed, followed by their removal in the periphery circuits region.

Abstract: The present invention provides a method for forming an embedded memory MOS. The method involves first forming a dielectric layer and an undoped polysilicon layer, respectively, on the surface of the semiconductor wafer with a defined memory array area and a periphery circuits region. Then, the undoped polysilicon layer in the memory array area is doped to become a doped polysilicon layer. Thereafter, a protective layer is formed on the surface of the semiconductor wafer, followed by a first photolithographic and etching process (PEP) to define a plurality of gate patterns in the protective layer in the memory array area. Then, a second PEP is applied to etch the undoped polysilicon layer in the periphery circuits region and the doped polysilicon layer in the memory array area to simultaneously form a gate of each MOS in the periphery circuits region and the memory array area.

Abstract: In accordance with the invention, a silicon gate field effect device is provided with improved control over the distribution of dopants by forming thin buried layer of oxide within the silicon gate. In essence, a silicon gate device is fabricated by the steps of forming a gate dielectric on a silicon substrate and forming a first layer of the silicon gate (amorphous or polycrystalline) on the dielectric. A thin layer of oxide is formed on the first gate layer, and a second silicon gate layer is formed on the oxide, producing a silicon gate containing a thin buried oxide layer. Dopants are then implanted through the second gate layer and the buried oxide, and the device is finished in a conventional manner. The buried oxide layer, acting as a sieve, maintains high dopant concentration near the interface between the gate and minimizes dopant outdiffusion through the gate.

Abstract: A method of forming a polysilicon layer includes the steps of: loading a semiconductor substrate in a CVD reactor wherein a gate insulating layer is formed on the substrate; decompressing the reactor; depositing a first polysilicon layer on the substrate by flowing an SiH4 gas into the reactor; forming a plurality of Si—N bonds on the first polysilicon layer by maintaining atmospheric pressure of the reactor by filling the reactor with nitrogen gas; decompressing the reactor; and depositing a second polysilicon layer on the first polysilicon layer by flowing SiH4 gas into the reactor.

Abstract: A method of reducing the boron-penetrating of effect in a CMOS transistor provides a silicon substrate, which comprises an isolating area, an active area and a gate oxide layer formed on the silicon substrate in the active layer. A polysilicon layer is then deposited on the silicon substrate. Next, boron ions (B+) are doped into the polysilicon layer. Next, a gate photoresist with a predetermined gate pattern is formed on the polysilicon layer. The polysilicon not covered by the gate photoresist is then etched to form a polysilicon gate. The gate photoresist is used as a mask to dope boron difluoride ions (BF2+) into the silicon substrate. Finally, after removing the gate photoresist, a tempering procedure is performed to form a shallow junction area of a source/drain region on the silicon substrate.

Abstract: A method for making a ULSI MOSFET chip includes forming transistor gates on a substrate and a semiconductor device thereby made. The gates are formed by depositing a polysilicon layer on the substrate, implanting germanium into the polysilicon layer at a comparatively low dose, and then oxidizing the doped polysilicon layer. Under the influence of the oxidation, the germanium is repelled from an upper sacrificial region of the polysilicon layer into a lower gate region of the polysilicon layer, thereby increasing the germanium concentration in the lower gate region. The sacrificial region is then etched away and an undoped polysilicon film deposited on the gate region. Subsequently, the gate region with undoped polysilicon film is patterned to establish a MOSFET gate, with the substrate then being appropriately processed to establish MOSFET source/drain regions.

Abstract: A silicon oxide film and a doped polysilicon film are successively formed on a silicon substrate. Then, a doped polysilicon-germanium film is formed on the doped polysilicon film as a film having a higher impurity activation rate than polysilicon. Then, a barrier film, a metal film and another barrier film are successively formed on the doped polysilicon-germanium film. Thus obtained is a method of manufacturing a semiconductor device comprising a polymetal gate capable of suppressing increase of gate resistance also when an impurity introduced into a semiconductor film diffuses into the barrier films.

Abstract: Methods and apparatus for forming a conductor layer utilize an implanted matrix to form C54-titanium silicide. Word line stacks formed by the methods of the invention are used in sub-0.25 micron line width applications, interconnects, and silicided source/drain regions, among other applications, and have a lower resistivity and improved thermal stability.

Abstract: After phosphorus is ion implanted into a portion of a polysilicon film, first RTA is performed. After boron is ion implanted into another portion of the polysilicon film, the polysilicon film is patterned to form a gate electrode and a resistor film. A TEOS film is deposited and patterned to form a silicidation mask having an opening corresponding to a silicidation region. Thereafter, annealing for activating boron is performed in an atmosphere containing oxygen, thereby forming oxide films on a gate electrode and on heavily doped source/drain regions in the silicidation region. The oxide films suppress out-diffusion of the impurities and inhibit the impurity ions from penetrating the gate electrode 8 during ion implantation for promoting silicidation, which is performed subsequently.

Abstract: A method of forming a gate oxide layer with improved ability to resist process damage increases the reliability and yield of a transistor device. First, a nitrogen-containing gate oxide layer is formed on an element area of a silicon substrate. Then, a polysilicon layer is deposited on the gate oxide layer. Next, a gate doping process and a fluorine ion implantation are performed on the polysilicon layer. Then, a high-temperature tempering procedure is performed to make the fluorine enter the gate oxide layer.

Abstract: The invention encompasses stacked semiconductor devices including gate stacks, wordlines, PROMs, conductive interconnecting lines, and methods for forming such structures. The invention also includes a method of forming a transistor gate comprising: a) forming gate dielectric layer; b) forming a polysilicon gate layer against the gate dielectric layer; and c) doping the polysilicon gate layer with a conductivity-enhancing dopant, the dopant being provided in a concentration gradient within the polysilicon layer, the concentration gradient increasing in a direction toward the gate dielectric layer. The invention also includes a wordline comprising: a) a polysilicon line; a substantially fluorine impervious barrier layer over the polysilicon line; and a b) layer of metal-silicide over the substantially fluorine impervious barrier layer.

Abstract: A method for manufacturing an MDL semiconductor device comprises forming a gate insulating layer and a gate conductive layer in a DRAM device region and a logic device region to provide gate conductive layer patterns which will be respectively formed in the DRAM device region and the logic device region. Next, the gate conductive layer of the logic device region is patterned, and a gate conductive layer pattern is formed only in the logic device region. Spacers are formed on the gate conductive layer patterns, and impurity ions of different conductivity types are twice injected by a process for forming a mask layer pattern and an ion injection process. The first ion injection is performed on one gate conductive layer pattern of the logic device region, and the second ion injection is performed on the gate conductive layer of the DRAM device region and the other gate conductive layer pattern of the logic device region.

Abstract: The present invention is directed to a method of forming a semiconductor device. In one illustrative embodiment, the method comprises forming a layer of polysilicon, forming a masking layer above the layer of polysilicon, and patterning the masking layer to expose portions of the layer of polysilicon. The method further comprises implanting a dopant material into the exposed portions of the layer of polysilicon to convert the exposed portions of the layer of polysilicon to substantially amorphous silicon, and performing an etching process to remove the substantially amorphous silicon to define a gate electrode.

Abstract: An aluminum wire is connected to a P-type layer of a polydiode element through a resistive element consisting of a barrier metal film and a tungsten plug. Another aluminum wire is connected to an N-type layer of the polydiode element through another resistive element consisting of another barrier metal film and another tungsten plug. Thus, a semiconductor device including a polydiode element which is resistant to surge or contamination is provided.

Abstract: In the manufacture of CMOS devices, the n+ gate is partially counterdoped with boron to produce a modified p-type FET that has improved short channel effects, reduced gate induced drain leakage and gate oxide fields for improved reliability. A doped polysilicon layer is formed over a silicon or silicon oxide substrate, and is counterdoped with boron to a level of about 1×1013/cm2 to 5×1016/cm2 to adjust the work function but without changing the essentially n-type character of the gate electrode. This single counterdoping step achieves improved results for sub-micron devices below 0.5 micron at low cost. For CMOS device manufacturing, the alternating n-type and p-type devices are made in similar manner but reversing the n-type and p-type dopants.

Abstract: There is provided a method of reliably preparing a diamond semiconductor by irradiating diamond with a corpuscular ray. In this method, when a diamond substrate is irradiated with a corpuscular ray, the diamond substrate is maintained at a temperature of 300° C. to 2000° C., the angle of the surface of the diamond substrate irradiated is set within −20° to +20° to the (001) crystal plane of the diamond substrate, and the angle of the direction of the corpuscular ray is set within −20° to +20° to the <001> crystal orientation of the diamond substrate. Preferably, the direction of the corpuscular ray forms an angle of 3° to 10° with the <001> crystal orientation.

Abstract: An embodiment of the instant invention is a method of making a transistor having a silicided gate structure insulatively disposed over a semiconductor substrate, the method comprising the steps of: forming a conductive structure insulatively disposed over the semiconductor substrate (step 302 of FIG. 3); introducing a silicide enhancing substance into the conductive structure (step 304 of FIG. 3); amorphizing a portion of the conductive structure; forming a metal layer on the conductive structure (step 310 of FIG. 3); and wherein the metal layer interacts with the silicide enhancing substance in the amorphized portion of the conductive structure so as to form a lower resistivity silicide on the conductive structure. The conductive structure is, preferably, comprised of: doped polysilicon, undoped polysilicon, epitaxial silicon, or any combination thereof. Preferably, the silicide enhancing substance is comprised of: molybdenum, Co, W, Ta, Nb, Ru, Cr, any refractory metal, and any combination thereof.

Abstract: A process for forming high-precision analog transistors with a low threshold voltage roll-up and digital transistors with a high threshold voltage roll-up is disclosed. The process selectively implants the polysilicon layer that forms the gates of the analog transistors so that the doping concentration of the analog gates is greater than the doping concentration of the digital gates.

Abstract: There is described a method of manufacturing a semiconductor device of dual-gate construction, which method prevents occurrence of a highly-resistant local area in a gate electrode of dual-gate construction. A polysilicon layer which is to become a conductive layer of a gate electrode of dual-gate construction is formed on an isolation oxide film. N-type impurities are implanted into an n-type implantation region of the polysilicon film while a photoresist film is taken as a mask. P-type impurities are implanted into a p-type impurity region of the polysilicon film 3 while another photoresist film is taken as a mask. Implantation of n-type impurities and implantation of p-type impurities are performed such that an overlapping area to be doped with these impurities in an overlapping manner is inevitably formed.

Abstract: In a method for forming a semiconductor device having a power MOSFET and a diode, after a gate electrode and n+ type source regions for the power MOSFET and an n+ type region of a poly-Si layer for the diode are formed, an oxide film is formed by thermal oxidation. At that time, accelerated oxidation occurs where an n type impurity is heavily implanted, so that the oxide film becomes thick on the surfaces of the gate electrode, the source regions, and the n+ type region, as compared to the other region. Then, a p type impurity is self-alignedly implanted through the oxide film serving as a mask to form a p+ type contact region for the MOSFET and a p+ type region of the poly-Si layer for the diode.

Abstract: According to the disclosed method, there is provided a structure consisting of a silicon substrate coated with a bottom thin SiO2 layer, a doped polysilicon layer, a refractory metal layer and a top Si3N4 capping layer. Said refractory metal and doped polysilicon layers will form a polycide layer under subsequent thermal treatments. First, a sacrificial layer of a dielectric material such as oxynitride is deposited onto the structure. Oxynitride is impervious to UV radiation and has excellent conformal properties. Then, a layer of a photoresist material is deposited onto the structure and patterned to form a mask. Now the dielectric and top Si3N4 layers are anisotropically etched using the photoresist mask. The mask is stripped and the refractory metal and doped polysilicon layers are anisotropically dry etched down to the SiO2 layer using the patterned dielectric layer as an in-situ hard mask.

Abstract: A process for device fabrication, comprising the steps of forming a dielectric material region on a silicon substrate, forming a first amorphous silicon or polysilicon region on the dielectric material region, implanting one or more dopants in the first amorphous silicon or polysilicon region, and, subsequent to implanting the one or more dopants in the first amorphous silicon or polysilicon region, forming a second amorphous silicon or polysilicon region on the first amorphous silicon or polysilicon region. Typically, a refractory metal silicide layer is formed over the silicon, and such silicide is optionally formed by a salicide process. The second silicon region makes it more difficult for the implanted dopants to reach the silicide layer, and thereby reduces undesirable lateral diffusion of dopants in the silicide and accompanying cross-doping. The buried nature of the dopants in the silicon further reduces the amount of lateral diffusion within the silicon, regardless of the gate material.

Abstract: A method for forming a cell passes transistor in DRAM process disclosed. In one embodiment, the present invention provides a MOS structure, which can reduce junction leakage for P/N junction and increase the refreshes time capability. A method for DRAM fabrication comprises providing a semiconductor substrate having at least an isolation device therein. The isolation device defines an active area adjacent thereto on the semiconductor substrate. A first photoresist layer is formed on the semiconductor substrate, which exposes the active area in a first direction. The first conductive ions are implanted to form a well region in the semiconductor substrate, and the second conductive ions are implanted to form a field implant region in the semiconductor substrate. The third conductive ions are implanted to form a punchthrough implant region in the semiconductor substrate. Then the first photoresist layer is removed, and a second photoresist layer is formed on the semiconductor substrate.

Abstract: There are disclosed multi-crystalline silicon which is added with Ga (gallium) as a dopant and a method for producing Ga-doped multi-crystalline silicon, which comprises adding Ga to silicon melt in a crucible, which is melted by heating, and cooling the silicon melt to allow growth of multi-crystalline silicon. According to the present invention, there are provided multi-crystalline silicon and a multi-crystalline silicon wafer for producing solar cells showing stable conversion efficiency for light energy without causing photodegradation as well as methods for producing them.

Abstract: An improved gas phase synthesized diamond, CBN, BCN, or CN thin film having a modified region in which strain, defects, color and the like are reduced and/or eliminated. The thin film can be formed on a substrate or be a free-standing thin film from which the substrate has been removed. The thin film can be stably and reproducibly modified to have an oriented polycrystal structure or a single crystal structure. The thin film is modified by being subjected to and heated by microwave irradiation in a controlled atmosphere. The thin film has a modified region in which a line width of the diamond spectrum evaluated by Raman spectroscopy of 0.1 microns or greater is substantially constant along a film thickness direction of the thin film, and the line width of the modified region is 85% or less of a maximum line width of the residual portion of the film thickness.

Abstract: A PIP (Poly-Interpoly-Poly) capacitor with high capacitance is provided in a split-gate flash memory cell. A method is also disclosed to form the same PIP capacitor where the bottom and top plates of the capacitor are formed simultaneously with the floating gate and control gate, respectively, of the split-gate flash memory cell. Furthermore, the thin interpoly oxide of the cell, rather than the thick poly-oxide over the floating gate is used as the insulator between the plates of the capacitor. The resulting capacitor yields high storage capacity through high capacitance per unit area.

Abstract: A method of forming a gate electrode with a titanium polycide which can prevent particle creation and abnormal oxidation of the gate electrode, is disclosed. In the present invention, a gate oxidation process is performed after implanting Si ions into the side wall or overall surface of the titanium silicide layer, thereby preventing abnormal oxidation of the titanium silicide during the gate oxidation process. Furthermore, a titanium silicide layer is deposited to a low mole ratio of Si/Ti, thereby minimizing particle creation.

Abstract: In a method for fabricating a highly activated shallow abrupt doped junction in a semiconductor substrate, a first dopant is implanted into a predetermined surface of the semiconductor substrate to form a preamorphization junction having a first predetermined depth from the predetermined surface of the semiconductor substrate. Furthermore, a second dopant is implanted into the preamorphization junction with a dopant profile along a depth of the semiconductor substrate from the predetermined surface of the semiconductor substrate. A peak of the dopant profile is located at a fraction of the first predetermined depth of the preamorphization junction. A silicidation RTA (Rapid Thermal Anneal) is performed to form silicide on the semiconductor substrate. The silicidation RTA (Rapid Thermal Anneal) recrystallizes the preamorphization junction from the first predetermined depth of the preamorphization junction up to an unrecrystallized depth of the preamorphization junction.

Abstract: A method (100) of forming a transistor (50, 80) includes forming a gate oxide (120) over a portion of a semiconductor material (56, 122) and forming a doped polysilicon film (124) having a dopant concentration over the gate oxide (122). Subsequently, the doped polysilicon film (124) is etched to form a gate electrode (52) overlying a channel region (58) in the semiconductor material (56, 122), wherein the gate electrode (52) separates the semiconductor material into a first region (60) and a second region (68) having the channel region (58) therebetween. The method (100) further includes forming a drain extension region (64) in the first region (60) and a source extension region (72) in the second region (68), and forming a drain region (62) in the first region (60) and a source region (70) in the second region (68). The source/drain formation is such that the drain and source regions (62, 70) have a dopant concentration which is less than the polysilicon film (124) doping concentration.

Abstract: The method of fabricating a semiconductor device having a dual-gate provides a semiconductor substrate with a gate insulating film formed on a first portion and a second portion thereof and a polysilicon layer formed on the gate insulating film. A first dopant of a first conductive type is implanted in the polysilicon layer covering the first portion, and a second dopant of a second conductive type is implanted in the polysilicon layer covering the second portion. Then, the polysilicon layer covering the first portion is selectively etched using a first mask to form a first gate, and a third dopant of the first conductive type is implanted to form source/drain LDD regions on both sides of the first gate. Thereafter, the polysilicon layer covering the second portion is selectively etched using a second mask to form a second gate, and a fourth dopant of the second conductive type is implanted to form source/drain LDD regions on both sides of the second gate.

Abstract: A method for forming a low voltage coefficient capacitor. A doped polysilicon layer is formed in a region predetermined to form a capacitor and a doped polysilicon layer is formed in a region predetermined to form a gate. A silicide layer is formed on the doped polysilicon layer serving as a bottom electrode of a capacitor.

Abstract: A power MOSFET suitable for use in RF applications and a method for making the same is disclosed. The power MOSFET has an increased distance between gate and drain regions of the device in order to decrease the device gate to drain capacitance Cgd. The distance between the gate and drain regions is increased by selective doping of a polysilicon layer of the gate to produce at least two polysilicon gate regions separated by a region of undoped polysilicon that is positioned over a substantial portion of the drain region that resides between the channel portions of the body region of the device. The addition of a contact oxide layer formed directly above the region of undoped polysilicon further increases the distance between gate and drain. Finally, a metal layer is deposited over the entire structure to form the gate and source electrodes of the device.

Abstract: A method for forming gate structures with smooth sidewalls by amorphizing the polysilicon along the gate boundaries is described. This method results in minimal gate depletion effects and improved critical dimension control in the gates of smaller devices. The method involves providing a gate silicon oxide layer on the surface of the semiconductor substrate. A gate electrode layer, such as polysilicon is deposited over the gate silicon oxide followed by a masking oxide layer deposited over the gate electrode layer. The masking oxide layer is patterned for the formation of the gate electrode. An ion implantation of silicon or germanium amorphizes the area of the polysilicon not protected by the masking oxide mask and also amorphizes the area along the boundaries of the polysilicon gate.

Abstract: A method for fabricating a semiconductor device having a wiring part connected via an opening portion formed in an insulting film on a semiconductor region to the semiconductor region. The wiring part includes a polycrystalline semiconductor layer and a metal or metal silicide on the semiconductor layer. A polycrystalline semiconductor layer is deposited over the opening portion of the semiconductor region. First and second impurities are respectively ion injected into the polycrystalline semiconductor layer, wherein the ion injecting range of the first impurities is longer than that of the second impurities, thereby forming a high concentration region at least on a surface side of the polycrystalline semiconductor layer. Following the ion injection of the first and second impurities, a heat treatment is conducted to grow crystals of the polycrystalline semiconductor layer. After the heat treatment, a metal or a metal silicide is deposited on the polycrystalline layer using a low melting point method.

Abstract: A method for forming hemispherical silicon grains on selected surfaces of a silicon layer includes the steps of forming a doped polysilicon layer over a substrate, and then forming amorphous spacers on the sidewalls of the doped polysilicon layer. Thereafter, an ion implantation is carried out to transform the upper portion of the doped polysilicon into an amorphous silicon layer. Finally, hemispherical silicon grains are formed on the upper surface of the amorphous layer lying above the polysilicon layer and the exposed surface of the amorphous spacers.

Abstract: The present invention relates to a method for fabricating an integrated circuit including an NPN-type bipolar transistor, including the steps of defining a base-emitter location of the transistor with polysilicon spacers resting on a silicon nitride layer; overetching the silicon nitride under the spacers; filling the overetched layer with highly-doped N-type polysilicon; depositing an N-type doped polysilicon layer; and diffusing the doping contained in the third and fourth layers to form the emitter of the bipolar transistor.

Abstract: A contact structure provides electrical contact between two polycrystalline silicon interconnect layers. The lower layer has a silicide layer on its upper surface. The upper polycrystalline silicon layer can be doped with a different conductivity type, and makes an ohmic contact with the silicided region of the lower polycrystalline silicon layer.