Solid Source In Operative Relation With Semiconductor Region Patents (Class 438/567)
  • Patent number: 9520529
    Abstract: The composition for forming a composition for forming a p-type diffusion layer, the composition containing a glass powder and a dispersion medium, in which the glass powder includes an acceptor element and a total amount of a life time killer element in the glass powder is 1000 ppm or less. A p-type diffusion layer and a photovoltaic cell having a p-type diffusion layer are prepared by applying the composition for forming a p-type diffusion layer, followed by a thermal diffusion treatment.
    Type: Grant
    Filed: November 9, 2013
    Date of Patent: December 13, 2016
    Assignee: Hitachi Chemical Co., Ltd.
    Inventors: Yoichi Machii, Masato Yoshida, Takeshi Nojiri, Kaoru Okaniwa, Mitsunori Iwamuro, Shuichiro Adachi, Tetsuya Sato, Keiko Kizawa
  • Patent number: 8912038
    Abstract: Methods of forming emitters for back-contact solar cells are described. In one embodiment, a method includes forming a first solid-state dopant source above a substrate. The first solid-state dopant source includes a plurality of regions separated by gaps. Regions of a second solid-state dopant source are formed above the substrate by printing.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: December 16, 2014
    Assignee: SunPower Corporation
    Inventors: Bo Li, Peter J. Cousins, David D. Smith
  • Patent number: 8846508
    Abstract: Methods to implant ions into the sidewall of a three dimensional high aspect ratio feature, such as a trench or via, are disclosed. The methods utilize a phenomenon known as knock-in, which causes a first species of ions, already disposed in the fill material, to become implanted in the sidewall when these ions are struck by ions of a second species being implanted into the fill material. In some embodiments, these first species and second species have similar masses to facilitate knock-in. In some embodiments, the entire hole is not completely filled with fill material. Rather, some fill material is deposited, an ion implant is performed to cause knock-in to the sidewall adjacent to the deposited fill material, and the process is repeated until the hole is filled.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: September 30, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Jonathan Gerald England, Andrew M. Waite, Simon Ruffell
  • Patent number: 8802486
    Abstract: Methods of forming emitters for back-contact solar cells are described. In one embodiment, a method includes forming a first solid-state dopant source above a substrate. The first solid-state dopant source includes a plurality of regions separated by gaps. Regions of a second solid-state dopant source are formed above the substrate by printing.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: August 12, 2014
    Assignee: SunPower Corporation
    Inventors: Bo Li, Peter J. Cousins, David D. Smith
  • Patent number: 8790957
    Abstract: Methods of fabricating back-contact solar cells and devices thereof are described. A method of fabricating a back-contact solar cell includes forming an N-type dopant source layer and a P-type dopant source layer above a material layer disposed above a substrate. The N-type dopant source layer is spaced apart from the P-type dopant source layer. The N-type dopant source layer and the P-type dopant source layer are heated. Subsequently, a trench is formed in the material layer, between the N-type and P-type dopant source layers.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: July 29, 2014
    Assignee: SunPower Corporation
    Inventors: Bo Li, David Smith, Peter Cousins
  • Patent number: 8450130
    Abstract: Provided is a semiconductor laser, wherein (?a??w)>15 (nm) and Lt<25 (?m), where ?w is the wavelength of light corresponding to the band gap of the active layer disposed at a position within a distance of 2 ?m from one end surface in a resonator direction, ?a is the wavelength of light corresponding to the band gap of the active layer disposed at a position that is spaced a distance of equal to or more than ( 3/10)L and ?( 7/10)L from the one end surface in a resonator direction, “L” is the resonator length, and “Lt” is the length of a transition region provided between the position of the active layer with a band gap corresponding to a light wavelength of ?w+2 (nm) and the position of the active layer with a band gap corresponding to a light wavelength of ?a?2 (nm) in the resonator direction.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: May 28, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Kentaro Tada, Kenji Endo, Kazuo Fukagai, Tetsuro Okuda, Masahide Kobayashi
  • Patent number: 8372721
    Abstract: Embedded DRAM MOSFETs including an array NFET having a gate stack comprising a high-K dielectric layer upon which is deposited a first metal oxide layer (CD1) then a conductive layer (TiN), and then a polysilicon layer (Poly). A logic PFET having substantially the same gate stack as the array NFET, and a logic NFET having a third gate stack comprising the high-K dielectric layer upon which is deposited the conductive layer (TiN) and then the polysilicon layer (Poly), without the first metal oxide layer (CD1) between the high-K dielectric layer and the conductive layer (TiN). The array NFET may therefore have a higher gate stack work function than the logic NFET, but substantially the same gate stack work function as the logic PFET.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: February 12, 2013
    Assignee: International Business Machines Corporation
    Inventors: Xiangdong Chen, Herbert L. Ho, Geng Wang
  • Patent number: 8030188
    Abstract: Provided is a method of forming a compound semiconductor device. In the method, a dopant element layer is formed on an undoped compound semiconductor layer. An annealing process is performed to diffuse dopants in the dopant element layer into the undoped compound semiconductor layer, thereby forming a dopant diffusion region. A rapid cooling process is performed using liquid nitrogen with respect to the substrate having the dopant diffusion region.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: October 4, 2011
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Mi-Ran Park, Jae-Sik Sim, Yong-Hwan Kwon, Bongki Mheen, Dae Kon Oh
  • Patent number: 7883998
    Abstract: It is to provide a vapor phase growth method in which an epitaxial layer consisting of a compound semiconductor such as InAlAs, can be grown, with superior reproducibility, on a semiconductor substrate such as Fe-doped InP. In vapor phase growth method for growing an epitaxial layer on a semiconductor substrate, a resistivity of the semiconductor substrate at a room temperature is previously measured, a set temperature of the substrate is controlled depending on the resistivity at the room temperature such that a surface temperature of the substrate is a desired temperature regardless of the resistivity of the semiconductor substrate, and the epitaxial layer is grown.
    Type: Grant
    Filed: February 15, 2005
    Date of Patent: February 8, 2011
    Assignee: Nippon Mining & Metals Co., Ltd.
    Inventors: Masashi Nakamura, Suguru Oota, Ryuichi Hirano
  • Patent number: 7507649
    Abstract: The invention relates to a method for doping a semiconductor material with Cesium, wherein said semiconductor material is exposed to a cesium vapor. Said Cesium vapor is provided by Cesium sublimation from a Cesium alloy. There is also provided an organic light emitting diode comprising at least one layer of a Cesium doped organic semiconductor material, wherein said at least one layer of said Cesium doped organic semiconductor material is doped with Cesium provided by Cesium evaporation of Cesium from a Cesium alloy. The Cesium vapor is preferably provided by Cesium sublimation from a standard organic material deposition evaporator.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: March 24, 2009
    Assignee: Novaled AG
    Inventors: Ansgar Werner, Tilmann Romainczyk
  • Patent number: 6825104
    Abstract: The present invention describes a method of manufacturing a semiconductor device, comprising a semiconductor substrate in the shape of a slice, the method comprising the steps of: step 1) selectively applying a pattern of a solids-based dopant source to a first major surface of said semiconducting substrate; step 2) diffusing the dopant atoms from said solids-based dopant source into said substrate by a controlled heat treatment step in a gaseous environment surrounding said semi-conducting substrate, the dopant from said solids-based dopant source diffusing directly into said substrate to form a first diffusion region and, at the same time, diffusing said dopant from said solids-based dopant source indirectly via said gaseous environment into said substrate to form a second diffusion region in at least some areas of said substrate to form a second diffusion region in at least some areas of said substrate not covered by said pattern; and step 3) forming a metal contact pattern substantially in alignment with
    Type: Grant
    Filed: January 27, 2003
    Date of Patent: November 30, 2004
    Assignee: Interuniversitair Micro-Elektronica Centrum (IMEC)
    Inventors: Jörg Horzel, Jozef Szlufcik, Mia Honoré, Johan Nijs
  • Patent number: 6774012
    Abstract: An improved furnace system and method is provided to substantially minimize, if not eliminate, ambient air from entering a heated chamber of the furnace system during a critical processing step. The furnace system can be used in, for example, an oxidation step where ambient air containing oxygen is prevented from entering an atmospheric pressure tube by essentially purging potential leak areas with an inert gas, such as nitrogen, at the critical moment during temperature ramp up and ramp down, and prior to temperature stabilization and the introduction of an oxidizing gas. If oxygen is not present within the tube, then a tungsten sidewall surface of a gate conductor, for example, will not inadvertently oxidize at the critical pre- and post-oxidation moments. However, if steam is present where hydrogen is available with oxygen, the underlying polysilicon sidewall surface will selectively oxidize instead of the overlying tungsten.
    Type: Grant
    Filed: November 8, 2002
    Date of Patent: August 10, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventor: Sundar Narayanan
  • Patent number: 6562705
    Abstract: A laser heating apparatus for forming an electrode on one surface of an Si chip provided on an Si wafer, thereby producing a semiconductor element, comprises a high vacuum chamber having a light transmission window, an XY table contained in the high vacuum chamber for mounting the Si wafer thereon, heater contained in the high vacuum chamber for heating and evaporating an impurity in a solid state, and laser beam applying means for applying a laser beam to the Si chip placed on the XY table from the outside of the high vacuum chamber through the light transmission window, thereby implanting the impurity into the Si in chip and activating the implanted impurity.
    Type: Grant
    Filed: October 26, 2000
    Date of Patent: May 13, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Obara, Hideki Nozaki, Motoshige Kobayashi
  • Patent number: 6461947
    Abstract: To form an impurity diffusion layer on only one side of a semiconductor substrate at least one semiconductor substrate and at least one diffusion protecting plate are put close to each other and a first impurity diffusion is perfomed on them, or at least one semiconductor substrate and at least one diffusion protecting plate are put close to each other and a first impurity diffusion is performed on them and then the semiconductor substrate and the diffusion protecting plate are arranged such that those sides on which the impurity diffusion has been performed face each other and a second impurity diffusion is performed. The diffusion protecting plate may be replaced by a semiconductor substrate. The first and second impurity diffusions may be performed using an impurity of the same conductivity type.
    Type: Grant
    Filed: September 7, 2000
    Date of Patent: October 8, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Tsuyoshi Uematsu, Yoshiaki Yazawa, Hiroyuki Ohtsuka, Ken Tsutsui
  • Patent number: 6461948
    Abstract: A method of doping silicon that involves placing a silicon wafer in spaced relationship to a solid phosphorus dopant source at a first temperature for a time sufficient to deposit a phosphorus-containing layer on the surface of the wafer and subsequently oxidizing the doped silicon wafer with wet oxygen or pyrogenic steam at a second temperature lower than the first temperature. The silicon wafer is maintained in spaced relationship to the solid phosphorus dopant source during the oxidizing step. The temperatures are selected such that the solid phosphorus dopant source evolves P2O5 at the first temperature and the second temperature is sufficiently lower than the first temperature to decrease evolution of P2O5 from the solid phosphorus dopant source during the oxidizing step.
    Type: Grant
    Filed: March 29, 2000
    Date of Patent: October 8, 2002
    Assignee: Techneglas, Inc.
    Inventors: James E. Rapp, Russell B. Rogenski
  • Patent number: 6426280
    Abstract: A method for doping crystals is disclosed. The method includes a receiver for receiving semiconductor spheres and doping powder. The semiconductor spheres and dopant powder are then directed to a chamber defined within an enclosure. The chamber maintains a heated, inert atmosphere with which to diffuse the dopant to the semiconductor spheres.
    Type: Grant
    Filed: January 25, 2001
    Date of Patent: July 30, 2002
    Assignee: Ball Semiconductor, Inc.
    Inventors: Evangellos Vekris, Nainesh J. Patel, Murali Hanabe
  • Patent number: 6426291
    Abstract: A method of forming ultra-shallow source/drain junctions in MOS devices by co-depositing cobalt or nickel with an n or p-type dopant following a seeding step. The co-deposition of cobalt or nickel with the dopant is done either via an electroless or an electrodeposition. The co-deposited Co(P) or Ni(P) is capped with a layer of PVD elemental titanium. The wafer is then annealed such that the titanium partially alloys with the cobalt or nickel and getters some of the cobalt or nickel limiting the thickness of the cobalt or nickel salicide which forms over exposed regions of the silicon substrate. The excess metal layers are removed with a wet etch, such as a piranha etch. A subsequent drive step forms ultra-shallow source/drain junctions using the doped cobalt or nickel salicide as a diffusion source.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: July 30, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Yongjun Jeff Hu, Li Li
  • Publication number: 20010041433
    Abstract: A method for doping crystals is disclosed. The method includes a receiver for receiving semiconductor spheres and doping powder. The semiconductor spheres and dopant powder are then directed to a chamber defined within an enclosure. The chamber maintains a heated, inert atmosphere with which to diffuse the dopant to the semiconductor spheres.
    Type: Application
    Filed: January 25, 2001
    Publication date: November 15, 2001
    Inventors: Evangellos Vekris, Nainesh J. Patel, Murali Hanabe
  • Patent number: 6143633
    Abstract: A dendritic web formation process and apparatus for diffusing dopant impurities into a growing dendritic crystal web to produce photovoltaic cells. A solid dopant diffusion source is arranged in a holder mounted in a vertical thermal element either within the melt furnace or outside the furnace adjacent the furnace exit port. The solid diffusion source is heated by thermal conduction from the vertical thermal element and source holder using the furnace heat as a source. Auxiliary heater coils are optionally provided around the vertical thermal element to control the temperature of the solid diffusion source. The source and holder can also be mounted outside the furnace adjacent the exit port and heated using a secondary rapid temperature external heater. The growing dendritic crystal web is exposed to the dopant impurities as part of the web growing process, eliminating the need for a separate diffusion gaseous station and processing.
    Type: Grant
    Filed: October 4, 1996
    Date of Patent: November 7, 2000
    Assignee: Ebara Solar, Inc.
    Inventor: Balakrishnan R Bathey
  • Patent number: 6110276
    Abstract: A method for making n-type semiconducting diamond by use of CVD in which n-type impurities are doped simultaneously with the deposition of diamond. As the n-type impurities, an Li compound and a B compound, both, are used at once. After doping, a diamond film thus obtained is etched to peel off its surface. The n-type semiconducting diamond is superior in specific resistivity, 10.sup.-2 .OMEGA.cm or less.
    Type: Grant
    Filed: February 24, 1998
    Date of Patent: August 29, 2000
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Jin Yu, Woong Sun Lee, Jung Keun Kim
  • Patent number: 5972784
    Abstract: Disclosed is an arrangement, dopant source and method used in the fabrication of photocells that minimize handling of cell wafers and involve a single furnace step. First, dopant sources are created by depositing selected dopants onto both surfaces of source wafers. The concentration of dopant that is placed on the surface is relatively low so that the sources are starved sources. These sources are stacked with photocell wafers in alternating orientation in a furnace. Next, the temperature is raised and thermal diffusion takes place whereby the dopant leaves the source wafers and becomes diffused in a cell wafer creating the junctions necessary for photocells to operate. The concentration of dopant diffused into a single side of the cell wafer is proportional to the concentration placed on the respective dopant source facing the side of the cell wafer. Then, in the same thermal cycle, a layer of oxide is created by introducing oxygen into the furnace environment after sufficient diffusion has taken place.
    Type: Grant
    Filed: April 24, 1997
    Date of Patent: October 26, 1999
    Assignee: Georgia Tech Research Corporation
    Inventors: Ajeet Rohatgi, Thomas W. Krygowski
  • Patent number: 5926727
    Abstract: A method (10) of phosphorus doping a semiconductor particle using ammonium phosphate. A p-doped silicon sphere is mixed with a diluted solution of ammonium phosphate having a predetermined concentration. These spheres are dried (16, 18), with the phosphorus then being diffused (20) into the sphere to create either a shallow or deep p-n junction. A good PSG glass layer is formed on the surface of the sphere during the diffusion process. A subsequent segregation anneal process is utilized to strip metal impurities from near the p-n junction into the glass layer. A subsequent HF strip procedure is then utilized to removed the PSG layer. Ammonium phosphate is not a restricted chemical, is inexpensive, and does not pose any special shipping, handling, or disposal requirement.
    Type: Grant
    Filed: December 11, 1995
    Date of Patent: July 20, 1999
    Inventors: Gary Don Stevens, Jeffrey Scott Reynolds
  • Patent number: 5866472
    Abstract: A direct doping method for semiconductor wafers, comprising the steps of providing a semiconductor wafer, exposing the surface of the wafer to a process medium in order to directly dope at least a portion of the surface of the wafer, wherein the process medium comprises a dopant gas, and wherein the dopant gas comprises an organic compound of a dopant species, and heating the wafer, thermally activating the direct doping process and causing solid-state diffusion of the dopant species into the semiconductor wafer surface. The organic source of a dopant species includes the organic compounds comprising boron, arsenic and phosphorous. The wafer is heated in the presence of an organic dopant source, thermally activating the doping process and causing surface chemisorption, surface dissociation, and solid-state diffusion of the dopant species into the wafer surface. The organic dopant source can be used with a germanium-containing additive gas, a halogen-containing compound or a remote plasma energy source.
    Type: Grant
    Filed: January 16, 1997
    Date of Patent: February 2, 1999
    Assignee: Texas Instruments Incorporated
    Inventor: Mehrdad M. Moslehi
  • Patent number: 5851906
    Abstract: In order to dope impurities selectively at low temperature where the resist can be used, the invention presents an impurity doping method capable of performing not only cleaning process but also doping process at low temperature where the resist can be used. First, the active sample surface of a solid sample is exposed by irradiation with plasma, and without active irradiation with plasma, the gas or vapor containing object impurities is contacted with the active sample surface of the solid sample to dope the impurities. As a result, the impurity doping process at the time of formation of C-MOS structure or the like can be executed at low temperature so as not to spoil the function of the resist.
    Type: Grant
    Filed: August 7, 1996
    Date of Patent: December 22, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Bunji Mizuno, Hiroaki Nakaoka, Michihiko Takase, Ichiro Nakayama
  • Patent number: 5851909
    Abstract: An impurity adsorption layer is formed on a substrate surface and solid-phase thermal diffusion is carried out to form source and drain regions for a metal-insulator-semiconductor field-effect-transistor having lightly doped drain structure or double doped drain structure. The thus formed impurity-doped region is ultrashallow, thereby producing high speed semiconductor devices of small dimensions.
    Type: Grant
    Filed: January 19, 1993
    Date of Patent: December 22, 1998
    Assignee: Seiko Instruments Inc.
    Inventors: Masaaki Kamiya, Kenji Aoki, Naoto Saito
  • Patent number: 5763320
    Abstract: A method (10,30) of boron doping a semiconductor particle using boric acid to obtain a p-type doped particle. Either silicon spheres or silicon powder is mixed with a diluted solution of boric acid having a predetermined concentration. The spheres are dried (16), with the boron film then being driven (18) into the sphere. A melt procedure mixes the driven boron uniformly throughout the sphere. In the case of silicon powder, the powder is metered out (38) into piles and melted/fused (40) with an optical furnace. Both processes obtain a p-type doped silicon sphere with desired resistivity. Boric acid is not a restricted chemical, is inexpensive, and does not pose any special shipping, handling, or disposal requirements.
    Type: Grant
    Filed: December 11, 1995
    Date of Patent: June 9, 1998
    Inventors: Gary Don Stevens, Jeffrey Scott Reynolds, Louanne Kay Brown
  • Patent number: 5656541
    Abstract: The present invention relates to a solid low temperature phosphorus diffusion source that is an R.sub.2 O.sub.3 /P.sub.2 O.sub.5 compound in which the ratio of R.sub.2 O.sub.3 to P.sub.2 O.sub.5 is 1 to 5 and R is Nd, Eu, Pr, Sm, Ho, Tb, Er, Yb, Tm or Dy. The invention also relates to a method of making the diffusion source, a method of using the diffusion source to evolve P.sub.2 O.sub.5 to dope a silicon wafer, and the doped silicon wafer.
    Type: Grant
    Filed: July 5, 1995
    Date of Patent: August 12, 1997
    Assignee: Techneglas, Inc.
    Inventors: James E. Rapp, Gary R. Pickrell
  • Patent number: 5635422
    Abstract: Dopants from a diffusion source (16) are diffused into a product wafer (14) to form a uniform doping concentration within the product wafer (14). The source (16) has a thermal conductivity that is approximately equal to a thermal conductivity of the wafer (14). The source (16) is positioned near the wafer (14) thereby forming a space (23) between the source (16) and the wafer (14). Gas flow (26) through the space (23) is limited to a predetermined value in order to prevent disturbing dopant diffusion. The source (16) is heated to a predetermined temperature, then the wafer (14) is heated. Subsequently, the wafer (14) and the source (16) are cooled at substantially equal rates.
    Type: Grant
    Filed: March 2, 1992
    Date of Patent: June 3, 1997
    Assignee: Motorola, Inc.
    Inventor: Bohumil Lojek
  • Patent number: 5629234
    Abstract: The present invention relates to a solid high temperature phosphorus diffusion source that is an R.sub.2 O.sub.3 /P.sub.2 O.sub.5 compound in which the ratio of R.sub.2 O.sub.3 to P.sub.2 O.sub.5 is 1 to 3 and R is La, Y, Ce, Nd, Eu, Pr, Sm, Ho, Tb, Er, Yb, Tm or Dy. The invention also relates to a method of making the diffusion source, a method of using the diffusion source to evolve P.sub.2 O.sub.5 to dope a silicon wafer, and to the doped silicon wafer.
    Type: Grant
    Filed: October 19, 1995
    Date of Patent: May 13, 1997
    Assignee: Techneglas, Inc.
    Inventors: Gary R. Pickrell, James E. Rapp