In Capsule-type Enclosure Patents (Class 438/568)
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Patent number: 7989329Abstract: A method and apparatus for removing excess dopant from a doped substrate is provided. In one embodiment, a substrate is doped by surfaced deposition of dopant followed by formation of a capping layer and thermal diffusion drive-in. A reactive etchant mixture is provided to the process chamber, with optional plasma, to etch away the capping layer and form volatile compounds by reacting with excess dopant. In another embodiment, a substrate is doped by energetic implantation of dopant. A reactive gas mixture is provided to the process chamber, with optional plasma, to remove excess dopant adsorbed on the surface and high-concentration dopant near the surface by reacting with the dopant to form volatile compounds. The reactive gas mixture may be provided during thermal treatment, or it may be provided before or after at temperatures different from the thermal treatment temperature. The volatile compounds are removed.Type: GrantFiled: December 21, 2007Date of Patent: August 2, 2011Assignee: Applied Materials, Inc.Inventors: Kartik Ramaswamy, Kenneth S. Collins, Biagio Gallo, Hiroji Hanawa, Majeed A. Foad, Martin A. Hilkene, Kartik Santhanam, Matthew D. Scotney-Castle
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Patent number: 7883998Abstract: It is to provide a vapor phase growth method in which an epitaxial layer consisting of a compound semiconductor such as InAlAs, can be grown, with superior reproducibility, on a semiconductor substrate such as Fe-doped InP. In vapor phase growth method for growing an epitaxial layer on a semiconductor substrate, a resistivity of the semiconductor substrate at a room temperature is previously measured, a set temperature of the substrate is controlled depending on the resistivity at the room temperature such that a surface temperature of the substrate is a desired temperature regardless of the resistivity of the semiconductor substrate, and the epitaxial layer is grown.Type: GrantFiled: February 15, 2005Date of Patent: February 8, 2011Assignee: Nippon Mining & Metals Co., Ltd.Inventors: Masashi Nakamura, Suguru Oota, Ryuichi Hirano
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Publication number: 20040171239Abstract: For the formation of a first aluminum interconnect line (3) serving as a lower electrode of a MIM capacitor element, an antireflection film (4) having a two-layer structure of a TiN layer (41) and a SiON layer (42) is used. The SiON layer (42) of the antireflection film (4) is utilized as-is as a dielectric layer of the MIM capacitor element. An upper electrode (81) and a contact plug (82) are formed by the same process. Since the upper surfaces of the upper electrode (81) and the contact plug (82) are at the same level, an electrical contact can be easily provided between a second aluminum interconnect line (10) and each of the upper electrode (81) and the lower electrode (first aluminum interconnect line (3)) of the MIM capacitor element. Accordingly, the MIM capacitor element and contacts to the upper and lower electrodes of the MIM capacitor element can be formed through simple processes.Type: ApplicationFiled: June 30, 2003Publication date: September 2, 2004Applicant: Renesas Technology Corp.Inventors: Tomohiro Tanaka, Naofumi Murata, Tohru Koyama
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Patent number: 6562705Abstract: A laser heating apparatus for forming an electrode on one surface of an Si chip provided on an Si wafer, thereby producing a semiconductor element, comprises a high vacuum chamber having a light transmission window, an XY table contained in the high vacuum chamber for mounting the Si wafer thereon, heater contained in the high vacuum chamber for heating and evaporating an impurity in a solid state, and laser beam applying means for applying a laser beam to the Si chip placed on the XY table from the outside of the high vacuum chamber through the light transmission window, thereby implanting the impurity into the Si in chip and activating the implanted impurity.Type: GrantFiled: October 26, 2000Date of Patent: May 13, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Obara, Hideki Nozaki, Motoshige Kobayashi
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Patent number: 6448167Abstract: A process for forming a composite insulator spacer on the sides of a MOSFET gate structure, wherein the underlying component of the composite insulator spacer is comprised of a thin silicon oxide layer obtained via chemical vapor deposition procedures using tetraethylorthosilicate (TEOS), as a source, has been developed. To densify the underlying thin silicon oxide layer an anneal procedure usually performed after implantation of ions used for a lightly doped source/drain region, is delayed and performed after deposition of the thin silicon oxide layer. The anneal procedure is then used for both activation of the lightly doped source/drain ions, and densification of the thin silicon oxide layer. The etch rate of the densified silicon oxide layer, in dilute hydrofluoric acid procedures is now reduced allowing the underlying silicon oxide component, of the composite insulator spacer, to survive subsequent wet clean procedures employing dilute hydrofluoric acid.Type: GrantFiled: December 20, 2001Date of Patent: September 10, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Ling-Sung Wang, Ying-Lin Chen
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Patent number: 6426280Abstract: A method for doping crystals is disclosed. The method includes a receiver for receiving semiconductor spheres and doping powder. The semiconductor spheres and dopant powder are then directed to a chamber defined within an enclosure. The chamber maintains a heated, inert atmosphere with which to diffuse the dopant to the semiconductor spheres.Type: GrantFiled: January 25, 2001Date of Patent: July 30, 2002Assignee: Ball Semiconductor, Inc.Inventors: Evangellos Vekris, Nainesh J. Patel, Murali Hanabe
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Patent number: 6399480Abstract: At least one patterned dielectric layer is provided within a transistor arrangement to prevent a local interconnect from electrically contacting,the gate conductor due to misalignments during the damascene formation of etched openings used in forming local interconnects. By selectively etching through a plurality of dielectric layers during the local interconnect etching process, the patterned dielectric layer is left in place to prevent short-circuiting of the gate to an adjacent local interconnect that is slightly misaligned.Type: GrantFiled: February 29, 2000Date of Patent: June 4, 2002Assignee: Advanced Micro Devices, Inc.Inventors: William G. En, Darin A. Chan, David K. Foote, Fei Wang, Minh Van Ngo
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Publication number: 20010041433Abstract: A method for doping crystals is disclosed. The method includes a receiver for receiving semiconductor spheres and doping powder. The semiconductor spheres and dopant powder are then directed to a chamber defined within an enclosure. The chamber maintains a heated, inert atmosphere with which to diffuse the dopant to the semiconductor spheres.Type: ApplicationFiled: January 25, 2001Publication date: November 15, 2001Inventors: Evangellos Vekris, Nainesh J. Patel, Murali Hanabe
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Patent number: 6090722Abstract: A self-aligned dielectric spacer is etched by providing capped gate structure along a second layer of dielectric material located above the gate cap material. Dopant material at an increased doping level is provided in the second layer of dielectric material where the self-aligned spacer is to be located. The second layer of dielectric material is then etched selective to the dopant to define the self-aligned dielectric spacer.Type: GrantFiled: January 6, 1999Date of Patent: July 18, 2000Assignee: International Business Machines CorporationInventors: Michael Armacost, Sandra G. Malhotra, Tina Wagner, Richard Wise
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Patent number: 6083833Abstract: A method for forming a conductive film for a semiconductor device wherein a conductive film is formed on each wafer loaded in a boat of a vertical furnace of a low pressure chemical vapor deposition apparatus provided with a chamber, a reaction tube in a center portion of the chamber, a boat loaded in the reaction chamber and a heater surrounding the chamber. The method includes a decompression step for reducing pressure in the chamber to a vacuum condition, a deposition step for depositing a conductive film on each wafer by introducing reaction gas into the chamber in the vacuum condition, a purge step for removing from the chamber toxic gas generated in the deposition step, and a normal pressure step for increasing pressure and temperature in the chamber, wherein the pressure increases from the normal pressure step and the temperature increases from the purge step.Type: GrantFiled: June 16, 1998Date of Patent: July 4, 2000Assignee: LG Semicon Co., Ltd.Inventor: Min Su Ahn