Abstract: A method for manufacturing a semiconductor device, comprises the steps of: depositing a first insulating film on a semiconductor substrate, and then, applying a photo resist to the first insulating film to align and develop the photo resist to form a first photo resist pattern; side-etching the first insulating film, by a predetermined size from an end portion of the first photo resist pattern, using the first photo resist pattern as a mask; depositing a second insulating film on the entire surface of the semiconductor substrate to form a gap above the semiconductor substrate between the first and second insulating films; removing the first photo resist pattern; and forming a gate electrode.

Abstract: A method of producing a platinum-metal structure or pattern on a substrate, which includes the steps of applying a silicon oxide layer to the substrate; applying a mask to the silicon oxide layer which is formed with an opening at a location thereof at which the platinum-metal structure or pattern is to be produced; etching the silicon oxide layer so that the substrate surface area exposed by the opening formed in the mask is larger than the opening in the mask; applying a platinum-metal layer to the mask and the exposed substrate surface area; and removing the silicon oxide layer in an etching process, so that the platinum metal present on the mask is removed simultaneously therewith, and the platinum metal present on the substrate surface forms the platinum-metal pattern or structure.

Abstract: A method of fabricating a capacitor in a DRAM. A semiconductor substrate having a metal-oxide-semiconductor is provided. Using only one photolithography process, a bottom electrode is formed. By forming a dielectric layer over the substrate, and a poly-silicon layer on the dielectric layer, a capacitor is formed.

Abstract: In a method for fabricating a semiconductor device, an insulating layer is formed on a semiconductor substrate, then a resist layer is formed on the insulating layer to have an opening therein. Next, removing the insulating layer at the bottom of the opening, then a reflow process is performed to the resist layer to have a curved surface thereon.

Abstract: Salicide (self-aligned silicide) structures are formed using a process that does not form oxide spacer structures alongside polysilicon gate electrodes and wiring lines. A shaped polysilicon electrode is formed having protrusions extending beyond the sidewalls of the electrode. LDD source/drain regions are formed by ion implantation using only the polysilicon gate electrode as a mask, thereby forming LDD source drain/regions without using spacer oxide regions. Physical vapor deposition is used to deposit a metal layer having discontinuities at or adjacent the protrusions. A first rapid thermal anneal is performed to cause the metal to form a metal silicide over the polysilicon electrode. Unreacted metal is etched and then a second rapid thermal anneal is performed to convert the metal silicide to its lowest resistivity phase.

Abstract: Method for manufacturing a T-gate useful for reducing a gate resistance, improving through-put, and simplifying an MMIC (monolithic microwave integrated circuit) process is disclosed, the method including the steps of depositing a first photoresist layer on a semiconductor substrate and patterning the first photoresist layer so as to expose a predetermined portion of the surface of the substrate; successively forming a seed metal layer and a second photoresist layer on the entire surface inclusive of the exposed substrate and patterning the second photoresist layer so as to define a gate electrode region; plating Au on the seed metal layer on the gate electrode region so as to form a gate electrode; and removing the first and second photoresist layers and the seed metal layer except the gate electrode.

Abstract: A method is provided for forming a transistor in which capacitive coupling between the gate conductors and adjacent structures employed by the integrated circuit is reduced. According to an embodiment, a gate conductor is dielectrically spaced above a semiconductor substrate, and a masking structure is arranged upon an upper surface of the gate conductor. A source/drain implant self-aligned to opposed lateral sidewalls of the masking structure is performed to form source/drain implant areas within the substrate. Select portions of the gate conductor are removed such that opposed ends of the masking structure extend beyond opposed sidewall surfaces of the gate conductor. A lightly doped drain implant self-aligned to the opposed sidewall surfaces of the narrowed gate conductor is performed to form lightly doped drain implant areas within the substrate.

Abstract: Methods of forming electrical interconnects on semiconductor substrates include the steps of forming a first electrically insulating layer (e.g., silicon dioxide) and then forming a contact hole in the insulating layer to expose a layer underlying the insulating layer. A first electrically conductive region (e.g., W, Ti, Tin, Al) is then formed in the contact hole. A step is then performed to remove a portion of the first electrically insulating layer to define a recess therein which preferably surrounds an upper portion of the first conductive region. A second electrically conductive region (e.g., Al, Cu, W, Ti, Ta and Co) is then formed in the recess. Here, the first conductive region is preferably chosen to have good step coverage capability to fully bury the contact hole and the second conductive region is preferably chosen to have very low resistance even if some degree of step coverage capability is sacrificed. Planarization steps (e.

Abstract: A dielectric film is formed on a semiconductor substrate, and on the dielectric film an inorganic dielectric mask film is deposited by CVD. The mask film comprises a first component which is relatively high in etch rate by isotropic plasma etching and a second component relatively low in etch rate, and the content of the first component is linearly gradient in the film thickness direction so as to become lowest at the interface between the mask film and the underlying dielectric film. For example, the mask film is a phosphosilicate glass (P.sub.2 O.sub.5 --SiO.sub.2) film. A resist film is formed on the mask film, and a window is opened in the resist film by electron beam lithography. Then a window is opened in the mask film by isotropic plasma etching, and the underlying dielectric film is also etched to form a window under the window in the mask film.

Abstract: A method for fabricating a T-shaped gate electrode includes the steps of: forming a fine gate pattern on a semiconductor substrate; forming an insulating layer on the semiconductor substrate on which the gate pattern is formed, and forming a planarizing layer on the insulating layer to planarize the surface of the semiconductor substrate; etching the planarizing layer to expose the top of the insulating layer; isotropically etching the insulating layer to expose the gate pattern using the planarizing layer as a mask; etching the exposed gate pattern to selectively expose the semiconductor substrate; depositing a gate metal to cover the exposed substrate, the insulating layer and the planarizing layer, to form a T-shaped gate; and simultaneously removing the planarizing layer, thereby forming a T-shaped gate metal with improved productivity.

Abstract: A method of forming a T-type gate electrode of a high-frequency transistor having excellent high-frequency power transfer characteristic with no concave portions and protrusions. A first resist pattern having a first relatively narrow opening is formed on a semiconductor substrate and a leg portion of the electrode is formed in the first opening by depositing electrode metal on the substrate. A second resist pattern having a second relatively wide opening is formed over the electrode leg portion for locating an exposed tip of the electrode leg portion in the bottom of the second opening and forming a head portion of the electrode by depositing electrode metal in the second opening. The head portion is etched for removing any protrusions formed on the head portion.

Abstract: A high power, flip-chip microwave monolithic integrated circuit (MMIC) assembly (30) has a high power microwave monolithic integrated circuit (MMIC) having a surface with an active area (72) in which heat is generated. The assembly also has a host substrate (34). A thermally conductive bump (51) formed over the surface of the MMIC has a first portion (51') in close proximity to and in thermal communication with the active area (72) of the MMIC and a second portion (51") which is in close proximity to and in thermal communication with the host substrate (34). The second portion (51") of the thermal bump (51) has a greater cross-sectional area than the first portion (51'). A multi-layer, multi-exposure method of manufacturing the improved thermal bump (51) includes several steps. A plating membrane (80) is formed on a surface of the MMIC (32). A first layer of negative photoresist is applied to the surface of the plating membrane (80), and is exposed with a first masked pattern of light.