Using Refractory Group Metal (i.e., Titanium (ti), Zirconium (zr), Hafnium (hf), Vanadium (v), Niobium (nb), Tantalum (ta), Chromium (cr), Molybdenum (mo), Tungsten (w), Or Alloy Thereof) Patents (Class 438/582)
  • Patent number: 10510800
    Abstract: An integrated circuit is provided with a (bridge) rectifier circuit configured to couple to an alternating current (AC) supply to a (string of) LEDs monolithically fabricated on substrate, preferably on a patterned sapphire substrate (PSS). The rectifier including at least one schottky barrier diode configured to have a reverse-bias breakdown voltage substantially equal to or greater than half a peak voltage of the AC supply. Further embodiments include a method for fabricating an integrated Schottky barrier diode (SBD) with a LED on a LED wafer. Some embodiments can include etching processes to a wafer that may include a plurality of processing cycles. Some embodiments can further include a wafer having a patterned substrate. The wafer with the patterned substrate may have an interface layer configured to facilitate increasing a forward bias current density of the SBD.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: December 17, 2019
    Assignee: The Penn State Research Foundation
    Inventors: Jie Liu, Jian Xu
  • Patent number: 9640683
    Abstract: A semiconductor structure includes a silicon substrate, a protection layer, an electrical pad, an isolation layer, a redistribution layer, a conductive layer, a passivation layer, and a conductive structure. The silicon substrate has a concave region, a step structure, a tooth structure, a first surface, and a second surface opposite to the first surface. The step structure and the tooth structure surround the concave region. The step structure has a first oblique surface, a third surface, and a second oblique surface facing the concave region and connected in sequence. The protection layer is located on the first surface of the silicon substrate. The electrical pad is located in the protection layer and exposed through the concave region. The isolation layer is located on the first and second oblique surfaces, the second and third surfaces of the step structure, and the tooth structure.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: May 2, 2017
    Assignee: XINTEC INC.
    Inventors: Wei-Luen Suen, Wei-Ming Chien, Po-Han Lee, Tsang-Yu Liu, Yen-Shih Ho
  • Patent number: 9117681
    Abstract: A silicon carbide semiconductor element and a manufacturing method thereof are disclosed in which a low contact resistance is attained between an electrode film and a wiring conductor element, and the wiring conductor element is hardly detached from the electrode film. In the method, a nickel film and a nickel oxide film are laminated in this order on a surface of an n-type silicon carbide substrate or an n-type silicon carbide region of a silicon carbide substrate, followed by a heat treatment under a non-oxidizing condition. The heat treatment transforms a portion of the nickel film into a nickel silicide film. Then, the nickel oxide film is removed with hydrochloric acid solution, and subsequently, a nickel aluminum film and an aluminum film are laminated in this order on a surface of the nickel silicide film.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: August 25, 2015
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yasuyuki Kawada, Takeshi Tawara, Shun-ichi Nakamura, Masahide Gotoh
  • Patent number: 8987124
    Abstract: A silicon carbide substrate having a main face is prepared. By applying thermal oxidation to the main face of the silicon carbide substrate at a first temperature, an oxide film is formed on the main face. After the oxide film is formed, heat treatment is applied to the silicon carbide substrate at a second temperature higher than the first temperature. An opening exposing a portion of the main face is formed at the oxide film. A Schottky electrode is formed on the main face exposed by the opening.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: March 24, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Tomihito Miyazaki, Toru Hiyoshi
  • Patent number: 8900899
    Abstract: Novel processing methods for production of high-refractive index contrast and low loss optical waveguides are disclosed. In one embodiment, a “channel” waveguide is produced by first depositing a lower cladding material layer with a low refractive index on a base substrate, a refractory metal layer, and a top diffusion barrier layer. Then, a trench is formed with an open surface to the refractory metal layer. The open surface is subsequently oxidized to form an oxidized refractory metal region, and the top diffusion barrier layer and the non-oxidized refractory metal region are removed. Then, a low-refractive-index top cladding layer is deposited on this waveguide structure to encapsulate the oxidized refractory metal region. In another embodiment, a “ridge” waveguide is produced by using similar process steps with an added step of depositing a high-refractive-index material layer and an optional optically-transparent layer.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: December 2, 2014
    Inventor: Payam Rabiei
  • Patent number: 8890279
    Abstract: A trench Schottky rectifier device includes a substrate having a first conductivity type, a plurality of trenches formed in the substrate, and an insulating layer formed on sidewalls of the trenches. The trenches are filled with conductive structure. There is an electrode overlying the conductive structure and the substrate, and thus a Schottky contact forms between the electrode and the substrate. A plurality of embedded doped regions having a second conductivity type are formed in the substrate and located under the trenches. Each doped region and the substrate form a PN junction to pinch off current flowing toward the Schottky contact so as to suppress current leakage.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: November 18, 2014
    Assignee: PFC Device Corp.
    Inventors: Kou-Liang Chao, Mei-Ling Chen, Tse-Chuan Su, Hung-Hsin Kuo
  • Patent number: 8865556
    Abstract: Techniques for forming a smooth silicide without the use of a cap layer are provided. In one aspect, a FET device is provided. The FET device includes a SOI wafer having a SOI layer over a BOX and at least one active area formed in the wafer; a gate stack over a portion of the at least one active area which serves as a channel of the device; source and drain regions of the device adjacent to the gate stack, wherein the source and drain regions of the device include a semiconductor material selected from: silicon and silicon germanium; and silicide contacts to the source and drain regions of the device, wherein an interface is present between the silicide contacts and the semiconductor material, and wherein the interface has an interface roughness of less than about 5 nanometers.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Joseph S. Newbury, Kenneth Parker Rodbell, Zhen Zhang, Yu Zhu
  • Patent number: 8858763
    Abstract: Disclosed are apparatus and method embodiments for achieving etch and/or deposition selectivity in vias and trenches of a semiconductor wafer. That is, deposition coverage in the bottom of each via of a semiconductor wafer differs from the coverage in the bottom of each trench of such wafer. The selectivity may be configured so as to result in punch through in each via without damaging the dielectric material at the bottom of each trench or the like. In this configuration, the coverage amount deposited in each trench is greater than the coverage amount deposited in each via.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: October 14, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Erich R. Klawuhn, Robert Rozbicki, Girish A. Dixit
  • Patent number: 8815724
    Abstract: Embodiments of the invention described herein generally provide methods and apparatuses for forming cobalt silicide layers, metallic cobalt layers, and other cobalt-containing materials. In one embodiment, a method for forming a cobalt silicide containing material on a substrate is provided which includes exposing a substrate to at least one preclean process to expose a silicon-containing surface, depositing a cobalt silicide material on the silicon-containing surface, depositing a metallic cobalt material on the cobalt silicide material, and depositing a metallic contact material on the substrate. In another embodiment, a method includes exposing a substrate to at least one preclean process to expose a silicon-containing surface, depositing a cobalt silicide material on the silicon-containing surface, expose the substrate to an annealing process, depositing a barrier material on the cobalt silicide material, and depositing a metallic contact material on the barrier material.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: August 26, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Seshadri Ganguli, Schubert S. Chu, Mei Chang, Sang-ho Yu, Kevin Moraes, See-Eng Phan
  • Patent number: 8796808
    Abstract: A MOS P-N junction Schottky diode device includes a substrate having a first conductivity type, a field oxide structure defining a trench structure, a gate structure formed in the trench structure and a doped region having a second conductivity type adjacent to the gate structure in the substrate. An ohmic contact and a Schottky contact are formed at different sides of the gate structure. The method for manufacturing such diode device includes several ion-implanting steps to form several doped sub-regions with different implantation depths to constitute the doped regions. The formed MOS P-N junction Schottky diode device has low forward voltage drop, low reverse leakage current, fast reverse recovery time and high reverse voltage tolerance.
    Type: Grant
    Filed: April 21, 2009
    Date of Patent: August 5, 2014
    Assignee: PFC Device Corp.
    Inventors: Kuo-Liang Chao, Hung-Hsin Kuo, Tse-Chuan Su
  • Patent number: 8685848
    Abstract: A silicon oxide film is formed on an epitaxial layer by dry thermal oxidation, an ohmic electrode is formed on a back surface of a SiC substrate, an ohmic junction is formed between the ohmic electrode and the back surface of the SiC substrate by annealing the SiC substrate, the silicon oxide film is removed, and a Schottky electrode is formed on the epitaxial layer. Then, a sintering treatment is performed to form a Schottky junction between the Schottky electrode and the epitaxial layer.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: April 1, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshinori Matsuno, Yoichiro Tarui
  • Patent number: 8685849
    Abstract: A semiconductor device in one embodiment includes a depletion junction, a peripheral region adjacent the depletion junction, and a buffer layer. The buffer layer is adapted to reduce localization of avalanche breakdown proximate the interface between the depletion junction and the peripheral region.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: April 1, 2014
    Assignee: Siliconix Technology C. V. IR
    Inventors: Andrea Irace, Giovanni Breglio, Paolo Spirito, Andrea Bricconi, Diego Raffo, Luigi Merlin
  • Patent number: 8642468
    Abstract: Embodiments of the invention generally provide methods for depositing metal-containing materials and compositions thereof. The methods include deposition processes that form metal, metal carbide, metal silicide, metal nitride, and metal carbide derivatives by a vapor deposition process, including thermal decomposition, CVD, pulsed-CVD, or ALD.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: February 4, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Seshadri Ganguli, Srinivas Gandikota, Yu Lei, Xinliang Lu, Sang Ho Yu, Hoon Kim, Paul F. Ma, Mei Chang, Maitreyee Mahajani, Patricia M. Liu
  • Patent number: 8618626
    Abstract: A trench Schottky rectifier device includes a substrate having a first conductivity type, a plurality of trenches formed in the substrate, and an insulating layer formed on sidewalls of the trenches. The trenches are filled with conductive structure. There is an electrode overlying the conductive structure and the substrate, and thus a Schottky contact forms between the electrode and the substrate. A plurality of embedded doped regions having a second conductivity type are formed in the substrate and located under the trenches. Each doped region and the substrate form a PN junction to pinch off current flowing toward the Schottky contact so as to suppress current leakage.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: December 31, 2013
    Assignee: PFC Device Corporation
    Inventors: Kou-Liang Chao, Mei-Ling Chen, Tse-Chuan Su, Hung-Hsin Kuo
  • Publication number: 20130292790
    Abstract: A semiconductor device includes a semiconductor layer and a Schottky electrode, a Schottky junction being formed between the semiconductor layer and the Schottky electrode. The Schottky electrode includes a metal part containing a metal, a Schottky junction being formed between the semiconductor layer and the metal part; and a nitride part around the metal part, the nitride part containing a nitride of the metal, and a Schottky junction being formed between the semiconductor layer and the nitride part.
    Type: Application
    Filed: June 28, 2013
    Publication date: November 7, 2013
    Inventors: Yuichi Minoura, NAOYA OKAMOTO
  • Publication number: 20130149850
    Abstract: A method for manufacturing a semiconductor device includes the steps of preparing a substrate made of silicon carbide and having an n type region formed to include a main surface, forming a p type region in a region including the main surface, forming an oxide film on the main surface across the n type region and the p type region, by heating the substrate having the p type region formed therein at a temperature of 1250° C. or more, removing the oxide film to expose at least a part of the main surface, and forming a Schottky electrode in contact with the main surface that has been exposed by removing the oxide film.
    Type: Application
    Filed: November 6, 2012
    Publication date: June 13, 2013
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventor: Sumitomo Electric Industries, Ltd.
  • Patent number: 8445370
    Abstract: A method for manufacturing a Schottky diode comprising steps of 1) providing a region with a dopant of a second conductivity type opposite to a first conductivity type to form a top doped region in a semiconductor substrate of said first conductivity type; 2) providing a trench through the top doped region to a predetermined depth and providing a dopant of the second conductivity type to form a bottom dopant region of the second conductivity type; and 3) lining a Schottky barrier metal layer on a sidewall of the trench at least extending from a bottom of the top doped region to a top of the bottom doped region.
    Type: Grant
    Filed: June 14, 2010
    Date of Patent: May 21, 2013
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Sik K Lui, Anup Bhalla
  • Publication number: 20130115765
    Abstract: A semiconductor device in one embodiment includes a depletion junction, a peripheral region adjacent the depletion junction, and a buffer layer. The buffer layer is adapted to reduce localization of avalanche breakdown proximate the interface between the depletion junction and the peripheral region.
    Type: Application
    Filed: September 25, 2012
    Publication date: May 9, 2013
    Applicant: SILICONIX TECHNOLOGY C.V.IR
    Inventor: SILICONIX TECHNOLOGY C.V.IR
  • Patent number: 8377811
    Abstract: An object of the invention is to provide a method for manufacturing a silicon carbide semiconductor device having constant characteristics with reduced variations in forward characteristics. The method for manufacturing the silicon carbide semiconductor device according to the invention includes the steps of: (a) preparing a silicon carbide substrate; (b) forming an epitaxial layer on a first main surface of the silicon carbide substrate; (c) forming a protective film on the epitaxial layer; (d) forming a first metal layer on a second main surface of the silicon carbide substrate; (e) applying heat treatment to the silicon carbide substrate at a predetermined temperature to form an ohmic junction between the first metal layer and the second main surface of the silicon carbide substrate; (f) removing the protective film; (g) forming a second metal layer on the epitaxial layer; and (h) applying heat treatment to the silicon carbide substrate at a temperature from 400° C. to 600° C.
    Type: Grant
    Filed: August 8, 2008
    Date of Patent: February 19, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshinori Matsuno, Kenichi Ohtsuka, Kenichi Kuroda, Shozo Shikama, Naoki Yutani
  • Publication number: 20130015550
    Abstract: A semiconductor junction barrier Schottky (JBS-SKY) diode with enforced upper contact structure (EUCS) is disclosed. Referencing an X-Y-Z coordinate, the JBS-SKY diode has semiconductor substrate (SCST) parallel to X-Y plane. Active device zone (ACDZ) atop SCST and having a JBS-SKY diode with Z-direction current flow. Peripheral guarding zone (PRGZ) atop SCST and surrounding the ACDZ. The ACDZ has active lower semiconductor structure (ALSS) and enforced active upper contact structure (EUCS) atop ALSS. The EUC has top contact metal (TPCM) extending downwards and in electrical conduction with bottom of EUCS; and embedded bottom supporting structure (EBSS) inside TPCM and made of a hard material, the EBSS extending downwards till bottom of the EUCS. Upon encountering bonding force onto TPCM during packaging of the JBS-SKY diode, the EBSS enforces the EUCS against an otherwise potential micro cracking of the TPCM degrading the leakage current of the JBS-SKY diode.
    Type: Application
    Filed: July 15, 2011
    Publication date: January 17, 2013
    Inventors: Anup Bhalla, Ji Pan, Daniel Ng
  • Patent number: 8324704
    Abstract: A silicon carbide semiconductor device with a Schottky barrier diode includes a first conductivity type silicon carbide substrate, a first conductivity type silicon carbide drift layer on a first surface of the substrate, a Schottky electrode forming a Schottky contact with the drift layer, and an ohmic electrode on a second surface of the substrate. The Schottky electrode includes an oxide layer in direct contact with the drift layer. The oxide layer is made of an oxide of molybdenum, titanium, nickel, or an alloy of at least two of these elements.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: December 4, 2012
    Assignees: DENSO CORPORATION, Toyota Jidosha Kabushiki Kaisha
    Inventors: Takeo Yamamoto, Takeshi Endo, Eiichi Okuno, Hirokazu Fujiwara, Masaki Konishi, Takashi Katsuno, Yukihiko Watanabe
  • Patent number: 8304332
    Abstract: A method for fabrication of a field effect transistor gate, with or without field plates, includes the steps of defining a relatively thin Schottky metal layer by a lithography/metal liftoff or metal deposition/etch process on a semiconductor surface. This is followed by depositing a dielectric passivation layer over the entire wafer and defining a second lithographic pattern coincident with or slightly inset from the boundaries of the previously defined metal gate layer. This is followed by etching the dielectric using dry or wet etching techniques and stripping the resist, followed by exposing and developing a third resist pattern to define the thicker gate metal layers required for electrical conductivity and also for the field plate if one is utilized. The final step is depositing gate and/or field plate metal, resulting in a gate electrode and an integral field plate.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: November 6, 2012
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Anthony A. Immorlica, Pane-chane Chao, Kanin Chu
  • Patent number: 8278199
    Abstract: Reliability of a semiconductor element and its product yield are improved by reducing variations in the electrical characteristic of a metal silicide layer. After forming a nickel-platinum alloy film over a semiconductor substrate, by carrying out a first thermal treatment at a thermal treatment temperature of 210 to 310° C. using a heater heating device, the technique causes the nickel-platinum alloy film and silicon to react with each other to form a platinum-added nickel silicide layer in a (PtNi)2Si phase. After removing unreacted nickel-platinum alloy film, the technique carries out a second thermal treatment having the thermal treatment temperature higher than that of the first thermal treatment to form the platinum-added nickel silicide layer in a PtNiSi phase. The temperature rise rate of each thermal treatment is set to 10° C./s or more.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: October 2, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Shigenari Okada, Takuya Futase, Yutaka Inaba
  • Patent number: 8237172
    Abstract: A semiconductor device according to the present invention includes: a silicon carbide substrate (11) that has a principal surface and a back surface; a semiconductor layer (12), which has been formed on the principal surface of the silicon carbide substrate; and a back surface ohmic electrode layer (1d), which has been formed on the back surface of the silicon carbide substrate. The back surface ohmic electrode layer (1d) includes: a reaction layer (1da), which is located closer to the back surface of the silicon carbide substrate and which includes titanium, silicon and carbon; and a titanium nitride layer (1db), which is located more distant from the back surface of the silicon carbide substrate.
    Type: Grant
    Filed: October 24, 2008
    Date of Patent: August 7, 2012
    Assignee: Panasonic Corporation
    Inventors: Masao Uchida, Kazuya Utsunomiya, Masashi Hayashi
  • Publication number: 20120129328
    Abstract: A semiconductor device formed on a semiconductor substrate may include a component formed in a contact trench located in an active cell region. The component may comprise a barrier metal deposited on a bottom and portions of sidewalls of the contact trench and a tungsten plug deposited in a remaining portion of the contact trench. The barrier metal may comprise first and second metal layers. The first metal layer may be proximate to the sidewall and the bottom of the contact trench. The first metal layer may include a nitride. The second metal layer may be between the first metal layer and the tungsten plug and between the tungsten plug and the sidewall. The second metal layer covers portions of the sidewalls of not covered by the first metal layer.
    Type: Application
    Filed: January 30, 2012
    Publication date: May 24, 2012
    Applicant: ALPHA & OMEGA SEMICONDUCTOR, INC.
    Inventors: Hong Chang, John Chen, Limin Weng, Wenjun Li
  • Patent number: 8143655
    Abstract: A fabrication process for a trench Schottky diode with differential oxide thickness within the trenches includes forming a first nitride layer on a substrate surface and subsequently forming a plurality of trenches in the substrate including, possibly, a termination trench. Following a sacrificial oxide layer formation and removal, sidewall and bottom surfaces of the trenches are oxidized. A second nitride layer is then applied to the substrate and etched such that the second nitride layer covers the oxide layer on the trench sidewalls but exposes the oxide layer on the trench bottom surfaces. The trench bottom surfaces are then re-oxidized and the remaining second nitride layer then removed from the sidewalls, resulting in an oxide layer of varying thickness being formed on the sidewall and bottom surfaces of each trench. The trenches are then filled with a P type polysilicon, the first nitride layer removed, and a Schottky barrier metal applied to the substrate surface.
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: March 27, 2012
    Assignee: International Rectifier Corporation
    Inventor: Davide Chiola
  • Patent number: 8110489
    Abstract: Embodiments of the invention described herein generally provide methods and apparatuses for forming cobalt silicide layers, metallic cobalt layers, and other cobalt-containing materials. In one embodiment, a method for forming a cobalt silicide containing material on a substrate is provided which includes exposing a substrate to at least one preclean process to expose a silicon-containing surface, depositing a cobalt silicide material on the silicon-containing surface, depositing a metallic cobalt material on the cobalt silicide material, and depositing a metallic contact material on the substrate. In another embodiment, a method includes exposing a substrate to at least one preclean process to expose a silicon-containing surface, depositing a cobalt silicide material on the silicon-containing surface, expose the substrate to an annealing process, depositing a barrier material on the cobalt silicide material, and depositing a metallic contact material on the barrier material.
    Type: Grant
    Filed: April 11, 2007
    Date of Patent: February 7, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Seshadri Ganguli, Schubert S. Chu, Mei Chang, Sang-Ho Yu, Kevin Moraes, See-Eng Phan
  • Patent number: 8084342
    Abstract: A CMOS device and method of manufacture is provided for producing an integrated circuit that is not susceptible to various soft errors such as single-event upsets, multi-bit upsets or single-event latchup. The CMOS device and method utilizes a new and novel well architecture in conjunction with metal source/drain electrodes to eliminate soft errors. In one embodiment, the CMOS device uses a first metal source/drain material for the NMOS device and a second metal source/drain material for the PMOS device. The CMOS device further uses a multi-layered well-structure with a shallow N-well and a buried P-well for the PMOS device and a shallow P-well and a buried N-well for the NMOS device.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: December 27, 2011
    Assignee: Avolare 2, LLC
    Inventors: John P. Snyder, John M. Larson
  • Patent number: 8039378
    Abstract: To provide a technique capable of improving the reliability of a semiconductor element and its product yield by reducing the variations in the electrical characteristic of a metal silicide layer. After forming a nickel-platinum alloy film over a semiconductor substrate 1, by carrying out a first thermal treatment at a thermal treatment temperature of 210 to 310° C. using a heater heating device, the technique causes the nickel-platinum alloy film and silicon to react with each other to form a platinum-added nickel silicide layer in a (PtNi)2Si phase. Subsequently, after removing the unreacted nickel-platinum alloy film, the technique carries out a second thermal treatment having the thermal treatment temperature higher than that of the first thermal treatment to form the platinum-added nickel silicide layer in a PtNiSi phase. The temperature rise rate of the first thermal treatment is set to 10° C./s or more (for example, 30 to 250° C.
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: October 18, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Shigenari Okada, Takuya Futase, Yutaka Inaba
  • Patent number: 8003504
    Abstract: A method for fabrication of a field effect transistor gate, with or without field plates, includes the steps of defining a relatively thin Schottky metal layer by a lithography/metal liftoff or metal deposition/etch process on a semiconductor surface. This is followed by depositing a dielectric passivation layer over the entire wafer and defining a second lithographic pattern coincident with or slightly inset from the boundaries of the previously defined metal gate layer. This is followed by etching the dielectric using dry or wet etching techniques and stripping the resist, followed by exposing and developing a third resist pattern to define the thicker gate metal layers required for electrical conductivity and also for the field plate if one is utilized. The final step is depositing gate and/or field plate metal, resulting in a gate electrode and an integral field plate.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: August 23, 2011
    Assignees: BAE Systems Information and Electronic Systems Integration Inc., Biogen IDEC MA Inc.
    Inventors: Anthony A. Immorlica, Pane-chane Chao, Kanin Chu
  • Patent number: 7981785
    Abstract: A polysilicon electrode layer (103) (a first electrode layer) is formed by forming a polysilicon film on a gate oxide film (102) on a silicon wafer (101). A tungsten layer (105) (a second electrode layer) is formed on this polysilicon electrode layer (103). In addition, a barrier layer (104) is formed on the polysilicon electrode layer (103) before the formation of the tungsten layer (105). Etching is then conducted using a silicon nitride layer (106) as the etching mask. Next, an oxide insulating film (107) is formed on an exposed surface of the polysilicon layer (103) by plasma oxidation wherein a process gas containing oxygen gas and hydrogen gas is used at a process temperature not less than 300° C. With this method, a selective oxidation of the polysilicon electrode layer (103) can be carried out without oxidizing the tungsten layer (105).
    Type: Grant
    Filed: March 1, 2004
    Date of Patent: July 19, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Masaru Sasaki, Yoshiro Kabe
  • Patent number: 7955961
    Abstract: A trench-type Schottky semiconductor device and a method for fabricating the trench-type Schottky semiconductor device are disclosed. The method includes the steps of forming an epitaxial (EPI) layer atop a silicon substrate, forming a nitride layer atop the EPI layer, patterning a plurality of windows in the nitride layer into an active region and a termination region, forming a plurality of trenches in the active and termination regions such that the plurality of trenches in the termination regions are spaced apart from each other so as to form a plurality of mesas, lining the first type of trenches with a gate oxide layer, and converting the mesas to oxide mesas; and then applying a barrier layer metal to the mesas in the device active area and in the termination trenches.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: June 7, 2011
    Assignee: International Rectifier Corporation
    Inventor: Giovanni Richieri
  • Patent number: 7923362
    Abstract: A method for manufacturing a metal-semiconductor contact in semiconductor Components is disclosed. There is a relatively high risk of contamination in the course of metal depositions in prior-art methods. In the disclosed method, the actual metal -semiconductor or Schottky contact is produced only after the application of a protective layer system, as a result of which it is possible to use any metals, particularly platinum, without the risk of contamination.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: April 12, 2011
    Assignee: TELEFUNKEN Semiconductors GmbH & Co. KG
    Inventors: Franz Dietz, Volker Dudek, Tobias Florian, Michael Graf
  • Patent number: 7902054
    Abstract: A silicon carbide Schottky barrier semiconductor device provided with a Ta electrode as a Schottky electrode, in which the Schottky barrier height is controlled to a desired value in a range where power loss is minimized without increasing the n factor. The method for manufacturing the silicon carbide Schottky barrier semiconductor device includes the steps of depositing Ta on a crystal face of an n-type silicon carbide epitaxial film, the crystal face having an inclined angle in the range of 0° to 10° from a (000-1) C face, and carrying out a thermal treatment at a temperature range of 300 to 1200° C. to form the Schottky electrode.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: March 8, 2011
    Assignee: Central Research Institute of Electric Power Industry
    Inventors: Hidekazu Tsuchida, Tomonori Nakamura, Toshiyuki Miyanagi
  • Patent number: 7902056
    Abstract: Devices and methods for plasma treated metal silicide layer formation are disclosed. In one embodiment, a method for manufacturing a semiconductor device comprises forming a metal layer on a silicon substrate, exposing the metal layer to a plasma, and thermally treating the silicon substrate and the metal layer to form a metal silicide layer.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: March 8, 2011
    Assignee: Spansion LLC
    Inventors: Takayuki Enda, Tatsuya Inoue, Naoki Takeguchi
  • Patent number: 7879705
    Abstract: A method is set forth of forming an ohmic electrode having good characteristics on a SiC semiconductor layer. In the method, a Ti-layer and an Al-layer are formed on a surface of the SiC substrate. The SiC substrate having the Ti-layer and the Al-layer is maintained at a temperature that is higher than or equal to a first temperature and lower than a second temperature until all Ti in the Ti-layer has reacted with Al. The first temperature is the minimum temperature of a temperature zone at which the Ti reacts with the Al to form Al3Ti, and the second temperature is the minimum temperature of a temperature zone at which the Al3Ti reacts with SiC to form Ti3SiC2. As a result of this maintaining of temperature step, an Al3Ti-layer is formed on the surface of the SiC substrate. The method also comprises further heating the SiC substrate having the Al3Ti-layer to a temperature that is higher than the second temperature.
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: February 1, 2011
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Akira Kawahashi, Masahiro Sugimoto, Akinori Seki, Masakatsu Maeda, Yasuo Takahashi
  • Patent number: 7868360
    Abstract: There are disclosed TFTs that have excellent characteristics and can be fabricated with a high yield. The TFTs are fabricated, using an active layer crystallized by making use of nickel. Gate electrodes are comprising tantalum. Phosphorus is introduced into source/drain regions. Then, a heat treatment is performed to getter nickel element in the active layer and to drive it into the source/drain regions. At the same time, the source/drain regions can be annealed out. The gate electrodes of tantalum can withstand this heat treatment.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: January 11, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Publication number: 20100258897
    Abstract: A method for manufacturing a Schottky diode comprising steps of 1) providing a region with a dopant of a second conductivity type opposite to a first conductivity type to form a top doped region in a semiconductor substrate of said first conductivity type; 2) providing a trench through the top doped region to a predetermined depth and providing a dopant of the second conductivity type to form a bottom dopant region of the second conductivity type; and 3) lining a Schottky barrier metal layer on a sidewall of the trench at least extending from a bottom of the top doped region to a top of the bottom doped region.
    Type: Application
    Filed: June 14, 2010
    Publication date: October 14, 2010
    Inventors: Sik K. Lui, Anup Bhalla
  • Patent number: 7777292
    Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type having a top surface and a bottom surface, a semiconductor layer of a first conductivity type formed on the top surface of the semiconductor substrate, and having an active region and an edge termination region surrounding the active region, a first semiconductor region of a second conductivity type formed in the edge termination region adjacent to an edge of the active region, a second semiconductor region of a second conductivity type buried in the edge termination region in a sheet shape or a mesh shape substantially in parallel with a surface of the semiconductor layer, a first electrode formed on the active region of the semiconductor layer and a part of the first semiconductor region, and a second electrode formed on the bottom surface of the semiconductor substrate.
    Type: Grant
    Filed: June 25, 2007
    Date of Patent: August 17, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chiharu Ota, Johji Nishio, Tetsuo Hatakeyama, Takashi Shinohe
  • Publication number: 20100164050
    Abstract: A high-voltage Schottky diode including a deep P-well having a first width is fanned on the semiconductor substrate. A doped P-well is disposed over the deep P-well and has a second width that is less than the width of the deep P-well. An M-type guard ring is formed around the upper surface of the second doped well, A Schottky metal is disposed on an upper surface of the second doped well and the N-type guard ring.
    Type: Application
    Filed: December 31, 2008
    Publication date: July 1, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Dah-Chuen HO, Chien-Shao TANG, Yu-Chang JONG, Zhe-Yi WANG
  • Patent number: 7745316
    Abstract: Provided is a method for fabricating a Schottky barrier tunnel transistor (SBTT) that can fundamentally prevent the generation of a gate leakage current caused by damage of spacers formed on both sidewalls of a gate electrode. The method for fabricating a Schottky barrier tunnel transistor, which includes: a) forming a silicon pattern and a sacrificial pattern on a buried oxide layer supported by a support substrate; b) forming a source/drain region on the buried oxide layer exposed on both sides of the silicon pattern, the source/drain region being formed of a metal layer and being in contact with both sidewalls of the silicon pattern; c) removing the sacrificial pattern to expose the top surface of the silicon pattern; and d) forming a gate insulating layer and a gate electrode on the exposed silicon pattern.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: June 29, 2010
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Yark-Yeon Kim, Seong-Jae Lee, Moon-Gyu Jang, Tae-Youb Kim, Chel-Jong Choi, Myung-Sim Jun, Byoung-Chul Park
  • Patent number: 7745317
    Abstract: A semiconductor device provided with a silicon carbide semiconductor substrate, and an ohmic metal layer joined to one surface of the silicon carbide semiconductor substrate in an ohmic contact and composed of a metal material whose silicide formation free energy and carbide formation free energy respectively take negative values. The ohmic metal layer is composed of, for example, a metal material such as molybdenum, titanium, chromium, manganese, zirconium, tantalum, or tungsten.
    Type: Grant
    Filed: June 14, 2006
    Date of Patent: June 29, 2010
    Assignee: Rohm Co., Ltd.
    Inventors: Yuji Okamura, Masashi Matsushita
  • Patent number: 7645691
    Abstract: A method for forming an ohmic contact and a zener zap diode in an integrated circuit includes forming a first contact opening in the insulating layer over a first diffusion region to expose the semiconductor substrate; forming a barrier metal layer on the insulating layer and in the first contact opening; forming a second contact opening in the barrier metal layer over a second diffusion region and the insulating layer to expose the semiconductor substrate; forming a third contact opening in the barrier metal layer and the insulating layer over a third diffusion region to expose the semiconductor substrate; forming an aluminum layer on the barrier metal layer and the insulating layer and in the first, second and third contact openings; and patterning the aluminum layer to form the ohmic contact over the first diffusion region and the zener zap diode over the second and third diffusion regions.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: January 12, 2010
    Assignee: Micrel, Inc.
    Inventor: Schyi-yi Wu
  • Patent number: 7629205
    Abstract: A thin film transistor (TFT) that can prevent damage to a silicon layer under a gate electrode in an annealing process by using a first gate electrode having high thermal resistance and a second gate electrode having high reflectance and a method of manufacturing the TFT are provided. The method of manufacturing a TFT includes forming a double-layered gate electrode which includes a first gate electrode formed of a material having high thermal resistance and a second gate electrode formed of a metal having high optical reflectance on the first gate electrode, and forming a source and a drain by annealing doped regions on both sides of a silicon layer under the gate electrode by radiating a laser beam onto the entire upper surface of the silicon layer.
    Type: Grant
    Filed: January 12, 2006
    Date of Patent: December 8, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hans S. Cho, Hyuck Lim, Takashi Noguchi, Jang-yeon Kwon
  • Patent number: 7618884
    Abstract: A Schottky barrier silicon carbide device has a Re Schottky metal contact. The Re contact 27 is thicker than 250 Angstroms and may be between 2000 and 4000 Angstroms. A termination structure is provided by ion milling an annular region around the Schottky contact.
    Type: Grant
    Filed: April 21, 2008
    Date of Patent: November 17, 2009
    Assignee: Fairchild Semiconductor Corporation
    Inventors: William F. Seng, Richard L. Woodin, Carl Anthony Witt
  • Patent number: 7615839
    Abstract: Since VF and IR characteristics of a Schottky barrier diode are in a trade-off relationship, there has heretofore been a problem that an increase in a leak current is unavoidable in order to realize a low VF. Moreover, there has been a known structure which suppresses the leak current in such a manner that a depletion layer is spread by providing P+ regions and a pinch-off effect is utilized. However, in reality, it is difficult to completely pinch off the depletion layer. P+ type regions are provided, and a low VF Schottky metal layer is allowed to come into contact with the P+ type regions and depletion regions therearound. A low IR Schottky metal layer is allowed to come into contact with a surface of a N type substrate between the depletion regions. When a forward bias is applied, a current flows through the metal layer of low VF characteristic. When a reverse bias is applied, a current path narrowed by the depletion regions is formed only in the metal layer portion of low IR characteristic.
    Type: Grant
    Filed: February 16, 2005
    Date of Patent: November 10, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tadaaki Souma, Tadashi Natsume
  • Publication number: 20090230405
    Abstract: A manufacturing method of a diode includes: forming a P type semiconductor film on a N type semiconductor layer with a crystal growth method; forming a first metallic film on the P type semiconductor film so that the first metallic film contacts the P type semiconductor film with an ohmic contact; forming a mask having an opening on the first metallic film; etching a part of the first metallic film and a part of the P type semiconductor film via the opening so that a part of the N type semiconductor layer is exposed; and forming a second metallic film on the part of the N type semiconductor layer so that the second metallic film contacts the N type semiconductor layer with a Schottky contact.
    Type: Application
    Filed: March 13, 2009
    Publication date: September 17, 2009
    Applicant: DENSO CORPORATION
    Inventors: Takeo Yamamoto, Takeshi Endo, Masaki Konishi, Hirokazu Fujiwara, Yukihiko Watanabe, Takashi Katsuno, Masayasu Ishiko
  • Publication number: 20090224355
    Abstract: A semiconductor device in one embodiment includes a depletion junction, a peripheral region adjacent the depletion junction, and a buffer layer. The buffer layer is adapted to reduce localization of avalanche breakdown proximate the interface between the depletion junction and the peripheral region.
    Type: Application
    Filed: March 24, 2008
    Publication date: September 10, 2009
    Applicant: SILICONIX TECHNOLOGY C. V. IR
    Inventors: Andrea Irace, Giovanni Breglio, Paolo Spirito, Andrea Bricconi, Diego Raffo, Luigi Merlin
  • Patent number: 7566642
    Abstract: An n-type SBTT and a manufacturing method thereof are provided. The SBTT includes a silicon layer, a gate, a double layer that has a rare-earth metal silicide layer and a transition metal silicide layer. The silicon layer has a channel region. The gate is formed in an overlapping manner on the channel region and has a gate dielectric layer on its interface with respect to the silicon layer. The double layer is formed as a source/drain that has the channel region interposed on the silicon layer.
    Type: Grant
    Filed: July 22, 2005
    Date of Patent: July 28, 2009
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Yark Yeon Kim, Moon Gyu Jang, Jae Heon Shin, Seong Jae Lee
  • Publication number: 20090166795
    Abstract: A method includes forming a first conductive type buried layer on a semiconductor substrate, forming a second conductive type epi-layer on the semiconductor substrate using an epitaxial growth method such that the epi-layer surrounds the buried layer, forming a first conductive type plug from the surface of the semiconductor substrate to the buried layer, forming a first conductive type well, which is horizontally spaced from the first conductive type plug, from the surface of the semiconductor substrate to the buried layer, and forming a plurality of metal contacts as an anode and cathode of the schottky diode, respectively, by making electrical connection to the well and plug.
    Type: Application
    Filed: December 28, 2008
    Publication date: July 2, 2009
    Inventor: Chul-Jin Yoon