Abstract: A method includes forming a first conductive type buried layer on a semiconductor substrate, forming a second conductive type epi-layer on the semiconductor substrate using an epitaxial growth method such that the epi-layer surrounds the buried layer, forming a first conductive type plug from the surface of the semiconductor substrate to the buried layer, forming a first conductive type well, which is horizontally spaced from the first conductive type plug, from the surface of the semiconductor substrate to the buried layer, and forming a plurality of metal contacts as an anode and cathode of the schottky diode, respectively, by making electrical connection to the well and plug.

Abstract: A semiconductor fabrication method includes forming a gate module overlying a substrate. Recesses are etched in the substrate using the gate module as a mask. A barrier layer is deposited over the wafer and anisotropically etched to form barrier “curtains” on sidewalls of the source/drain recesses. A metal layer is deposited wherein the metal layer contacts a semiconductor within the recess. The wafer is annealed to form a silicide selectively. The diffusivity of the metal with respect to the barrier structure material is an order of magnitude less than the diffusivity of the metal with respect to the semiconductor material. The etched recesses may include re-entrant sidewalls. The metal layer may be a nickel layer and the barrier layer may be a titanium nitride layer. Silicon or silicon germanium epitaxial structures may be formed in the recesses overlying the semiconductor substrate.

Abstract: A silicon carbide Schottky barrier semiconductor device provided with a Ta electrode as a Schottky electrode, in which the Schottky barrier height is controlled to a desired value in a range where power loss is minimized without increasing the n factor. The method for manufacturing the silicon carbide Schottky barrier semiconductor device includes the steps of depositing Ta on a crystal face of an n-type silicon carbide epitaxial film, the crystal face having an inclined angle in the range of 0° to 10° from a (000-1) C face, and carrying out a thermal treatment at a temperature range of 300 to 1200° C. to form the Schottky electrode.

Abstract: A semiconductor structure in which the contact resistance in the contact opening is reduced as well as a method of forming the same are provided. This is achieved in the present invention by replacing conventional contact metallurgy, such as tungsten, or a metal silicide, such as Ni silicide or Cu silicide, with a metal germanide-containing contact material. The term “metal germanide-containing” is used in the present application to denote a pure metal germanide (i.e., MGe alloy) or a metal germanide that includes Si (i.e., MSiGe alloy).

Abstract: A power Schottky rectifier device and method of making the same are disclosed. The Schottky rectifier device includes a LOCOS structure grown on the bottom of the trenches by using nitride spacer on the sidewall of the trenches as a thermal oxidation mask. A polycrystalline silicon layer is then filled the first trenches. Under LOCOS structure, a p doped region is optionally formed to minimize the current leakage when the device undergoes a reverse biased. A Schottky barrier silicide layer formed by sputtering and annealing steps is formed on the upper surfaces of the epi-layer and the polycrystalline silicon layer. A top metal layer served as anode is then formed on the Schottky barrier silicide layer and extended to cover a portion of field oxide region of the termination trench. A metal layer served as a cathode electrode is then formed on the backside surface of the substrate opposite to the top metal layer.

Abstract: The present invention relates to a bit line barrier metal layer for a semiconductor device and a process for preparing the same, the process comprising: forming bit line contact on an insulation layer vapor-deposited on an upper part of a substrate so as to expose an ion implantation region; vapor-depositing a first barrier metal layer of a Ti film on the entire upper surface thereof; and vapor-depositing, on the upper part of the Ti film, a second barrier metal layer of a ZrB2 film having different upper and lower Boron concentrations, by RPECVD controlling the presence/absence of H2 plasma, wherein the barrier metal layer includes the Ti film, lower ZrB2 film and upper a ZrB2 film sequentially stacked between tungsten bit lines and ion implantation region of a semiconductor substrate.

Abstract: Under one aspect, a method of making a nanotube switch includes: providing a substrate having a first conductive terminal; depositing a multilayer nanotube fabric over the first conductive terminal; and depositing a second conductive terminal over the multilayer nanotube fabric, the nanotube fabric having a thickness, density, and composition selected to prevent direct physical and electrical contact between the first and second conductive terminals. In some embodiments, the first and second conductive terminals and the multilayer nanotube fabric are lithographically patterned so as to each have substantially the same lateral dimensions, e.g., to each have a substantially circular or rectangular lateral shape. In some embodiments, the multilayer nanotube fabric has a thickness from 10 nm to 200 nm, e.g., 10 nm to 50 nm. The structure may include an addressable diode provided under the first conductive terminal or deposited over the second terminal.

Abstract: In the method of fabricating a metal-insulator-metal (MIM) device, a first electrode of ?-Ta is provided. The Ta of the first electrode is oxidized to form a Ta2O5 layer on the first electrode. A second electrode of ?-Ta is provided on the Ta2O5 layer. Such a device exhibits strong data retention, along with resistance to performance degradation under high temperatures.

Abstract: A method for manufacturing a memory device having a metal nanocrystal charge storage structure. A substrate is provided and a first layer of dielectric material is grown on the substrate. A layer of metal oxide having a first heat of formation is formed on the first layer of dielectric material. A metal layer having a second heat of formation is formed on the metal oxide layer. The second heat of formation is greater than the first heat of formation. The metal oxide layer and the metal layer are annealed which causes the metal layer to reduce the metal oxide layer to metallic form, which then agglomerates to form metal islands. The metal layer becomes oxidized thereby embedding the metal islands within an oxide layer to form a nanocrystal layer. A control oxide is formed over the nanocrystal layer and a gate electrode is formed on the control oxide.

Abstract: There are disclosed TFTs that have excellent characteristics and can be fabricated with a high yield. The TFTs are fabricated, using an active layer crystallized by making use of nickel. Gate electrodes are comprising tantalum. Phosphorus is introduced into source/drain regions. Then, a heat treatment is performed to getter nickel element in the active layer and to drive it into the source/drain regions. At the same time, the source/drain regions can be annealed out. The rate electrodes of tantalum can withstand this heat treatment.

Abstract: A fabrication process for a trench Schottky diode with differential oxide thickness within the trenches includes forming a first nitride layer on a substrate surface and subsequently forming a plurality of trenches in the substrate including, possibly, a termination trench. Following a sacrificial oxide layer formation and removal, sidewall and bottom surfaces of the trenches are oxidized. A second nitride layer is then applied to the substrate and etched such that the second nitride layer covers the oxide layer on the trench sidewalls but exposes the oxide layer on the trench bottom surfaces. The trench bottom surfaces are then re-oxidized and the remaining second nitride layer then removed from the sidewalls, resulting in an oxide layer of varying thickness being formed on the sidewall and bottom surfaces of each trench. The trenches are then filled with a P type polysilicon, the first nitride layer removed, and a Schottky barrier metal applied to the substrate surface.

Abstract: The invention, in one aspect, provides a method of manufacturing a semiconductor device. This method includes providing a semiconductor substrate and depositing a metal layer over the semiconductor substrate that has an overall thickness of about 1 micron or greater. The metal layer is formed by depositing a first portion of the thickness of the metal layer, which has a compressive or tensile stress associated therewith over the semiconductor substrate. A stress-compensating layer is deposited over the first portion, such that the stress-compensating layer imparts a stress to the first portion that is opposite to the compressive or tensile stress associated with the first portion. A second portion of the thickness of the metal layer is then deposited over the stress-compensating layer.

Abstract: A method is provided to clean slurry particles from a surface in which tungsten and dielectric are coexposed after a dielectric CMP step. Such a surface is formed when tungsten features are patterned and etched, the tungsten features are covered with dielectric, and the dielectric is planarized to expose tops of the tungsten features. The surface to be cleaned is subjected to mechanical action in an acid environment. Suitable mechanical action includes performing a brief tungsten CMP step on the tungsten features or scrubbing the surface using, for example, a commercial post-CMP scrubber.

Abstract: A method for sealing an exposed surface of a wire bond pad with a material that is capable of preventing a possible chemical attack during electroless deposition of Ni/Au pad metallurgy is provided. Specifically, the present invention provides a method whereby a TiN/Ti or TiN/Al cap is used as a protective coating covering exposed surfaces of a wire bond pad. The TiN/Ti or TiN/Al cap is not affected by alkaline chemistries used in forming the Ni/Au metallization, yet it provides a sufficient electrical pathway connecting the bond pads to the Ni/Au pad metallization.

Abstract: A method of sputtering a Ta layer comprised of alpha phase Ta on a Cu layer. An embodiment includes a Ta sputter deposition on a Cu surface at a substrate temperature less than 200° C. Another embodiment has a pre-cooling step at a temperature less than 100° C. prior to Ta layer sputter deposition. In another non-limiting example embodiment, a pre-clean step comprising an inert gas sputter is performed prior to the tantalum sputter. Another non-limiting example embodiment provides a semiconductor structure comprising: a semiconductor structure; a copper layer over the semiconductor structure; a tantalum layer on the copper layer; the tantalum layer comprised alpha phase Ta; a metal layer on the tantalum layer.

Abstract: A method of fabricating a non-volatile memory cell on a semiconductor substrate is disclosed. An area of a first region of the semiconductor substrate designated for a layer of floating polysilicon is blocked while a second region of the semiconductor substrate designated for a layer of non-floating polysilicon is exposed. Exposed regions of the semiconductor substrate are doped with charges.

Abstract: A method is provided for producing a solid-state imaging device in which a plurality of pixels are arranged two-dimensionally so as to form a photosensitive region, each of the pixels including a photodiode that photoelectrically converts incident light to store a signal charge and read-out elements for reading out the signal charge from the photodiode, and a vertical driving circuit for driving the plurality of pixels in the photosensitive region in a row direction, a horizontal driving circuit for driving the same in a column direction and an amplify circuit for amplifying an output signal are formed with MOS transistors. The method includes: forming an element isolation region with a STI (Shallow Trench Isolation) structure between the plurality of photodiodes and the plurality of MOS transistors; and forming a gate oxide film of the MOS transistors to have a thickness of 10 nm or less.

Abstract: A semiconductor device includes: a gate electrode formed on a silicon substrate; source/drain regions formed at both sides of the gate electrode in the silicon substrate; and a silicide layer formed on the source/drain regions. The silicide layer includes a first silicide layer mainly made of a metal silicide having a formation enthalpy lower than that of NiSi and a second silicide layer formed on the first silicide and made of Ni silicide.

Abstract: A problem in related art according to which an increase in leak current cannot be avoided in order to obtain a low forward voltage VF as forward voltage VF and reverse leak current IR characteristics of a Schottky barrier diode are in a trade-off relationship is hereby solved by forming a Schottky barrier diode using a metal layer comprising a Schottky metal layer of Ti including a small amount of Al. Consequently, a low reverse leak current IR can be obtained without causing a large increase in the forward voltage VF of pure Ti such that power consumption can be reduced by suppressing forward power loss and decreasing reverse power loss.

Abstract: Methods of making a semiconductor structure are disclosed. A refractory metal layer containing W, TiW, Ta, or TaN and semiconductor layer are formed on a substrate that contains copper in, for example, a via therein. A portion of the refractory metal layer and semiconductor layer is removed by etching using a fluorine-containing compound. By using W, TiW, Ta, or TaN as the refractory metal layer material and employing fluorine-based etching, the copper portion in the substrate is not substantially etched, thus preventing corrosion of the copper portion.

Abstract: A filter having a thin-film resonator fabricated on a semiconductor substrate and a method of making the same are disclosed. The filter has a bonding pad connected to the resonator and in contact with the substrate to form a Schottky diode with the substrate to protect the resonator from electrostatic discharges.

Abstract: A process is described which allows a buried, retrograde doping profile or a delta doping to be produced in a relatively simple and inexpensive way. The process uses individual process steps that are already used in the mass production of integrated circuits and accordingly can be configured for a high throughput.

Abstract: A process is provided for depositing an undoped silicon oxide film on a substrate disposed in a process chamber. A process gas that includes SiF4, a fluent gas, a silicon source, and an oxidizing gas reactant is flowed into the process chamber. A plasma having an ion density of at least 1011 ions/cm3 is formed from the process gas. The undoped silicon oxide film is deposited over the substrate with the plasma using a process that has simultaneous deposition and sputtering components.

Abstract: The present invention provides method of manufacturing a metal-insulator-metal capacitor (100). A method of manufacturing includes depositing a first refractory metal layer (105) over a semiconductor substrate (110). The first refractory metal layer (105) over a capacitor region (200) of the semiconductor substrate (110) is removed and a second refractory metal (300) is deposited over the capacitor region (200). Other aspects of the present invention include a metal-insulator-metal capacitor (900) and a method of manufacturing an integrated circuit (1000).

Abstract: A method for treating a surface on an SiC semiconductor body produced by epitaxy. According to the method, the parts of the epitactic layer that are deposited in the final phase of the epitaxy are removed by etching and a wet chemical treatment is then carried out in order to remove a thin natural oxide on the surface. Alternatively, a metal layer configured as a Schottky contact and/or as an ohmic contact can also be applied to the surface immediately after the removal process.

Abstract: A method for manufacturing a metal-oxide-semiconductor transistor prevents the occurrence of a contact spiking phenomenon. The method includes forming a metal thin film and an isolation oxidation film on a semiconductor substrate, and selectively etching the isolation oxidation film such that the isolation oxidation film is left remaining only over a field oxidation film; heat treating the semiconductor substrate to form silicide by the metal thin film in gate, source, and drain regions; removing portions of the metal thin film that is not formed into silicide, that is, removing unreacted metal thin film; removing the isolation oxidation film left remaining on the field oxidation film; and heat treating the semiconductor substrate in an oxygen environment to form the unreacted metal thin film remaining on the field oxidation film into a metal oxidation film. The present invention is related also to a semiconductor device that employs a metal-oxide-semiconductor transistor made using the method.

Abstract: A semiconductor device is disclosed containing a semiconductor die having a trimetal electrode soldered to a substrate by a Sn—Sb solder.

Abstract: A highly localized diffusion barrier is incorporated into a polysilicon line to allow the doping of the polysilicon layer without sacrificing an underlying material layer. The diffusion barrier is formed by depositing a thin polysilicon layer and exposing the layer to a nitrogen-containing plasma ambient. Thereafter, the deposition is resumed to obtain the required final thickness. Moreover, a polysilicon line is disclosed, having a highly localized barrier layer.

Abstract: A method of manufacturing a semiconductor device having an improved ohmic contact system to epitaxially grown, low bandgap compound semiconductors. In an exemplary embodiment, the improved ohmic contact system comprises a thin reactive layer of nickel deposited on a portion of an epitaxially grown N+ doped InGaAs emitter cap layer. The improved ohmic contact system further comprises a thick refractory layer of titanium or other suitable material deposited on the thin reactive layer. Both the reactive layer and the refractory layer are substantially free of gold and other low resistivity, high conductivity metal overlayers.

Abstract: A fabrication process for a Schottky barrier structure includes forming a nitride layer directly on a surface of an epitaxial (“epi”) layer and subsequently forming a plurality of trenches in the epi layer. The interior walls of the trenches are then deposited with a final oxide layer without forming a sacrificial oxide layer to avoid formation of a beak bird at the tops of the interior trench walls. A termination trench is etched in the same process step for forming the plurality of trenches in the active area.

Abstract: Oxidation on the surface of a film of refractory metal constituting a gate electrode (word line WL) is suppressed by forming an insulation film constituting a cap insulation film of the gate electrode (word line WL) at a temperature of 500° C. or lower. Further, oxidation on the surface of the refractory metal film exposed to the side wall of the gate electrode (word line WL) is suppressed by forming an insulation film constituting the side wall spacer of the gate electrode (word line WL) at a temperature of 500° C. or lower.

Abstract: A method of forming inter-level contacts or vias between metal layers using a tungsten film deposited into the via using non-collimated sputter deposition. The sputter chamber is configured with a pressure of about 1 mTorr to about 10 mTorr with an inert gas flow of at least 25 cm3/min to about 150 cm3/min. Shielding inside the chamber is coated with a material, preferably, aluminum oxide, that promotes adhesion of tungsten to the shielding. An adhesion layer of titanium may be included prior to deposition of the tungsten film. Non-collimated sputter deposition increases the target to substrate distance inside the sputter chamber; reduces the heating effect associated with traditional collimated sputtering; and provides more robust diffusion barriers.

Abstract: A method of forming junction isolation to isolate active elements. A substrate having a plurality of active areas and an isolation area between active areas is provided. A first gate structure is formed on part of the substrate located in the active areas and, simultaneously, a second gate structure serving as a dummy gate structure is formed on the substrate located in the isolation area. A first doped region is formed in the substrate located at two sides of the first and the second gate structures. A bottom anti-reflection layer is formed on the substrate, the first gate structure and the second gate structure. Part of the bottom anti-reflection layer is etched to expose the second gate structure. The second gate structure is removed to expose the substrate. A second doped region serving as a junction isolation region is formed in the substrate located in the isolation area.

Abstract: The presently disclosed technology provides a method for forming a structure wherein an electrode, such as a gate, comprising a refractory metal is deposited. The method comprises depositing a plurality of electron sensitive resist layers on the substrate. Several of the resist layers used have properties that allow them to maintain their shape when exposed to the temperatures needed to deposit refractory metals. Using electron beam lithography, several regions are defined in the resist layers that will be removed to create a mold for a gate. By using resist layers which maintain their shape when exposed to the temperatures needed for evaporating a refractory metal, the mold defined in the resist layers will maintain its shape, thereby allowing a gate having a mushroom shape to be formed.

Abstract: A temperature-controlled focus ring assembly for use in a plasma chamber that includes a focus ring surrounding a wafer pedestal for confining plasma ions to a top surface of a wafer positioned on the wafer pedestal; a heat transfer means in intimate contact with the focus ring for decreasing or increasing the temperature of the focus ring; and a controller for controlling the temperature of the focus ring to a predetermined value. The invention further discloses a method for operating a plasma chamber equipped with a temperature-controlled focus ring assembly.

Abstract: A semiconductor device formed on a semiconductor substrate having an active region and a method of making the same is disclosed. The semiconductor device includes a dielectric layer interposed between a gate electrode and the semiconductor substrate. Further, the semiconductor device includes graded dielectric constant spacers formed on sidewalls of the dielectric layer, sidewalls of the gate electrode and portions of an upper surface of the semiconductor substrate. The dielectric constant of the graded dielectric constant spacers decreases in a direction away from the sidewalls of the dielectric layer.

Abstract: A method of ensuring against deterioration of an underlying silicide layer over which a refractory material layer is deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD) is realized by first providing a continuous polysilicon layer prior to the refractory material deposition. The continuous polysilicon layer, preferably no thicker than 50 Å, serves a sacrificial purpose and prevents interaction between any fluorine that is released during the refractory material deposition step from interacting with the underlying silicide.

Abstract: A method of forming silicide, especially in a CMOS device in which polysilicon grains in a p-type gate are re-doped with n-type impurities such as As and the like at a critical implantation dose. This increases the grain size of the polysilicon, which also reduces sheet resistance by securing thermal stability in subsequent process steps thereof. The present invention generally includes forming an undoped polysilicon layer, doping the polysilicon layer with p-type impurity ions, doping the p-doped polysilicon layer with ions that increase the grain size of the polysilicon layer by being heated, forming a metal layer on the twice-doped polysilicon layer, and forming a silicide layer by reacting a portion of the twice-doped polysilicon layer with the metal layer.

Abstract: The method of fabricating a semiconductor device through a salicide process includes the steps of forming a gate electrode and source/drain regions on a semiconductor substrate, and performing only a wet etching; sequentially, entirely, forming a high melting point metal film and a capping film; forming a mono silicide film on the gate electrode and the source/drain regions through a first heat process, and removing the high melting point metal film and the capping film of a region excepting of a region where the mono silicide film is formed; and forming the di-silicide film through a second heat process.

Abstract: A method for forming a metal salicide layer on a shallow junction is described. A substrate having a gate structure thereon and a shallow junction therein is provided. An atomic layer deposition (ALD) process is then performed to deposit a tungsten salicide layer on the shallow junction. In the ALD process, a gaseous silicon-containing compound and a gaseous metal-containing compound that react into metal silicide are introduced alternatively onto the substrate, wherein either compound can be introduced at first. When either compound is introduced at first, the flow rate thereof is controlled so that only a single layer of molecules are adsorbed, while the flow rate of the metal-containing compound is controlled in each case so that few silicon atoms in the substrate are consumed. By repeating the two gas introduction steps, a metal salicide layer constituted of many thin layers is formed on the shallow junction.

Abstract: A process of making a buried digit line stack is disclosed. The process includes forming a silicon-lean metal silicide first film over a polysilicon plug, followed by a silicide compound barrier second film. The silicide compound barrier second film is covered with a refractory metal third film. A salicidation process causes the first film to salicide with the polysilicon plug. In one embodiment, all the aforementioned deposition processes are carried out by physical vapor deposition (“PVD”).

Abstract: A gate electrode, in which the slope of the profile of a gate electrode forming material layer, for example, a refractory metal silicide layer is prevented from being decreased due to thermal expansion by patterning a refractory metal silicide layer after performing a thermal process on a refractory metal silicide layer, thereby having a stable operation characteristic, and a method for manufacturing the same are provided.

Abstract: This invention relates to a method for forming a dielectric layer, more particularly, to a method for forming a silicate dielectric layer. The first step of the present invention is to form a silicate layer on the substrate of the wafer by using a physical vapor deposition (PVD) procedure. The silicate layer is a hafnium silicate (HfSi) layer or a zirconium silicate (ZrSi) layer. Then the silicate layer is treated to become a gate dielectric layer or an inter-layer dielectric layer which has higher a dielectric constant by using a rapid thermal annealing (RTA) procedure in a environment which is filled of nitrogen or ammonia.

Abstract: A first metal film of a first metal is deposited on a silicon-containing film containing silicon as a principal constituent, and a second metal film of a nitride of a second metal is deposited on the first metal film. Thereafter, a metal film with a high melting point is deposited on the second metal film, so as to form a multi-layer film of the silicon-containing film, the first metal film, the second metal film and the metal film with a high melting point. The multi-layer film is then subjected to annealing at a temperature of 750° C. or more. In this case, the first metal is nitrided to be changed into a nitride of the first metal and a silicide layer of the first metal is not formed in a surface portion of the silicon-containing film before the annealing.

Abstract: A method for depositing a two-layer diffusion barrier on a semiconductor wafer consisting of a TaN layer and a Ta layer serving as a carrier layer for copper interconnects. The TaN layer is inventively deposited at temperatures above 200° C. in a first step, and the Ta layer is deposited in a second step while cooling the semiconductor wafer to a temperature below 50° C.

Abstract: A high density plasma chemical vapor deposition (HDP-CVD) process is used to deposit silicon dioxide in trenches of various widths. The thickness of the silicon dioxide filling both narrow and wide trenches is made more uniform by reducing an HDP-CVD etch to deposition ratio. The lowered etch to deposition ratio is achieved by lowering a ratio of oxygen to silane gas, by lowering the power of a high frequency bias signal, and by lowering the total gas flow rate.

Abstract: A method for etching and removing an anti-reflective coating from a substrate. The method comprises providing a substrate supporting a conductive layer (a tungsten-silicide layer) having an anti-reflective coating (e.g., a dielectric anti-reflective coating) disposed thereon. The anti-reflective coating is etched with an etchant gas consisting of NF3 and Cl2 to break through and to remove at least a portion of the anti-reflective coating to expose at least part of the conductive layer. The conductive layer is subsequently etched with the etchant gas to produce an anti-reflective coating gate structure which is used in semiconductor integrated circuits containing transistors.

Abstract: The present invention provides a self-aligned gate transistor. The present invention implants P-type impurity ions only below a channel region below a gate and below a source and drain electrode on semiconductor substrate having an ion implantation channel layer without implanting the P-type impurity ions into a narrow region between the source-gate and the gate-drain, deposits a gate metal and etches the gate pattern. In this case, the length (Lg) of the gate is defined to be narrower than the length (Lch-g) into which P-type impurity ions are implanted below the channel layer, thus improving a pinch-off characteristic. A method of manufacturing a field effect transistor having a self aligned gate according to the present invention comprises the steps of implanting P-type impurity ions only below a channel region below a gate and below a source and drain electrode; and depositing a refractory gate metal having a good high temperature stability to form a gate pattern using a dry etch method.

Abstract: A chemical vapor deposition process for depositing tungsten films having small grain size is provided. The process involves depositing a nucleation layer having very small nuclei that are closely spaced so that there are few vacancies on the surface. Such a nucleation layer results in a film with small grains after the subsequent deposition of bulk layers. The temperature of the substrate can be increased during deposition of the nucleation layer and then lowered for deposition of the bulk layer to produce a small grain tungsten film. Additionally, the thickness of the nucleation layer can be controlled, and the deposition chamber pressure and silage flow rates can also be controlled to achieve the desired nucleation layer before deposition of the bulk layers.

Abstract: The construction of a film on a wafer, which is placed in a processing chamber, may be carried out through the following steps. A layer of material is deposited on the wafer. Next, the layer of material is annealed. Once the annealing is completed, the material may be oxidized. Alternatively, the material may be exposed to a silicon gas once the annealing is completed. The deposition, annealing, and either oxidation or silicon gas exposure may all be carried out in the same chamber, without need for removing the wafer from the chamber until all three steps are completed. A semiconductor wafer processing chamber for carrying out such an in-situ construction may include a processing chamber, a showerhead, a wafer support and a rf signal means. The showerhead supplies gases into the processing chamber, while the wafer support supports a wafer in the processing chamber.