Abstract: Low resistant vias are formed by sequentially treating an opening in an interlayer dielectric and the exposed surface of a lower metal feature with an NH3 plasma followed by a N2/H2 plasma, thereby removing any oxide on the metal surface and removing residual polymers or polymeric deposits generated during etching to form the opening. Embodiments include forming a dual damascene opening in a low-k interlayer dielectric exposing the upper surface of a lower Cu or Cu alloy feature, sequentially treating the opening and the upper surface of the lower metal feature with an NH3 plasma and then with a N2/H2 plasma, Ar sputter etching, depositing a barrier layer lining the opening, depositing a seedlayer and filling the opening with Cu or a Cu alloy.

Abstract: A semiconductor device and method for fabricating the same which improves reliability of the semiconductor device is disclosed. The semiconductor device includes: a first insulating film and a gate electrode sequentially formed on a part of a semiconductor substrate; a first insulating spacer formed at both sides above the gate electrode; a second insulating spacer formed at both sides below the gate electrode; and a cobalt silicide film formed on a surface of the gate electrode at a predetermined depth.

Abstract: A method for fabricating a Schottky diode using a shallow trench contact to reduce leakage current in the fabrication of an integrated circuit device is described. The method provides a simple and effective method for decreasing the possibility of forming a bad Schottky diode.

Abstract: A single rapid thermal anneal (RTA) process is used to form a low resistivity titanium silicide layer atop a polysilicon gate layer for a MOSgated device. The process employs an amorphous silicon layer formed atop the polysilicon layer, followed by forming a titanium layer atop the amorphous silicon. A single RTA process at a temperature below the temperature of contamination diffusion is carried out, preferably at about 650° C. for 30 seconds. The top of the annealed titanium silicide layer is then stripped, and the remaining layer has a sheet Rho of less than about 2 ohms per square.

Abstract: A method for forming an improved copper inlaid interconnect (FIG. 11) begins by performing an RF preclean operation (408) on the inlaid structure in a chamber (10). The RF preclean rounds corners (210a and 206a) of the structure to reduce voiding and improve step coverage while not significantly removing copper atoms from the underlying exposed copper interconnects surfaces (202a). A tantalum barrier (220) is then deposited where one portion of the tantalum barrier is more tensile than another portion of the tantalum barrier. After formation of the barrier layer (220), a copper seed layer (222) is formed over a top of the barrier layer. The copper layer is formed while clamping the wafer with an improved clamp (85) which reduces copper peeling and contamination at wafer edges. Copper electroplating and chemical mechanical polishing (CMP) processes are then used to complete the copper interconnect structure.

Abstract: The inspection apparatus inspects defects of wafer circumference by processing the image information of the wafer circumference. The inspection apparatus includes a wafer moving unit and an image information acquisition unit. The moving unit accommodates the semiconductor wafers and either moves the wafers linearly or rotates the wafers. The moving unit moves the wafers linearly in a direction of the plane of the wafers when the image information of a linear portion of the wafer is being obtained by the image information acquisition unit. The moving unit rotates the wafers when the image information on a round portion of the wafer circumference is being obtained.

Abstract: A semiconductor device which exhibits reduced electromigration which includes an electrically conductive support member having a thin film of chromium overlaying the conductive support and a layer of semiconductor material overlaying said chromium film. The invention also includes a method of reducing electromigration and resistance and resistance in conductive supporting layers of semiconductor devices by forming a chromium layer over at least one surface of the conductive support layer of the device. The conductive support may be copper or aluminum with a semiconductive layer of germanium or silicon.

Abstract: A process for device fabrication, comprising the steps of forming a dielectric material region on a silicon substrate, forming a first amorphous silicon or polysilicon region on the dielectric material region, implanting one or more dopants in the first amorphous silicon or polysilicon region, and, subsequent to implanting the one or more dopants in the first amorphous silicon or polysilicon region, forming a second amorphous silicon or polysilicon region on the first amorphous silicon or polysilicon region. Typically, a refractory metal silicide layer is formed over the silicon, and such silicide is optionally formed by a salicide process. The second silicon region makes it more difficult for the implanted dopants to reach the silicide layer, and thereby reduces undesirable lateral diffusion of dopants in the silicide and accompanying cross-doping. The buried nature of the dopants in the silicon further reduces the amount of lateral diffusion within the silicon, regardless of the gate material.

Abstract: This invention relates to method of forming a barrier layer in a high aspect ratio recess in a dielectric layer on a semi-conductor wafer.

Abstract: A metal line of a semiconductor device and method of fabricating the same are provided in which the metal line deterioration due to electromigration is minimized to improve its reliability.

Abstract: Ohmic and rectifying contacts to a TaC layer on an n-type or p-type area of an SiC substrate are formed by depositing a WC layer over the TaC layer, followed by a metallic W layer. Such contacts are stable to at least 1150° C. Electrodes connect to the contacts either directly or via a protective bonding layer such as Pt or PtAu alloy through a dielectric layer.

Abstract: A process for chemical vapor deposition of titanium nitride film using thermal decomposition of a metal-organic compound is disclosed. In particular, the deposition of titanium nitride film from tetrakis dimethylamino-titanium (TDMAT) is performed at a temperature preferably below 350° C. in the presence of helium and nitrogen. The process is performed at a total pressure of about 5 torr, a nitrogen dilutant gas flow of at least 500 sccm, preferably about 1000 sccm, and an edge purge gas flow of at least 500 sccm. These process parameters, coupled with an improved thermal conduction between the wafer and the heated pedestal, lead to a conformal deposition of titanium nitride film at a rate of at least 6 Å/sec.

Abstract: A component is produced on a substrate made of SiC. The component has at least one ohmic contact and at least one Schottky contact. The component is brought to a temperature of more than 1300° C. at least during the growth of an epitaxial layer. To ensure that the production of the ohmic contact does not lead to impairment of other structures on the component and that the ohmic contact, for its part, is insensitive with respect to later method steps at high temperatures, the first metal is applied to the substrate for the ohmic contact before the epitaxial layer is grown.

Abstract: A dual-metal-trench silicon carbide Schottky pinch rectifier having a plurality of trenches formed in an n-type SiC substrate, with a Schottky contact having a relatively low barrier height on a mesa defined between adjacent ones of the trenches, and a Schottky contact having a relatively high barrier height at the bottom of each trench. The same metal used for the Schottky contact in each trench is deposited over the Schottky contact on the mesa. A simplified fabrication process is disclosed in which the high barrier height metal is deposited over the low barrier height metal and then used as an etch mask for reactive ion etching of the trenches to produce a self-aligned low barrier contact.

Abstract: A process for chemical vapor deposition of titanium nitride film using thermal decomposition of a metal-organic compound is disclosed. In particular, the deposition of titanium nitride film from tetrakis dimethylamino-titanium (TDMAT) is performed at a temperature preferably below 350° C. in the presence of helium and nitrogen. The process is performed at a total pressure of about 5 torr, a nitrogen dilutant gas flow of at least 500 sccm, preferably about 1000 sccm, and an edge purge gas flow of at least 500 sccm. These process parameters, coupled with an improved thermal conduction between the wafer and the heated pedestal, lead to a conformal deposition of titanium nitride film at a rate of at least 6 Å/sec.

Abstract: A method of forming an electrically conductive plug in an opening in a dielectric layer of a substrate. A layer of silicon is deposited on the walls of an opening. In one aspect, the opening is filled by depositing electrically conductive material directly over the silicon. In another aspect, the layer of silicon is exposed to a precursor gas that reacts with the silicon so as to (a) form a volatile material that consumes substantially all of the silicon and (b) deposit an electrically conductive material within the opening.

Abstract: The present invention Is a fabrication method for a short-channel Schottky-barrier field-effect transistor device. The method of the present invention includes introducing channel dopants into a semiconductor substrate such that the dopant concentration varies in the vertical direction and is generally constant in the lateral direction. A gate electrode is formed on the semiconductor substrate, and source and drain electrodes are formed on the substrate to form a Schottky or Schottky-like contact to the substrate.

Abstract: The construction of a film on a wafer, which is placed in a processing chamber, may be carried out through the following steps. A layer of material is deposited on the wafer. Next, the layer of material is annealed. Once the annealing is completed, the material may be oxidized. Alternatively, the material may be exposed to a silicon gas once the annealing is completed. The deposition, annealing, and either oxidation or silicon gas exposure may all be carried out in the same chamber, without need for removing the wafer from the chamber until all three steps are completed. A semiconductor wafer processing chamber for carrying out such an in-situ construction may include a processing chamber, a showerhead, a wafer support and a rf signal means. The showerhead supplies gases into the processing chamber, while the wafer support supports a wafer in the processing chamber.

Abstract: The construction of a film on a wafer, which is placed in a processing chamber, may be carried out through the following steps. A layer of material is deposited on the wafer. Next, the layer of material is annealed. Once the annealing is completed, the material may be oxidized. Alternatively, the material may be exposed to a silicon gas once the annealing is completed. The deposition, annealing, and either oxidation or silicon gas exposure may all be carried out in the same chamber, without need for removing the wafer from the chamber until all three steps are completed. A semiconductor wafer processing chamber for carrying out such an in-situ construction may include a processing chamber, a showerhead, a wafer support and a rf signal means. The showerhead supplies gases into the processing chamber, while the wafer support supports a wafer in the processing chamber.

Abstract: A method for preventing tungsten contact/via plug loss after a backside pressure fault defect in a deposition chamber is provided. In the method, first deposited by a silane soak step and a tungsten nucleation layer is subsequently deposited, a plasma treating step by a H2 plasma is carried out at a temperature of not higher than 480° C. for a time period of at least 15 seconds. The plasma treating step significantly improves the uniform distribution of the silicon prenucleation layer and substantially prevents the formation of any tungsten silicide layers such that during an etchback process, the dry etchant utilized does not remove a tungsten silicide layer at a much faster rate and leads to a plug loss defect.

Abstract: A Schottky rectifier has multiple stages with substantially identical or very similar structures. Each stage includes a nitride-based semiconductor layer, a Schottky contact formed on one surface of the semiconductor layer, and an ohmic contact formed on an opposite surface of the semiconductor layer. The Schottky layer is formed from a metallic material with a high metal work function, and the ohmic contact is formed from a metallic material with a low metal work function. At least one of the stages is a middle stage located between two adjacent stages, such that the Schottky contact of the middle stage and the ohmic contact of one of the adjacent stages are joined together, and such that the ohmic contact of the middle stage and the Schottky contact of another one of the adjacent stages are joined together.

Abstract: The silicon real estate consumed by a conventional Schottky diode is reduced in the present invention by forming the Schottky diode through a field oxide isolation region. Etching through the field oxide isolation region requires extra etch time which is provided by conventional etch steps that typically specify a 50-100% overetch during contact formation.

Abstract: A semiconductor device in which a salicide structure is applied to a buried gate transistor to largely reduce a difference of level or height in a element and to reduce the resistance of a gate electrode and a source/drain structure, thus enabling reliable high speed operations while maintaining high performance. For manufacturing the semiconductor device, a silicon substrate is formed with a groove for a buried gate. A gate insulating film is formed on the bottom surface of the groove. Then, side-wall insulating films are formed on both side surfaces of the groove in a large thickness as compared with that of the gate insulating film. Next, after a gate electrode is formed from a polycrystalline silicon film, a source/drain structure is formed in the silicon substrate through the gate electrode and the side-wall insulating film. Then, a Ti film is formed and annealed to form silicide layers on the gate electrode and on the source/drain electrodes, thus completing a salicide structure.

Abstract: High integrity ultra-shallow source/drain junctions are formed employing cobalt silicide contacts. These are formed by depositing a layer of cobalt on a substrate above intended source/drain regions, and depositing a doped amorphous silicon film on the cobalt. Silicidation, as by rapid thermal annealing, is performed to form a low-resistance cobalt suicide while consuming the amorphous silicon film and diffusing impurities from the doped amorphous silicon film through the cobalt silicide into the substrate. The diffusion of the impurities forms shallow junctions extending into the substrate a substantially constant depth below the cobalt silicide/silicon substrate interface.

Abstract: A method is disclosed for forming an array of submicron-sized wires in a host body. In the method, the vapor of a metal, such as bismuth, is caused to flow upward through a horizontal refractory plate having many through holes, 200 nanometers or less in diameter, until all foreign material is excluded from the holes and then the plate is cooled from the top side to progressively and simultaneously condense said vapor to form said wires in the holes.

Abstract: A method of contacting a silicide-based Schottky diode including the step of providing a contact to the silicide that is fully bordered with respect to an internal edge of the guard ring area. A Schottky diode having silicide contacting a guard ring of the Schottky diode and a contact to the silicide that is fully bordered by silicide with respect to an internal edge of the guard ring.

Abstract: A method of fabricating a DRAM device to reduce the stress and enhance the adhesion between the top electrode and the interlevel dielectric layer, includes forming a titanium layer between the top electrode and the interlevel dielectric layer. A titanium oxide layer and a titanium silicide are formed between the titanium layer and the interlevel dielectric layer in post thermal procedures, which enhances the adhesion and avoids cracks and leakage current between the top electrode and the interlevel dielectric layer.

Abstract: A method of forming channel for metal oxidation semiconductor in the integrated circuits. The manufacturing process is as following: a layer of amorphous silicon is deposited after forming the gate oxide, and ion implantation for forming channel is performed, then a doped polysilicon layer and a silicide layer are deposited orderly, finally the whole structure is defined to form a gate electrode. The key point of the current invention is the addition of amorphous silicon. This amorphous silicon can prevent the direct bombardment of implanted ions to the gate oxide, it can also avoid the diffusion of polysilicon dopant into the gate oxide, therefore, the electrical properties of transistor will be made stable. In addition, the native oxide spontaneously produced between amorphous silicon and polysilicon along with process is very even and plain, it is profitable to planarization when subsequently depositing other layers.

Abstract: An improved method for forming a metal contact for a silicon sensor. First, platinum is deposited over a contact area. Then the platinum is sintered to form platinum silicide. Subsequently, titanium/tungsten (TiW) is deposited over the platinum silicide. Finally, gold is deposited over the TiW.

Abstract: An integrated circuit fabrication process is provided for using a dual salicidation process to form a silicide gate conductor to a greater thickness than silicide structures formed upon source and drain regions of a transistor. A high K gate dielectric residing between the gate conductor and the substrate substantially inhibits consumption of the junctions during the formation of the silicide gate conductor. In an embodiment, a relatively thick layer of refractory metal is deposited across a transistor arranged upon and within a silicon-based substrate. The transistor includes a polysilicon gate conductor arranged upon a portion of a high K gate dielectric interposed between a pair of source and drain junctions. The refractory metal is heated to convert the polysilicon gate conductor to a silicide gate conductor.

Abstract: A tungsten nitride (6b) is provided also on side surface of a tungsten (6c), to increase an area where the tungsten (6c) and the tungsten nitride (6b) are in contact with each other. On a gate insulating film (2), a polysilicon side wall (5) having high adhesive strength to the gate insulating film is disposed. The polysilicon side wall (5) is brought into a close contact with the tungsten nitride (6b) on the side surface of the tungsten (6c). With this structure improved is adhesive strength of a metal wire or a metal electrode which is formed on an insulating film of a semiconductor device.

Abstract: A method for fabricating a deep sub-micron gate electrode, comprising polysilicon and metal, having ultra-low sheet resistance. The process begins by forming shallow trench isolation regions 14 in a silicon substrate 10. A gate oxide layer is formed on device areas. A doped blanket polysilicon layer 16 is formed on the gate oxide layer. A cap layer 20 composed of silicon nitride is formed on the polysilicon layer 16. The cap layer 20 and the polysilicon layer 16 are patterned by photoresist masking and anisotropic etching to form a bottom gate electrode 16A and a gate cap 20A. Lightly doped source/drain areas 22 are formed adjacent to the gate bottom electrodes 16A by ion implantation. Sidewall spacers 21 are formed on the gate electrode 16A and gate cap 20A. Source/drain regions 24 are formed by ion implantation adjacent to said sidewall spacers 21. A metal silicide 23 is formed on the source/drain regions 24.

Abstract: A method of fabricating an oxidation barrier for a thin film is provided. The method may include forming a thin film (10) outwardly from a semiconductor substrate (12) and separated from the semiconductor substrate (12) by a primary insulator layer (14). A reactive layer (16) may be formed in-situ adjacent to the thin film (10). An oxidation barrier (20) may be formed by a chemical reaction between the thin film (10) and the reactive layer (16). The oxidation barrier (20) may comprise a silicide alloy that operates to reduce oxidation of the thin film (10).

Abstract: A semiconductor device having an elevated silicidation layer and process for fabricating such a device is provided. Consistent with one embodiment of the invention, at least one gate electrode is formed over a substrate and silicon is formed over at least one active region of the substrate adjacent the gate electrode. A layer of metal is then formed over the silicon. Using the metal layer and the silicon, a silicidation layer is formed over the active region. The active region may, for example, include a source/drain region. The ratio of the depth of the silicidation layer to the depth of the source/drain region may, for example, be greater than or equal to 0.75:1. In other embodiments, the ratio of the silicidation layer depth to source/drain region depth may be greater than or equal to 1:1, 1.5:1 or 2:1.

Abstract: Provided are methods of forming a metal layer on the horizontal and vertical surfaces of a polysilicon gate electrode/interconnect in a MOS transistor, and devices having metal-encapsulated gates and interconnects. The metal encapsulation method of the present invention may also provide a layer of metal on the exposed surfaces of the source and drain regions of the transistor. The methods and apparatuses of the present invention allow reductions in device resistance and signal propagation delays.

Abstract: In the present invention, a vertical type MOSFET and a Schottky barrier diode which are used as a switching device of a DC--DC converter are formed on the same semiconductor substrate. Further, a barrier metal which is required for the Schottky barrier diode is also formed on an electrode portion of the vertical type MOSFET. In addition, a Schottky barrier diode forming region is formed to have low impurity concentration than a vertical type MOSFET forming region.

Abstract: A schottky diode is formed of a sintered palladium platinum silicide in contact with a lightly doped silicon surface in which the platinum and palladium are present in a ratio of about one part to about 10 parts respectively, by weight.

Abstract: The present invention provides a method for fabricating tungsten local interconnections in high density CMOS circuits, and also provides high density CMOS circuits having local interconnections formed of tungsten. Pursuant to the method, an etch stop layer of chromium is initially deposited on the circuit elements of the CMOS silicon substrate. Next, a conductive layer of tungsten is non-selectively deposited on the chromium layer. A photoresist mask is then lithographically patterned over the tungsten layer. The tungsten layer is then etched down to, and stopping at, the chromium layer, after which the photoresist mask is stripped. The stripping preferably uses a low temperature plasma etch in O.sub.2 at a temperature of less than 100.degree. C. Finally, a directional O.sub.2 reactive ion etch is used to remove the chromium layer selectively to the silicon substrate. Borderless contacts are formed with the aid of the chromium etch stop layer beneath the tungsten local interconnection layer.

Abstract: A method of defining a line width includes forming a spacer (45) over a layer (42) and using the spacer (45) as an etch mask (57) while etching the layer (42). In this manner, a width (47) of the spacer (45) is used to define a width or line width (47) for the layer (42). Another method of using a spacer to define a line width includes forming a spacer (14) over a substrate (11), depositing a layer (15) over the substrate (11) and the spacer (14), planarizing the layer (15) to expose the spacer (14), and removing the spacer (14) to form an opening (19) over the substrate (11), wherein the opening (19) has a width or line width (17) of the spacer (14).