Abstract: A memory cell of an SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly include a laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film of silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.

Abstract: A semiconductor memory device includes: a semiconductor substrate; an element isolation insulating film dividing the semiconductor substrate into a plurality of element regions; tunnel insulating films formed respectively on the plurality of element regions; floating gate electrodes formed respectively on the tunnel insulating films; a first control-gate electrode formed, on the floating gate electrodes and between each two floating gate electrodes adjacent to each other in a channel-width direction, with a laminated insulating film interposed therebetween; assist insulating films formed on side surface facing in the channel-width direction of the plurality of element regions; and a second control-gate electrode formed between the plurality of element regions with the assist insulating films interposed therebetween.

Abstract: Various methods for forming active electronic devices, such as field-effect transistors, and devices made using these methods are disclosed. Some of the methods include growing freestanding nano-, micro- and milli-scale semiconducting structures that are used for the active semiconducting channels of the active electronic devices. Others of the methods include forming strands of active electronic devices along a wire. Yet others of the methods utilize both of these concepts so that the active electronic devices on a particular strand include freestanding semiconducting structures.

Abstract: There are disclosed TFTs that have excellent characteristics and can be fabricated with a high yield. The TFTs are fabricated, using an active layer crystallized by making use of nickel. Gate electrodes are comprising tantalum. Phosphorus is introduced into source/drain regions. Then, a heat treatment is performed to getter nickel element in the active layer and to drive it into the source/drain regions. At the same time, the source/drain regions can be annealed out. The gate electrodes of tantalum can withstand this heat treatment.

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a plurality of active regions which are defined in a semiconductor substrate, a plurality of gate lines which are formed as zigzag lines, extend across the active regions, are symmetrically arranged, and define a plurality of first regions and a plurality of second regions therebetween, and wherein the first regions being narrower than the second regions. The semiconductor device further includes an insulation layer which defines a plurality of contact regions by filling empty spaces in the first regions between the gate lines and, extending from the first regions, and surrounding sidewalls of portions of the gate lines in the second regions, and wherein the contact regions partially exposing the active regions and a plurality of contacts which respectively fill the contact regions.

Abstract: Sophisticated gate electrode structures for N-channel transistors and P-channel transistors are patterned on the basis of substantially the same configuration while, nevertheless, the work function adjustment may be accomplished in an early manufacturing stage. For this purpose, diffusion layer and cap layer materials are removed after incorporating the desired work function metal species into the high-k dielectric material and subsequently a common gate layer stack is deposited and subsequently patterned.

Abstract: A nonvolatile semiconductor memory device includes first electrodes, a second and a third electrode, a first film, a first inter layer film, a second inter layer film, and a second film. The first electrodes each have a charge storage and a control electrode. The second and the third electrodes are formed above the semiconductor substrate. The first film is formed on each sidewall of the second and third electrodes and formed on the surface of the semiconductor substrate. The first inter layer film filled in a gap between the second and third electrodes. The second inter layer film filled in a gap between the first and second electrode. The second film is formed on the first to third gate electrodes, the first film and the first inter layer film, and a second inter layer insulating film to suppress diffusion of hydrogen atoms included in the first inter layer film.

Abstract: A method is provided for forming a self-aligned carbon nanotube (CNT) field effect transistor (FET). According to one feature, a self-aligned source-gate-drain (S-G-D) structure is formed that allows for the shrinking of the gate length to arbitrarily small values, thereby enabling ultra-high performance CNT FETs. In accordance with another feature, an improved design of the gate to possess a “T”-shape, referred to as the “T-Gate,” thereby enabling a reduction in gate resistance and further providing an increased power gain. The self-aligned T-gate CNT FET is formed using simple fabrication steps to ensure a low cost, high yield process.

Abstract: FinFET structures with fins having stress-inducing caps and methods for fabricating such FinFET structures are provided. In an exemplary embodiment, a method for forming stressed structures comprises forming a first stress-inducing material overlying a semiconductor material and forming spacers overlying the first stress-inducing material. The first stress-inducing material is etched using the spacers as an etch mask to form a plurality of first stress-inducing caps. The semiconductor material is etched using the plurality of first stress-inducing caps as an etch mask.

Abstract: System and method for transistor level routing is disclosed. A preferred embodiment comprises a semiconductor device including a first semiconductor device formed on a first active area in a substrate, the first semiconductor device having a first gate stack comprising a first high-k dielectric layer, a first metal layer and a first poly-silicon layer. The semiconductor device further includes a second semiconductor device formed on a second active area in the substrate, the second semiconductor device having a second gate stack comprising a second high-k dielectric layer, a second metal layer and a second poly-silicon layer. An electrical connection connects the first semiconductor device with the second semiconductor device and overlies the first active area, the second active area and a portion of the substrate between the first active area and the second active area.

Abstract: A method for forming a level of a tridimensional structure on a first support in which components are formed, including the steps of forming, on a second semiconductor support, a single-crystal semiconductor substrate with an interposed thermal oxide layer; placing the free surface of the single-crystal semiconductor substrate on the upper surface of the first support; eliminating the second semiconductor support; and thinning down the thermal oxide layer down to a thickness capable of forming a gate insulator.

Abstract: A method for fabricating a semiconductor device is disclosed. The method includes providing a substrate; forming one or more gate structures over the substrate; forming a buffer layer over the substrate, including over the one or more gate structures; forming an etch stop layer over the buffer layer; forming a interlevel dielectric (ILD) layer over the etch stop layer; and removing a portion of the buffer layer, a portion of the etch stop layer, and a portion of the ILD layer over the one or more gate structures.

Abstract: A nonvolatile semiconductor memory fabrication method including forming a first insulating film and a floating gate electrode material on a semiconductor substrate; forming a gate insulating film and a floating gate electrode by etching the first insulating film and the floating gate electrode material, respectively, and forming a groove for an element isolation region by etching the semiconductor substrate; and forming an element region and the element isolation region by burying a second insulating film in the groove and planarizing the second insulating film.

Abstract: In a method for forming a field effect transistor, a metal nitride layer is formed on a gate electrode insulating layer. Tantalum amine derivatives represented by the chemical formula Ta(NR1)(NR2R3)3, in which R1, R2 and R3 represent H or a C1-C6 alkyl group, may be used to form the metal nitride layer. Nitrogen may then be implanted into the metal nitride layer to increase the nitrogen content of the layer.

Abstract: A floating gate MOS transistor having a conductive floating gate electrode insulated from a semiconductor material having a main surface by a gate dielectric layer. At least one isolation region formed lateral to the gate electrode. An evacuation is formed in the isolation region and beneath the main surface of the semiconductor material layer. A conductive material fills the evacuation. A conductive control gate electrode is formed above the floating gate electrode. The floating gate electrode is laterally aligned to at least one isolation region.

Abstract: Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.

Abstract: A peripheral circuit area is formed around a memory cell array area. The peripheral circuit area has element regions, an element isolation region isolating the element regions, and field-effect transistor formed in each of the element regions and including a gate electrode extending in a channel width direction, on a semiconductor substrate. An end portion and a corner portion of the gate electrode are on the element isolation region. A radius of curvature of the corner portion of the gate electrode is smaller than a length from the end portion of the element region in the channel width direction to the end portion of the gate electrode in the channel width direction, and is less than 85 nm.

Abstract: A method of reforming a metal pattern for improving the productivity and reliability of a manufacturing process, an array substrate and a method of manufacturing the array substrate are disclosed. In the method, a first wiring pattern is formed on an insulation substrate. The first wiring pattern is removed. A second wiring pattern is formed on an embossed pattern by using the embossed pattern as an alignment mask. The embossed pattern is defined by a recess formed on a surface of the insulation substrate. Accordingly, the insulation substrate having the recess formed thereon may not be discarded, and may be reused in forming the first wiring pattern. In addition, the embossed pattern defined by the recess is used as an alignment mask, so that the alignment reliability of a metal pattern may be improved.

Abstract: A nonvolatile memory device including one resistor and one transistor. The resistor may correspond to a resistance layer electrically connected to a first impurity region and a second impurity region of the transistor.

Abstract: Four regions (a narrow NMOS region, a wide NMOS region, a wide PMOS region, and a narrow PMOS region) are defined on a semiconductor substrate. Then, after a gate insulating film and a polysilicon film are sequentially formed on the semiconductor substrate, n-type impurities are introduced into the polysilicon film in the wide NMOS region. Next, by patterning the polysilicon film, gate electrodes are formed in the four regions. Then, n-type impurities are introduced into the gate electrodes in the narrow NMOS region and the wide NMOS region. As a result, an impurity concentration of the gate electrode in the narrow NMOS region becomes lower than that of the gate electrode in the wide NMOS region.

Abstract: A nonvolatile memory device comprises floating gates formed over an active region of a semiconductor substrate, isolation layers formed within respective isolation regions of the semiconductor substrate, first nitridation patterns formed on sidewalls of the floating gates, a first insulating layer, a second nitride layer, a second insulating layer, and a third nitride layer formed on an entire surface of the first nitridation patterns and the isolation layers, and control gates formed over the third nitride layer.

Abstract: According to one embodiment of the present invention, a method of forming an apparatus comprises forming a plurality of deep trenches and a plurality of shallow trenches in a first region of a substrate. At least one of the shallow trenches is positioned between two deep trenches. The plurality of shallow trenches and the plurality of deep trenches are parallel to each other. The method further comprises depositing a layer of conductive material over the first region and a second region of the substrate. The method further comprises etching the layer of conductive material to define a plurality of lines separated by a plurality of gaps over the first region of the substrate, and a plurality of active device elements over the second region of the substrate. The method further comprises masking the second region of the substrate.

Abstract: The present invention discloses to a method of forming a gate electrode, the method according to the present invention comprises the steps of forming a lower amorphous silicon layer using silane (SiH4) gas and nitrous oxide (N2O) gas; forming an upper amorphous silicon layer on the lower amorphous silicon layer; and crystallizing the lower and upper amorphous silicon layers through a thermal process.

Abstract: A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a dielectric material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region. The method subjects the second upper surface region to a chemical mechanical polishing process to remove the first elevated region, the second elevated region, and the third elevated region to cause formation of a substantially planarized second polysilicon layer free from the fill material.

Abstract: A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a dielectric material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region.

Abstract: Stress enhanced transistor devices and methods of fabricating the same are provided. In one embodiment, a transistor device comprises: a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers, wherein the semiconductor substrate comprises a channel region underneath the gate conductor and recessed regions on opposite sides of the channel region, wherein the recessed regions undercut the dielectric spacers to form undercut areas of the channel region; and epitaxial source and drain regions disposed in the recessed regions of the semiconductor substrate and extending laterally underneath the dielectric spacers into the undercut areas of the channel region.

Abstract: A semiconductor device having a saddle fin gate and a method for manufacturing the same are presented. The semiconductor device includes a semiconductor substrate, an isolation structure, and gates. The semiconductor substrate is defined with first grooves in gate forming areas. The isolation structure is formed in the semiconductor substrate and is defined with second grooves which expose front and rear surfaces of the gate forming areas. The gates are formed within the first grooves in the gate forming areas. Gates are also formed in the second grooves of the isolation structure to cover the exposed front and rear surfaces of the gate forming areas. The second grooves are wider at the lower portions that at the upper portions.

Abstract: Metal-oxide semiconductor (MOS) devices and techniques for the fabrication thereof are provided. In one aspect, a metal-oxide semiconductor device is provided comprising a substrate; and at least one n-channel field effect transistor (NFET) having a gate stack over the substrate. The NFET gate stack comprises an NFET gate stack metal gate layer; a first NFET gate stack silicon layer over the NFET gate stack metal gate layer; a second NFET gate stack silicon layer over a side of the first NFET gate stack silicon layer opposite the NFET gate stack metal gate layer, wherein an interface is defined between the first NFET gate stack silicon layer and the second NFET gate stack silicon layer; and an NFET gate stack silicide region that extends through the interface between the first NFET gate stack silicon layer and the second NFET gate stack silicon layer.

Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.

Abstract: The present invention, in one embodiment provides a method of forming a semiconducting device including providing a substrate including a semiconducting surface, the substrate comprising a first device region and a second device region; forming a high-k dielectric layer atop the semiconducting surface of the substrate; forming a block mask atop the second device region of the substrate, wherein the first device region of the substrate is exposed; forming a first metal layer atop the high-k dielectric layer present in the first device region of the substrate; removing the block mask to expose a portion of the high-k dielectric layer in the first device region of the substrate; forming a second metal layer atop the portion of the high-k dielectric layer in the second device region and atop the first metal in the first device region of the substrate; and forming gate structures in the first and second device regions of the substrate.

Abstract: Various structures and methods for improving the performance of trench-shielded power semiconductor devices and the like are described.

Abstract: The present invention provides a manufacturing method of a thin film transistor array panel, which includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact on the gate line; forming a first conducting film including Mo, a second conducting film including Al, and a third conducting film including Mo on the ohmic contact; forming a first photoresist pattern on the third conducting film; etching the first, second, and third conducting films, the ohmic contact, and the semiconductor layer using the first photoresist pattern as a mask; removing the first photoresist pattern by a predetermined thickness to form a second photoresist pattern; etching the first, second, and third conducting films using the second photoresist pattern as a mask to expose a portion of the ohmic contact; and etching the exposed ohmic contact using a Cl-containing gas and a F-containing gas.

Abstract: Nonvolatile memory devices and methods of fabricating the same are provided. A semiconductor substrate is provided having a cell field region and a high-voltage field region. Device isolation films are provided on the substrate. The device isolation films define active regions of the substrate. A cell gate-insulation film and a cell gate-conductive film are provided on the cell field region of the substrate including the device isolation films. A high-voltage gate-insulation film and a high-voltage gate-conductive film are provided on the high-voltage field region of the substrate including the device isolation films. The device isolation film on the high-voltage field region of the substrate is at least partially recessed to provide a groove therein.

Abstract: A nonvolatile semiconductor memory that allows simultaneous implementation of high performance transistors in a low-voltage circuit region and transistors with high withstand voltages in a high-voltage circuit region.

Abstract: A semiconductor integrated circuit device according to an embodiment of the present invention includes a functional circuit region including a functional circuit, a dummy region formed in a region other than the functional circuit region, and plural dummy MOSFETs formed in a dummy region and having a dummy gate electrode on a dummy diffusion layer, the plural dummy MOSFETs being arranged such that date rates of the dummy diffusion layer and dummy gate electrode are kept constant in a predetermined section.

Abstract: Methods for fabricating FinFET structures having gate structures of different gate widths are provided. The methods include the formation of sidewall spacers of different thicknesses to define gate structures of the FinFET structures with different gate widths. The width of a sidewall spacer is defined by the height of the structure about which the sidewall spacer is formed, the thickness of the sidewall spacer material layer from which the spacer is formed, and the etch parameters used to etch the sidewall spacer material layer. By forming structures of varying height, forming the sidewall spacer material layer of varying thickness, or a combination of these, sidewall spacers of varying width can be fabricated and subsequently used as an etch mask so that gate structures of varying widths can be formed simultaneously.

Abstract: Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors.

Abstract: Gate stacks of an array of memory cells and a plurality of select transistors are formed above a carrier, the gate stacks being separated by spacers. An opening is formed between the spacers in an area that is provided for a source line. A sacrificial layer is applied to fill the opening and is subsequently patterned. Interspaces are filled with a planarizing layer of dielectric material. The residues of the sacrificial layer are removed and an electrically conductive material is applied to form a source line.

Abstract: A semiconductor device includes: a semiconductor substrate; a PFET formed on the substrate, the PFET includes a SiGe layer disposed on the substrate, a high-K dielectric layer disposed on the SiGe layer, a first metallic layer disposed on the high-k dielectric layer, a first intermediate layer disposed on the first metallic layer, a second metallic layer disposed on the first intermediate layer, a second intermediate layer disposed on the second metallic layer, and a third metallic layer disposed on the second intermediate layer; an NFET formed on the substrate, the NFET includes the high-k dielectric layer, the high-k dielectric layer being disposed on the substrate, the second intermediate layer, the second intermediate layer being disposed on the high-k dielectric layer, and the third metallic layer, the third metallic layer being disposed on the second intermediate layer. Alternatively, the first metallic layer is omitted.

Abstract: A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a doped dielectric material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region. The method subjects the second upper surface region to a chemical mechanical polishing process to remove the first elevated region, the second elevated region, and the third elevated region to cause formation of a substantially planarized second polysilicon layer free from the fill material.

Abstract: A thin film transistor array panel according to the present invention includes: an insulation substrate having a display area and a peripheral area; a plurality of thin film transistors disposed in the display area; a plurality of gate lines connected to the thin film transistors; a plurality of data lines connected to the thin film transistors; a driving unit disposed in the peripheral area of the insulation substrate, and controlling the thin film transistor; a plurality of signal lines connecting between the driving unit and the gate lines or the data lines; and a dummy pattern overlapping the signal line and made of a transparent conductive material.

Abstract: A method of manufacturing a transistor is disclosed. The method includes forming a first and a second source/drain regions, a channel connecting the first and the second source/drain regions and a gate electrode for controlling the conductivity of the channel. The gate electrode is formed by defining a gate groove in the substrate, and defining a pocket in each of the isolation trenches at a position adjacent to the groove so that the two pockets will be connected with the groove and the groove is disposed between the two pockets. A gate insulating material is provided at an interface between the active area and the groove and at an interface between the active area and the pockets. A gate electrode material is deposited so as to fill the groove and the two pockets.

Abstract: A method of manufacturing an array substrate for a liquid crystal display device includes forming a gate line, a gate pad and a gate electrode on a substrate through a first mask process, forming a data line, a data pad, a source electrode, a drain electrode and an active layer on the substrate including the gate line, the gate pad and the gate electrode through a second mask process, wherein the data line crosses the gate line to define a pixel region, the source electrode is extended from the data line, the drain electrode is spaced apart from the source electrode, and the active layer is disposed between the gate electrode and the source and drain electrodes, forming a passivation layer on an entire surface of the substrate including the data line, the source electrode and the drain electrode through a third mask process, the passivation layer being etched to expose the substrate in the pixel region, a part of the drain electrode, the gate pad and the data pad, and forming a pixel electrode, a gate pad ter

Abstract: Methods for manufacturing semiconductor devices are disclosed. In a preferred embodiment, a method of processing a semiconductor device includes providing a workpiece, the workpiece comprising a material layer to be patterned disposed thereon. A hard mask is formed over the material layer. A first pattern is formed in the hard mask and an upper portion of the material layer using a first etch process. A second pattern is formed in the hard mask and the upper portion of the material layer using a second etch process, the second pattern being different than the first pattern. The first pattern and the second pattern are formed in a lower portion of the material layer using a third etch process and using the hard mask as a mask.

Abstract: Threshold voltage of a field effect transistor is successfully adjusted with a smaller dose of an impurity, as compared with a conventional adjustment of the threshold voltage only by doping an impurity into the channel region. A semiconductor device 100 has a silicon substrate 101 and a P-type MOSFET 103 comprising a SiON film 113 formed on the silicon substrate 101, and a polycrystalline silicon film 106. Any one of, or two or more of metals selected from the group consisting of Hf, Zr, Al, La, Pr, Y, Ti, Ta and W are allowed to reside at the interface 115 between the polycrystalline silicon film 106 and the SiON film 113, and concentration of the metal(s) at the interface 115 is adjusted to 5×1013 atoms/cm2 or more and less than 1.4×1015 atoms/cm2.

Abstract: The invention includes methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates. In one implementation, a method of forming a field effect transistor includes forming masking material over semiconductive material of a substrate. A trench is formed through the masking material and into the semiconductive material. Gate dielectric material is formed within the trench in the semiconductive material. Gate material is deposited within the trench in the masking material and within the trench in the semiconductive material over the gate dielectric material. Source/drain regions are formed. Other aspects and implementations are contemplated.

Abstract: Systems and arrangements to interconnect cells and structures within cells of an integrated circuit to enhance cell density are disclosed. Embodiments comprise an adjusted polysilicon gate pitch to metal wire pitch relationship to improve area scalars while increasing ACLV tolerance with a fixed polysilicon gate pitch. In some embodiments, the wire pitch for at least one metallization layer is adjusted to match the pitch for the polysilicon gate. In one embodiment, the next to the lowest metallization layer running in the same orientation as the polysilicon gate, utilized to access the input or output of the interconnected cell structures is relaxed to match the minimum contacted gate pitch and the metal is aligned above each polysilicon gate. In another embodiment, the polysilicon gate pitch may be relaxed to attain a smaller lowest common multiple with the wire pitch for an integrated circuit to reduce the minimum step off.

Abstract: Provided are methods of fabricating flash memory devices that may prevent a short circuit from occurring between cell gate lines. Methods of fabricating such flash memory devices may include forming gate lines including a series of multiple cell gate lines and multiple selection gate lines. Each gate line may include a stacked structure of a tunnel insulating layer, a floating gate, a gate insulating layer, and/or a polysilicon layer operable to be a control gate, all formed on a semiconductor substrate. Methods may include forming a first insulating layer that selectively fills gaps between the cell gate lines from the bottom up and between adjacent ones of the cell gate lines and the selection gate lines, and does not fill a space located on outer sides of the selection gate lines that are opposite the plurality of cell gate lines. A spacer may be formed on the outer sides of the selection gate lines that are opposite to the cell gate lines, after forming the first insulating layer.

Abstract: A flash memory device and a method for fabricating the same are disclosed. The flash memory device includes an ONO layer on a substrate, polysilicon gates on the ONO layer, a gate oxide layer on the substrate, the ONO layer and the polysilicon gates, and a low temperature oxide layer and polysilicon sidewall spacers on outer side surfaces of the polysilicon gates, except in a region between nearest adjacent polysilicon gates.

Abstract: A method for fabricating a CMOS integrated circuit (IC) includes providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the semiconductor surface followed by forming at least a first metal including layer on the gate dielectric layer. A polysilicon or amorphous silicon layer is formed on the first metal including layer to form an intermediate gate electrode stack. A masking pattern is formed on the intermediate gate electrode stack. The polysilicon or amorphous silicon layer is dry etched using the masking pattern to define a patterned intermediate gate electrode stack over the NMOS or PMOS regions, wherein the dry etching stops on a portion of the first metal comprising layer. The masking pattern is removed using a first post etch clean for stripping the masking pattern.