Forming Array Of Gate Electrodes Patents (Class 438/587)
  • Publication number: 20130228842
    Abstract: A semiconductor storage device includes a semiconductor substrate. A first insulating film is provided on the semiconductor substrate. A charge storage layer includes a first part provided on the first insulating film, an intermediate insulating film provided on the first part, and a second part provided on the intermediate insulating film, and is capable of storing electric charges. A second insulating film is provided on an upper surface and a side surface of the charge storage layer. A control gate is opposed to the upper surface and the side surface of the charge storage layer via the second insulating film, and is configured to control a voltage of the charge storage layer. The intermediate insulating film is recessed in comparison with side surfaces of the first and second parts on the side surface of the charge storage layer.
    Type: Application
    Filed: August 31, 2012
    Publication date: September 5, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takahiro Kotou, Hideto Takekida, Minori Kajimoto
  • Patent number: 8518812
    Abstract: Some embodiments include methods of forming contacts. A row of projections may be formed over a semiconductor substrate. The projections may include a plurality of repeating components of an array, and a terminal projection. The terminal projection may have a sacrificial material spaced from semiconductor material of the substrate by a dielectric structure. An electrically conductive line may be formed along the row. The line may wrap around an end of the terminal projection and bifurcate into two branches that are along opposing sides of the repeating components. The individual branches may have regions spaced from the sacrificial material by segments of gate dielectric. The sacrificial material may be removed, together with the segments of gate dielectric, to form a contact opening. An electrically conductive contact may be formed within the contact opening and directly against the regions of the branches.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: August 27, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Marcello Mariani, Micaela Gabriella Tomasini
  • Patent number: 8518757
    Abstract: A strained semiconductor structure and method of making the structure. The method includes: forming a pad layer on a top surface of a silicon layer of a substrate, the substrate comprising the silicon layer separated from a supporting substrate by a buried oxide layer; forming openings in the pad layer and etching trenches through the silicon layer to the buried oxide layer in the openings to form silicon regions from the silicon layer; forming spacers on the entirety of sidewalls of the silicon regions exposed in the trenches; forming oxide regions in corners of the silicon regions proximate to both the sidewalls and the buried oxide layer to form strained silicon regions, the oxide regions not extending to the pad layer; and removing at least a portion of the spacers and filling remaining spaces in the trenches with silicon to form filled regions abutting the strained silicon region.
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: August 27, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brent Alan Anderson, Edward Joseph Nowak
  • Patent number: 8513105
    Abstract: An integrated circuit constructed according to an arrangement of logic blocks, with one or more logic blocks including transistors of a different threshold voltage than in other logic blocks. Spacing between neighboring active regions of different threshold voltages is minimized by constraining the angle of implant for the threshold adjust implant, and by constraining the thickness of the mask layer used with that implant. These constraints ensure adequate implant of dopant into the channel region while blocking the implant into channel regions not subject to the threshold adjust, while avoiding shadowing from the mask layer. Efficiency is attained by constraining the direction of implant to substantially perpendicular to the run of the gate electrodes in the implanted regions.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: August 20, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory Charles Baldwin, James Walter Blatchford
  • Patent number: 8507997
    Abstract: A mask read-only memory (ROM) includes parallel doping lines of a second conductivity type formed in a substrate of a first conductivity type, a first insulation film formed on the doping lines and the substrate, conductive pads fainted on the first insulation film, a second insulation film formed on the first insulation film and the conductive pads, parallel wires formed on the second insulation film extending perpendicular to the doping lines, contact plugs formed in the first insulation film that connect the doping lines to the conductive pads, and vias formed in the second insulation film that connect the conductive pads to the wires, wherein crossings of the doping lines and the wires define memory cells, contact plugs and vias are formed in memory cells of a first type, and at least one of the contact plug and via are missing from memory cells of a second type.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: August 13, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Jin Yang, Yong-Tae Kim, Hyuck-Soo Yang, Jung-Ho Moon
  • Patent number: 8507380
    Abstract: A method of forming contact openings in the fabrication of integrated circuitry includes forming a mask which includes at least one of photoresist and amorphous carbon received over a plurality of spaced conductive line constructions. The conductive line constructions include insulative caps and insulative sidewalls. The mask includes a plurality of spaced lines and trench spaces between adjacent of the spaced lines. The spaced lines and the trench spaces angle relative to the conductive line constructions. The trench spaces are received over node locations which are received between adjacent of the conductive line constructions. The at least one of photoresist and amorphous carbon is treated with a plasma to reduce lateral width of the spaced lines and to increase lateral width of the trench spaces. After the treating, contact openings are etched to the node locations selectively relative to the insulative caps and the insulative sidewalls.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: August 13, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Mark Kiehlbauch, Anton deVilliers
  • Patent number: 8501607
    Abstract: A method is provided for forming FinFETS with improved alignment features. Embodiments include forming on a Si substrate pillars of TEOS on poly-Si; conformally depositing a first TEOS liner over the entire substrate; etching the first TEOS liner and substrate through the pillars, forming first trenches; filling the first trenches and spaces between the pillars with an oxide; removing the TEOS from the pillars and the oxide therebetween; removing the poly-Si; conformally depositing a second TEOS liner over the entire Si substrate; etching the second TEOS liner and Si between the oxide, forming second trenches having a larger depth than the first trenches; filling the second trenches with oxide; removing the oxide and the first and second TEOS liners down to an upper surface of the Si substrate; and recessing the oxide below the upper surface of the Si substrate.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: August 6, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Werner Juengling
  • Patent number: 8497198
    Abstract: A semiconductor process is described as follows. A plurality of dummy patterns is formed on a substrate. A mask material layer is conformally formed on the substrate, so as to cover the dummy patterns. The mask material layer has an etching rate different from that of the dummy patterns. A portion of the mask material layer is removed, so as to form a mask layer on respective sidewalls of each dummy pattern. An upper surface of the mask layer and an upper surface of each dummy pattern are substantially coplanar. The dummy patterns are removed. A portion of the substrate is removed using the mask layer as a mask, so as to form a plurality of fin structures and a plurality of trenches alternately arranged in the substrate. The mask layer is removed.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: July 30, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Teng-Chun Tsai
  • Publication number: 20130187235
    Abstract: The present disclosure involves a FinFET. The FinFET includes a fin structure formed over a substrate. A gate dielectric layer is least partially wrapped around a segment of the fin structure. The gate dielectric layer contains a high-k gate dielectric material. The FinFET includes a polysilicon layer conformally formed on the gate dielectric layer. The FinFET includes a metal gate electrode layer formed over the polysilicon layer. The present disclosure provides a method of fabricating a FinFET. The method includes providing a fin structure containing a semiconductor material. The method includes forming a gate dielectric layer over the fin structure, the gate dielectric layer being at least partially wrapped around the fin structure. The method includes forming a polysilicon layer over the gate dielectric layer, wherein the polysilicon layer is formed in a conformal manner. The method includes forming a dummy gate layer over the polysilicon layer.
    Type: Application
    Filed: January 19, 2012
    Publication date: July 25, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuan-Sheng Huang, Tzu-Yen Hsieh, Ming-Ching Chang, Chao-Cheng Chen, Chia-Jen Chen
  • Patent number: 8487397
    Abstract: An integrated circuit with a self-aligned contact includes a substrate with a transistor formed thereover, a dielectric spacer, a protection barrier, and a conductive layer. The transistor includes a mask layer and a pair of insulating spacers formed on opposite sides of the mask layer. The dielectric spacer partially covers at least one of the insulating spacers of the transistor. The protection barrier is formed over the dielectric spacer. The conductive layer is formed over the mask layer, the protection barrier, the dielectric spacer, the insulating spacer and the dielectric spacer as a self-aligned contact for contacting a source/drain region of the transistor.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: July 16, 2013
    Assignee: Nanya Technology Corporation
    Inventors: Jar-Ming Ho, Yi-Nan Chen, Hsien-Wen Liu
  • Patent number: 8486840
    Abstract: A method includes making a target feature of an integrated circuit by providing a main layer over a substrate, depositing a first mask layer over the main layer, patterning the first mask layer, forming sidewall spacers with a width (w) in adjoining sidewalls of the patterned first mask layer and exposing a top area of the patterned first mask layer, selectively removing the first mask layer and exposing a portion of the main layer between the sidewall spacers, depositing a second mask layer over the main layer between the sidewall spacers, selectively removing the sidewall spacers to form an opening and exposing another portion of the main layer in the opening, etching the main layer through the opening to form the target feature.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: July 16, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 8486817
    Abstract: A method for forming a level of a tridimensional structure on a first support in which components are formed, including the steps of forming, on a second semiconductor support, a single-crystal semiconductor substrate with an interposed thermal oxide layer; placing the free surface of the single-crystal semiconductor substrate on the upper surface of the first support; eliminating the second semiconductor support; and thinning down the thermal oxide layer down to a thickness capable of forming a gate insulator.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: July 16, 2013
    Assignees: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SAS, Commissariat √† l'√Čnergies Atomique et aux √Čnergies Alternatives
    Inventors: Perceval Coudrain, Philippe Coronel, Nicolas Buffet
  • Publication number: 20130175631
    Abstract: A semiconductor chip has shapes on a particular level that are small enough to require a first mask and a second mask, the first mask and the second mask used in separate exposures during processing. A circuit on the semiconductor chip requires close tracking between a first and a second FET (field effect transistor). For example, the particular level may be a gate shape level. Separate exposures of gate shapes using the first mask and the second mask will result in poorer FET tracking (e.g., gate length, threshold voltage) than for FETs having gate shapes defined by only the first mask. FET tracking is selectively improved by laying out a circuit such that selective FETs are defined by the first mask. In particular, static random access memory (SRAM) design benefits from close tracking of six or more FETs in an SRAM cell.
    Type: Application
    Filed: January 6, 2012
    Publication date: July 11, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Derick G. Behrends, Todd A. Christensen, Travis R. Hebig, Michael Launsbach, Daniel M. Nelson
  • Publication number: 20130170302
    Abstract: A non-volatile semiconductor memory device comprises a semiconductor substrate and a plurality of gate structures formed on a cell region of the semiconductor substrate. The plurality of gate structures include: a first select-gate structure and a second select-gate structure disposed on the cell region, the first select-gate structure and the second select-gate structure spaced apart from each other, and a plurality of cell gate structures disposed between the first select-gate structure and the second select-gate structure. At least one of the select-gate structures comprises plural select gates.
    Type: Application
    Filed: December 29, 2011
    Publication date: July 4, 2013
    Inventors: Sung-Min Hong, Tae-Kyung Kim, Woosung Choi
  • Publication number: 20130164925
    Abstract: A method of manufacturing a semiconductor memory device comprises forming a plurality of gate lines on a semiconductor substrate, forming an insulating layer on the gate lines, and performing a cleaning process using a surfactant-free cleaning solution having a viscosity of lower than 2 cP and an acidity of lower than 3 pH to remove residue from the surface of the insulating layer.
    Type: Application
    Filed: August 31, 2012
    Publication date: June 27, 2013
    Inventors: Duk Eui LEE, Seung Cheol LEE
  • Publication number: 20130161716
    Abstract: A non-volatile semiconductor memory device comprises a semiconductor substrate and a plurality of gate structures formed on a cell region of the semiconductor substrate. The plurality of gate structures include a first select-gate and a second select-gate disposed on the cell region, the first select-gate and the second select-gate spaced apart from each other. A plurality of cell gate structures are disposed between the first select-gate and the second select-gate. The first select-gate and an adjacent cell gate structure have no air gap defined therebetween. At least a pair of adjacent cell gate structures have an air gap defined therebetween.
    Type: Application
    Filed: December 21, 2011
    Publication date: June 27, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-Kyung KIM, Woosung CHOI
  • Patent number: 8470647
    Abstract: There has been a problem that the manufacturing process is complicated and the number of processes is increased when a TFT with an LDD structure or a TFT with a GOLD structure is formed. In a method of manufacturing a semiconductor device, after low concentration impurity regions (24, 25) are formed in a second doping process, a width of the low concentration impurity region which is overlapped with the third electrode (18c) and a width of the low concentration impurity region which is not overlapped with the third electrode can be freely controlled by a fourth etching process. Thus, in a region overlapped with the third electrode, a relaxation of electric field concentration is achieved and then a hot carrier injection can be prevented. And, in the region which is not overlapped with the third electrode, the off-current value can be suppressed.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: June 25, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Koji Ono, Toru Takayama, Tatsuya Arao, Shunpei Yamazaki
  • Publication number: 20130157451
    Abstract: Integrated circuits containing transistors are provided. A transistor may include a gate structure formed over an associated well region. The well region may be actively biased and may serve as a body terminal. The well region of one transistor may be formed adjacent to a gate structure of a neighboring transistor. If the gate structure of the neighboring transistor and the well region of the one transistor are both actively biased and are placed close to one another, substantial leakage may be generated. Computer-aided design tools may be used to identify actively driven gate terminals and well regions and may be used to determine whether each gate-well pair is spaced sufficiently far from one another. If a gate-well pair is too close, the design tools may locate an existing gate cut layer and extend the existing gate cut layer to cut the actively driven gate structure.
    Type: Application
    Filed: December 20, 2011
    Publication date: June 20, 2013
    Inventors: Wuu-Cherng Lin, Fangyun Richter, Che Ta Hsu, Wen Sun Wu
  • Publication number: 20130149854
    Abstract: An improvement is achieved in the manufacturing yield of a semiconductor device including a plurality of field effect transistors having different characteristics over the same substrate. By combining anisotropic dry etching with isotropic wet etching or isotropic dry etching, three types of sidewalls having different sidewall lengths are formed. By reducing the number of anisotropic dry etching steps, in a third n-type MISFET region and a third p-type MISFET region where layout densities are high, it is possible to prevent a semiconductor substrate from being partially cut between n-type gate electrodes adjacent to each other, between the n-type gate electrode and a p-type gate electrode adjacent to each other, and the p-type gate electrodes adjacent to each other.
    Type: Application
    Filed: October 28, 2012
    Publication date: June 13, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: RENESAS ELECTRONICS CORPORATION
  • Patent number: 8461628
    Abstract: A MOS transistor with a laser-patterned metal gate, and methods for its manufacture. The method generally includes forming a layer of metal-containing material on a dielectric film, wherein the dielectric film is on an electrically functional substrate comprising an inorganic semiconductor; laser patterning a metal gate from the metal-containing material layer; and forming source and drain terminals in the inorganic semiconductor in locations adjacent to the metal gate. The transistor generally includes an electrically functional substrate; a dielectric film on at least portions of the electrically functional substrate; a laser patterned metal gate on the dielectric film; and source and drain terminals comprising a doped inorganic semiconductor layer adjacent to the metal gate. The present invention advantageously provides MOS thin film transistors having reliable electrical characteristics quickly, efficiently, and/or at a low cost by eliminating one or more conventional photolithographic steps.
    Type: Grant
    Filed: August 11, 2005
    Date of Patent: June 11, 2013
    Assignee: Kovio, Inc.
    Inventors: Criswell Choi, Joerg Rockenberger, J. Devin MacKenzie, Christopher Gudeman
  • Patent number: 8460996
    Abstract: An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: June 11, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Gauri V. Karve, Mark D. Hall, Srikanth B. Samavedam
  • Publication number: 20130143397
    Abstract: An organic planarizing layer (OPL) is formed atop a semiconductor substrate which includes a plurality of gate lines thereon. Each gate line includes at least a high k gate dielectric and a metal gate. A patterned photoresist having at least one pattern formed therein is then positioned atop the OPL. The at least one pattern in the photoresist is perpendicular to each of the gate lines. The pattern is then transferred by etching into the OPL and portions of each of the underlying gate lines to provide a plurality of gate stacks each including at least a high k gate dielectric portion and a metal gate portion. The patterned photoresist and the remaining OPL layer are then removed utilizing a sequence of steps including first contacting with a first acid, second contacting with an aqueous cerium-containing solution, and third contacting with a second acid.
    Type: Application
    Filed: September 13, 2012
    Publication date: June 6, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nicholas C.M. Fuller, Pratik P. Joshi, Mahmoud Khojasteh, Rajiv M. Ranade, George G. Totir
  • Patent number: 8455342
    Abstract: A mask ROM fabrication method which comprises steps: sequentially forming a gate dielectric layer and a first photoresist layer on a substrate; letting a light having a wavelength of 365 nm pass through a first phase shift mask to photolithographically form on the first photoresist layer a plurality of first trenches having a width of 243-365 nm; doping the substrate to form a plurality of embedded bit lines having a width of 243-365 nm; removing the first photoresist layer; sequentially forming a polysilicon layer and a second photoresist layer on the gate dielectric layer; and letting the light pass through a second phase shift mask to photolithographically form a plurality of polysilicon word lines on the polysilicon layer. Thereby is reduced the line width of mask ROM to 243-365 nm and decreased the area of mask ROM.
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: June 4, 2013
    Assignees: Nyquest Technology Corporation Limited, Nuvoton Technology Corporation
    Inventors: Kuang-Chu Chen, Cheng Tao Chen, Chung-Lung Hsu, Chun-Yao Chiu, Chin-Yung Chang
  • Patent number: 8431458
    Abstract: A method of forming a nonvolatile memory cell includes forming a first electrode and a second electrode of the memory cell. Sacrificial material is provided between the first second electrodes. The sacrificial material is exchanged with programmable material. The sacrificial material may additionally be exchanged with select device material.
    Type: Grant
    Filed: December 27, 2010
    Date of Patent: April 30, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, Gurtej S. Sandhu
  • Patent number: 8409951
    Abstract: Methods for fabricating control gates in non-volatile storage are disclosed. When forming stacks for floating gate memory cells and transistor control gates, a sacrificial material may be formed at the top of the stacks. After insulation is formed between the stacks, the sacrificial material may be removed to reveal openings. In some embodiments, cutouts are then formed in regions in which control gates of transistors are to be formed. Metal is then formed in the openings, which may include the cutout regions. Therefore, floating gate memory cells having at least partially metal control gates and transistors having at least partially metal control gates may be formed in the same process. A barrier layer may be formed prior to depositing the metal in order to prevent silicidation of polysilicon in the control gates.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: April 2, 2013
    Assignee: SanDisk Technologies Inc.
    Inventors: Jarrett Jun Liang, Vinod Robert Purayath, Takashi Whitney Orimoto
  • Patent number: 8404600
    Abstract: A mold having an open interior volume is used to define patterns. The mold has a ceiling, floor and sidewalls that define the interior volume and inhibit deposition. One end of the mold is open and an opposite end has a sidewall that acts as a seed sidewall. A first material is deposited on the seed sidewall. A second material is deposited on the deposited first material. The deposition of the first and second materials is alternated, thereby forming alternating rows of the first and second materials in the interior volume. The mold and seed layer are subsequently selectively removed. In addition, one of the first or second materials is selectively removed, thereby forming a pattern including free-standing rows of the remaining material. The free-standing rows can be utilized as structures in a final product, e.g., an integrated circuit, or can be used as hard mask structures to pattern an underlying substrate. The mold and rows of material can be formed on multiple levels.
    Type: Grant
    Filed: June 17, 2008
    Date of Patent: March 26, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej Sandhu
  • Patent number: 8399919
    Abstract: A unit block circuit of a semiconductor device includes a first well, a first pickup unit configured to form a closed loop over the first well, a first transistor including a first gate and a first active region, and formed within the first pickup unit, and a first reservoir capacitor formed in a spare within the first pickup unit and arranged in a major-axis direction of the first gate of the first transistor, wherein the first reservoir capacitor comprises a second active region and a second gate, the second gate being formed over the second active region.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: March 19, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jong-Woo Kim
  • Patent number: 8395221
    Abstract: A semiconductor device and a method of manufacturing are provided. A dielectric layer is formed over a substrate, and a first silicon-containing layer, undoped, is formed over the dielectric layer. Atomic-layer doping is used to dope the undoped silicon-containing layer. A second silicon-containing layer is formed over first silicon-containing layer. The process may be expanded to include forming a PMOS and NMOS device on the same wafer. For example, the first silicon-containing layer may be thinned in the PMOS region prior to the atomic-layer doping. In the NMOS region, the doped portion of the first silicon-containing layer is removed such that the remaining portion of the first silicon-containing layer in the NMOS is undoped. Thereafter, another atomic-layer doping process may be used to dope the first silicon-containing layer in the NMOS region to a different conductivity type. A third silicon-containing layer may be formed doped to the respective conductivity type.
    Type: Grant
    Filed: August 11, 2010
    Date of Patent: March 12, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chen-Hua Yu
  • Publication number: 20130049134
    Abstract: In a semiconductor device and a method of making the same, a first transistor has a gate stack comprising an underlying layer formed of a first material and an overlying layer formed of a second material. A second transistor has a gate stack comprising an underlying layer formed of a third material and an overlying layer formed of the second material. A third transistor has a gate stack comprising an underlying layer formed of the first material and an overlying layer formed of a fourth material. A fourth transistor has a gate stack comprising an underlying layer formed of the third material and an overlying material formed of the fourth material. Each of the first through fourth materials has a respectively different work function, so that each of the first through fourth transistors has a respectively different threshold voltage.
    Type: Application
    Filed: July 9, 2012
    Publication date: February 28, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Hiroshi SUNAMURA
  • Publication number: 20130049072
    Abstract: A method of forming an array of recessed access device gate constructions includes using the width of an anisotropically etched sidewall spacer in forming mask openings in an etch mask for forming all recessed access device trenches within semiconductor material within all of the array. The etch mask is used while etching all of the recessed access device trenches into the semiconductor material within all of the array through the mask openings. Individual recessed access gate constructions are formed in the individual recessed access device trenches. Other methods are contemplated, including arrays of recessed access devices independent of method of manufacture.
    Type: Application
    Filed: August 25, 2011
    Publication date: February 28, 2013
    Inventors: Lars P. Heineck, Troy R. Sorensen
  • Publication number: 20130049120
    Abstract: A semiconductor device structure is disclosed. The semiconductor device structure includes a mesa extending above a substrate. The mesa has a channel region between a first side and second side of the mesa. A first gate is on a first side of the mesa, the first gate comprising a first gate insulator and a first gate conductor comprising graphene overlying the first gate insulator. The gate conductor may comprise graphene in one or more monolayers. Also disclosed are a method for fabricating the semiconductor device structure; an array of vertical transistor devices, including semiconductor devices having the structure disclosed; and a method for fabricating the array of vertical transistor devices.
    Type: Application
    Filed: August 23, 2011
    Publication date: February 28, 2013
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Gurtej S. Sandhu
  • Patent number: 8373165
    Abstract: A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to form a patterned seed layer, forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer, removing portions of the second dielectric layer to form a second patterned dielectric layer, irradiating the patterned seed layer to single-crystallize the patterned seed layer, removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer, and forming a gate electrode in contact with the single-crystal active pattern.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: February 12, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-hoon Son, Si-young Choi, Jong-wook Lee
  • Patent number: 8372740
    Abstract: The embodiments generally relate to methods of making semiconductor devices, and more particularly, to methods for making semiconductor pillar structures and increasing array feature pattern density using selective or directional gap fill. The technique has application to a variety of materials and can be applied to making monolithic two or three-dimensional memory arrays.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: February 12, 2013
    Assignee: SanDisk 3D, LLC
    Inventors: Huiwen Xu, Yung-Tin Chen, Steven J. Radigan
  • Publication number: 20130034953
    Abstract: A CMOS semiconductor device having an n-type MOSFET and a p-type MOSFET, comprising: a gate electrode of the n-type MOSFET having a first insulation layer composed of a high-k material, and a first metal layer provided on the first insulation layer and composed of a metal material; and a gate electrode of the p-type MOSFET having a second insulation layer composed of a high-k material, and a second metal layer provided on the second insulation layer and composed of a metal material, wherein the first insulation layer and the second insulation layer are composed of the different high-k materials, and the first metal layer and the second metal layer are composed of the same metal material.
    Type: Application
    Filed: August 6, 2012
    Publication date: February 7, 2013
    Inventors: Nobuyuki Mise, Takahisa Eimori
  • Patent number: 8367535
    Abstract: Example embodiments herein relate to a method of fabricating a semiconductor device. The method may include forming a liner insulating layer on a surface of a gate pattern to have a first thickness. Subsequently, a gap fill layer may be formed on the liner insulating layer by flowable chemical vapor deposition (FCVD) or spin-on-glass (SOG). The liner insulating layer and the gap fill layer may be recessed such that the liner insulating layer has a second thickness, which is smaller than the first thickness, in the region in which a metal silicide will be formed. Metal silicide may be formed on the plurality of gate patterns to have a relatively uniform thickness using the difference in thickness of the liner insulating layer.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: February 5, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Soon Choi, Ha-Young Yi, Gil-Heyun Choi, Eunkee Hong, Sang-Hoon Ahn
  • Patent number: 8367508
    Abstract: A method for forming a field effect transistor includes forming a gate stack, a spacer adjacent to opposing sides of the gate stack, a silicide source region and a silicide drain region on opposing sides of the spacer, epitaxially growing silicon on the source region and the drain region; forming a liner layer on the gate stack and the spacer, removing a portion of the liner layer to expose a portion of the hardmask layer, removing the exposed portions of the hardmask layer to expose a silicon layer of the gate stack, removing exposed silicon to expose a portion of a metal layer of the gate stack, the source region, and the drain region; and depositing a conductive material on the metal layer of the gate stack, the silicide source region, and the silicide drain region.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: February 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Wilfried E. Haensch, Xinhui Wang, Keith Kwong Hon Wong
  • Patent number: 8361864
    Abstract: A semiconductor device having a saddle fin gate and a method for manufacturing the same are presented. The semiconductor device includes a semiconductor substrate, an isolation structure, and gates. The semiconductor substrate is defined with first grooves in gate forming areas. The isolation structure is formed in the semiconductor substrate and is defined with second grooves which expose front and rear surfaces of the gate forming areas. The gates are formed within the first grooves in the gate forming areas. Gates are also formed in the second grooves of the isolation structure to cover the exposed front and rear surfaces of the gate forming areas. The second grooves are wider at the lower portions that at the upper portions.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: January 29, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung Joo Baek
  • Patent number: 8357606
    Abstract: A method of making a semiconductor device includes forming a layer over a substrate, forming a plurality of spaced apart features of imagable material over the layer, forming sidewall spacers on the plurality of features and filling a space between a first sidewall spacer on a first feature and a second sidewall spacer on a second feature with a filler feature. The method also includes removing the sidewall spacers to leave the first feature, the filler feature and the second feature spaced apart from each other, and etching the layer using the first feature, the filler feature and the second feature as a mask.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: January 22, 2013
    Assignee: SanDisk 3D LLC
    Inventors: Yung-Tin Chen, Steven J. Radigan
  • Patent number: 8349719
    Abstract: A semiconductor device and a method for fabricating the same. A plurality of gate patterns are formed over a first-conductivity type silicon layer of a silicon-on-insulator semiconductor substrate including a buried insulation layer, so as to be separated from each other. A plurality of silicon bodies are formed under the gate patterns, by removing a portion of the first-conductivity type silicon layer exposed between the gate patterns. A plurality of polysilicon spacers are formed over a sidewall of the silicon bodies, and each contains a second-conductivity type dopant. A contact plug is electrically connected to at least one of the polysilicon spacers.
    Type: Grant
    Filed: May 3, 2010
    Date of Patent: January 8, 2013
    Assignee: SK Hynix Inc.
    Inventor: Tae Su Jang
  • Patent number: 8350344
    Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a charge storage structure and a gate. The charge storage structure is formed on a substrate. The gate is formed on the charge storage structure. The gate includes a lower portion formed of silicon and an upper portion formed of metal silicide. The upper portion of the gate has a width greater than that of the lower portion of the gate.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: January 8, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Min Son, Woon-Kyung Lee
  • Patent number: 8338919
    Abstract: A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active regions in the p-MOS region; a p-MOS gate electrode structure formed above the semiconductor substrate, traversing the p-MOS active region and defining a p-MOS channel region under the p-MOS gate electrode structure; a compressive stress film selectively formed above the p-MOS active region and covering the p-MOS gate electrode structure; and a stress released region selectively formed above the element isolation region in the p-MOS region and releasing stress in the compressive stress film, wherein a compressive stress along the gate length direction and a tensile stress along the gate width direction are exerted on the p-MOS channel region. The performance of the semiconductor device can be improved by controlling the stress separately for the active region and element isolation region.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: December 25, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Shigeo Satoh
  • Patent number: 8330211
    Abstract: A memory device includes a substrate, a plurality of wordlines arranged over the substrate, a plurality of pillars formed over the substrate between the wordlines, a gate electrode surrounding external walls of the pillars to be connected to the wordlines, and an insulation layer for insulating one sidewall of each wordline from the gate electrode.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: December 11, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Min-Gyu Sung, Kwan-Yong Lim
  • Patent number: 8330234
    Abstract: In a semiconductor device, a gate electrode having a uniform composition prevents deviation in a work function. Controlling a Vth provides excellent operation properties. The semiconductor device includes an NMOS transistor and a PMOS transistor with a common line electrode. The line electrode includes electrode sections (A) and (B) and a diffusion barrier region formed over an isolation region so that (A) and (B) are kept out of contact. The diffusion barrier region meets at least one of: (1) The diffusion coefficient in the above diffusion barrier region of the constituent element of the above electrode section (A) is lower than the interdiffusion coefficient of the constituent element between electrode section (A) materials; and (2) The diffusion coefficient in the above diffusion barrier region of the constituent element of the above electrode section (B) is lower than the interdiffusion coefficient of the constituent element between electrode section (B) materials.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: December 11, 2012
    Assignee: NEC Corporation
    Inventor: Takashi Hase
  • Patent number: 8330219
    Abstract: A semiconductor device includes: a semiconductor substrate having a first conductivity type; a well having a second conductivity type and provided inside the semiconductor substrate; a first impurity region having the first conductivity type and provided within the well; a second impurity region having the second conductivity type, provided inside the well and away from the first impurity region; and a third impurity region having a first conductivity type, provided surrounding the well and away from the second impurity region. In this semiconductor device, the well is formed to be deeper than the first impurity region, the second impurity region, and the third impurity region, in a thickness direction of the semiconductor substrate; and a minimum distance between the first impurity region and the second impurity region is smaller than a minimum distance between the second impurity region and the third impurity region.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: December 11, 2012
    Assignee: Seiko Epson Corporation
    Inventors: Tomoyuki Furuhata, Hideyuki Akanuma, Hiroaki Nitta
  • Publication number: 20120309182
    Abstract: Disclosed herein is a method of forming sidewall spacers for a semiconductor device. In one example, the method comprises forming a gate electrode structure above a semiconducting substrate. performing a non-conformal deposition process to deposit a layer of spacer material above the gate electrode structure and performing an anisotropic etching process on the layer of spacer material to define a first sidewall spacer proximate a first side of the gate electrode structure and a second sidewall spacer proximate a second side of the gate electrode structure, wherein the first and second sidewall spacers have different widths.
    Type: Application
    Filed: May 31, 2011
    Publication date: December 6, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Stefan Flachowsky, Jan Hoentschel, Peter Javorka
  • Patent number: 8309449
    Abstract: A semiconductor and a method for forming the same are disclosed. The method for forming the semiconductor device includes forming a buried gate on a semiconductor substrate including an active region, forming an insulating layer on the semiconductor substrate, selectively removing the insulating layer from at least an upper part of the active region, forming a bit line on an upper part between the buried gates formed on the active region, and forming a storage electrode contact that is formed at both sides of the bit line and has an extended lower part, so that prevents short circuiting between the storage electrode contact and the bit line, and improves contact resistance by enlarging a contact area between the storage electrode contact and the active region, so that unique characteristics of the semiconductor device are improved.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: November 13, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Mun Mo Jeong, Dong Geun Lee
  • Patent number: 8304300
    Abstract: An object is to provide a display device which operates stably with use of a transistor having stable electric characteristics. In manufacture of a display device using transistors in which an oxide semiconductor layer is used for a channel formation region, a gate electrode is further provided over at least a transistor which is applied to a driver circuit. In manufacture of a transistor in which an oxide semiconductor layer is used for a channel formation region, the oxide semiconductor layer is subjected to heat treatment so as to be dehydrated or dehydrogenated; thus, impurities such as moisture existing in an interface between the oxide semiconductor layer and the gate insulating layer provided below and in contact with the oxide semiconductor layer and an interface between the oxide semiconductor layer and a protective insulating layer provided on and in contact with the oxide semiconductor layer can be reduced.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: November 6, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichiro Sakata, Toshinari Sasaki, Miyuki Hosoba
  • Patent number: 8293631
    Abstract: Semiconductor devices are provided which have a tensile and/or compressive strain applied thereto and methods of manufacturing. The structure includes a gate stack comprising an oxide layer, a polysilicon layer and sidewalls with adjacent spacers. The structure further includes an epitaxially grown straining material directly on the polysilicon layer and between portions of the sidewalls. The epitaxially grown straining material, in a relaxed state, strains the polysilicon layer.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: October 23, 2012
    Assignee: International Business Machines Corporation
    Inventors: Thomas W Dyer, Haining S Yang
  • Patent number: 8293319
    Abstract: By irradiating a first substrate which is an evaporation donor substrate including a function layer in which films having different refractive indexes (high-refractive index films and low refractive index films) are stacked with first light (wavelength=?1), a material layer over the first substrate is patterned, and by irradiating the first substrate with second light (wavelength=?2) which is different from ?1, the material layer which is patterned is evaporated onto a second substrate which is a deposition target substrate.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: October 23, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisao Ikeda, Takahiro Ibe
  • Patent number: 8288262
    Abstract: A method for fabricating a semiconductor device is described. A polysilicon layer is formed on a substrate. The polysilicon layer is doped with an N-type dopant. A portion of the polysilicon layer is then removed to form a plurality of dummy patterns. Each dummy pattern has a top, a bottom, and a neck arranged between the top and the bottom, where the width of the neck is narrower than that of the top. A dielectric layer is formed on the substrate to cover the substrate disposed between adjacent dummy patterns, and the top of each dummy pattern is exposed. Thereafter, the dummy patterns are removed to form a plurality of trenches in the dielectric layer. A plurality of gate structures is formed in the trenches, respectively.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: October 16, 2012
    Assignee: United Microelectronics Corp.
    Inventor: Chun-Hsien Lin