Compound Semiconductor Patents (Class 438/590)
  • Patent number: 10115801
    Abstract: After forming a trench extending through a sacrificial gate layer to expose a surface of a doped bottom semiconductor layer, a diode including a first doped semiconductor segment and a second doped semiconductor segment having a different conductivity type than the first doped semiconductor segment is formed within the trench. The sacrificial gate layer that laterally surrounds the first doped semiconductor segment and the second doped semiconductor segment is subsequently replaced with a gate structure to form a gated diode.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: October 30, 2018
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Alexander Reznicek
  • Patent number: 9935106
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to multi-finger devices in multiple-gate-contacted-pitch, integrated structures and methods of manufacture. The structure includes: a first plurality of fin structures formed on a substrate having a channel surface in a {110} plane; and a second plurality of fin structures formed on the substrate with a channel surface in a {100} plane, positioned in relation to the first plurality of fin structures.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: April 3, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Edward J. Nowak, Brent A. Anderson, Robert R. Robison
  • Patent number: 9887089
    Abstract: A semiconductor structure having a T-shaped electrode. The electrode has a top portion and a narrower stem portion extending from the top portion to a surface of a substrate. A solid dielectric layer has side portions juxtaposed and abutting sidewalls of a lower portion of the stem of electrode. A bottom surface of the top portion is spaced from an upper surface portion by a non-solid dielectric, such as air.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: February 6, 2018
    Assignee: Raytheon Company
    Inventors: Kiuchul Hwang, Dale M. Shaw, Adrian D. Williams
  • Patent number: 9728466
    Abstract: Semiconductor devices having vertical FET (field effect transistor) devices with metallic source/drain regions are provided, as well as methods for fabricating such vertical FET devices. For example, a semiconductor device includes a first source/drain region formed on a semiconductor substrate, a vertical semiconductor fin formed on the first source/drain region, a second source/drain region formed on an upper surface of the vertical semiconductor fin, a gate structure formed on a sidewall surface of the vertical semiconductor fin, and an insulating material that encapsulates the vertical semiconductor fin and the gate structure. The first source/drain region comprises a metallic layer and at least a first epitaxial semiconductor layer. For example, the metallic layer of the first source/drain region comprises a metal-semiconductor alloy such as silicide.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: August 8, 2017
    Assignee: International Business Machines Corporation
    Inventors: Hari V. Mallela, Robert R. Robison, Reinaldo Vega, Rajasekhar Venigalla
  • Patent number: 9640637
    Abstract: A method for producing a semiconductor device includes a first step of forming a first insulating film around a fin-shaped semiconductor layer; a second step of forming a first pillar-shaped semiconductor layer, a first dummy gate, a second pillar-shaped semiconductor layer, and a second dummy gate; a third step of forming a third dummy gate and a fourth dummy gate; a fourth step of forming a third diffusion layer in an upper portion of the fin-shaped semiconductor layer, in a lower portion of the first pillar-shaped semiconductor layer, and in a lower portion of the second pillar-shaped semiconductor layer; a fifth step of forming a gate electrode and a gate line around the first pillar-shaped semiconductor layer and forming a contact electrode and a contact line around the second pillar-shaped semiconductor layer; and a sixth step of forming first to fifth contacts.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: May 2, 2017
    Assignee: UNISANTIS ELECTRONICS SIGNAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 9553173
    Abstract: A field effect transistor device comprises a semiconductor substrate, a doped source layer arranged on the semiconductor substrate, an insulator layer arranged on the doped source layer, a fin arranged on the insulator layer, a source region extension portion extending from the doped source layer and through the fin, a gate stack arranged over a channel region of the fin and adjacent to the source region extension portion, a drain region arranged on the fin adjacent to the gate stack; the drain region having a graduated doping concentration.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: January 24, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chung H. Lam, Chung-hsun Lin, Darsen D. Lu, Philip J. Oldiges
  • Patent number: 9356431
    Abstract: A high power blue-violet Ill-nitride semipolar laser diode (LD) with an output power in excess of 1 W, a slope efficiency of more than 1 W/A, and an external quantum efficiency (EQE) in excess of 25% and more preferably, in excess of 35%. These operating characteristics make these laser diodes suitable for use in solid state lighting systems.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: May 31, 2016
    Assignee: The Regents of the University of California
    Inventors: Arash Pourhashemi, Robert M. Farrell, Steven P. DenBaars, James S. Speck, Shuji Nakamura
  • Patent number: 9214552
    Abstract: A method for fabricating a semiconductor device is disclosed. The method includes forming a gate stack over a substrate, forming spacers adjoining opposite sidewalls of the gate stack, forming a sacrificial layer adjoining the spacers, removing a portion of the sacrificial layer, removing a portion of the spacers to form a recess cavity below the left spacers. Then, a strain feature is formed in the recess cavity. The disclosed method provides an improved method by providing a space between the spacer and the substrate for forming the strained feature, therefor, to enhance carrier mobility and upgrade the device performance.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: December 15, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Yu-Lien Huang
  • Patent number: 9209200
    Abstract: A method for forming a semiconductor device includes forming gate stacks on a crystalline semiconductor layer; depositing a spacer layer over a top and sidewalls of the gate stacks; recessing the semiconductor layer between the gates stacks; and depositing a non-conformal layer over the gates stacks and within the recesses such that the non-conformal layer forms a pinch point over the recesses. The non-conformal layer is etched at a bottom of the recesses through the pinch point to expose the semiconductor layer. Dopant species are implanted at the bottom of the recesses through the pinch point in the semiconductor layer. The non-conformal layer is stripped, and source and drain material is grown in the recesses. The dopant species are activated to form PN junctions to act as a junction butt between portions of the semiconductor layer.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: December 8, 2015
    Assignee: GLOBALFOUNDRIES INC
    Inventors: Edward P. Maciejewski, Chengwen Pei, Gan Wang, Geng Wang
  • Patent number: 9041061
    Abstract: A structure and method for fabricating a III-V compound semiconductor-containing heterostructure field-effect transistor (FET) with self-aligned and overlapped extensions using a replacement gate process is disclosed. The a III-V compound semiconductor-containing heterostructure field-effect transistor (FET) structure may be formed by forming a III-V compound semiconductor-containing heterostructure having multiple layers and a T-shaped gate structure using a gate replacement process. The T-shaped gate structure may be formed with a bottom surface substantially below an upper surface of the III-V compound semiconductor-containing heterostructure and an upper surface above the III-V compound semiconductor-containing heterostructure. An undoped region may be formed below the bottom surface of the T-shaped gate structure on a layer of the III-V compound semiconductor-containing heterostructure.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: Amlan Majumdar, Yanning Sun
  • Patent number: 9041060
    Abstract: A structure and method for fabricating a III-V compound semiconductor-containing heterostructure field-effect transistor (FET) with self-aligned and overlapped extensions using a gate last process is disclosed. The a III-V compound semiconductor-containing heterostructure field-effect transistor (FET) structure may be formed by forming a III-V compound semiconductor-containing heterostructure having at least one layer; forming a doped contact layer on the III-V compound semiconductor-containing heterostructure; and forming a gate structure having a bottom surface substantially below an upper surface of the III-V compound semiconductor-containing heterostructure and an upper surface above the doped contact layer. An undoped region may be formed below the bottom surface of the T-shaped gate structure on a layer of the III-V compound semiconductor-containing heterostructure.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: Amlan Majumdar, Yanning Sun
  • Publication number: 20150132937
    Abstract: There is provided a method of manufacturing a semiconductor device including: preparing a semiconductor substrate having an active region; forming a dielectric layer for gate insulation on the active region; forming a curing layer with a material containing germanium (Ge) on the dielectric layer; heat-treating the curing layer; and removing the curing layer. The germanium-containing material may be silicon germanium (SiGe) or germanium (Ge).
    Type: Application
    Filed: July 28, 2014
    Publication date: May 14, 2015
    Inventors: Jin Soak Kim, Gab Jin Nam, Dong Hwan Kim, Su Hwan Kim, Toshiro Nakanishi, Sung Kweon Baek, Tae Hyun An, Eun Ae Chung
  • Publication number: 20150108503
    Abstract: A semiconductor device of the present disclosure includes a semiconductor layer provided on a main surface of a substrate. A cell region is provided with a gate insulating film disposed on the semiconductor layer and a gate electrode disposed on the gate insulating film, and a wiring region is provided with a field insulating film disposed on the semiconductor layer and a gate wire disposed on the field insulating film. An end of the field insulating film has a convex shape in a cross section perpendicular to the main surface of the substrate, and an upper surface of the field insulating film is rougher than an upper surface of a portion of the gate wire below which the field insulating film is not disposed.
    Type: Application
    Filed: October 9, 2014
    Publication date: April 23, 2015
    Inventor: CHIAKI KUDOU
  • Patent number: 9006064
    Abstract: A gate dielectric can be formed by depositing a first silicon oxide material by a first atomic layer deposition process. The thickness of the first silicon oxide material is selected to correspond to at least 10 deposition cycles of the first atomic layer deposition process. The first silicon oxide material is converted into a first silicon oxynitride material by a first plasma nitridation process. A second silicon oxide material is subsequently deposited by a second atomic layer deposition process. The second silicon oxide material is converted into a second silicon oxynitride material by a second plasma nitridation process. Multiple repetitions of the atomic layer deposition process and the plasma nitridation process provides a silicon oxynitride material having a ratio of nitrogen atoms to oxygen atoms greater than 1/3, which can be advantageously employed to reduce the leakage current through a gate dielectric.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michael P. Chudzik, Barry P. Linder, Shahab Siddiqui
  • Patent number: 8999772
    Abstract: Two layers of protection films are formed such that a sheet resistance at a portion directly below the protection film is higher than that at a portion directly below the protection film. The protection films are formed, for example, of SiN film, as insulating films. The protection film is formed to be higher, for instance, in hydrogen concentration than the protection film so that the protection film is higher in refractive index the protection film. The protection film is formed to cover a gate electrode and extend to the vicinity of the gate electrode on an electron supplying layer. The protection film is formed on the entire surface to cover the protection film. According to this configuration, the gate leakage is significantly reduced by a relatively simple configuration to realize a highly-reliable compound semiconductor device achieving high voltage operation, high withstand voltage, and high output.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: April 7, 2015
    Assignee: Fujitsu Limited
    Inventors: Masahito Kanamura, Kozo Makiyama
  • Publication number: 20150060958
    Abstract: A semiconductor device and a manufacturing method of the same are provided. The semiconductor device includes a substrate and a stacked structure vertically formed on the substrate. The stacked structure includes a plurality of conductive layers and a plurality of insulating layers, and the conductive layers and the insulating layers are interlaced. At least one of the conductive layers has a first doping segment having a first doping property and a second doping segment having a second doping property, the second doping property being different from the first doping property. The interface between the first doping segment and the second doping segment has a grain boundary.
    Type: Application
    Filed: September 3, 2013
    Publication date: March 5, 2015
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shih-Hung Chen, Erh-Kun Lai
  • Patent number: 8940579
    Abstract: Disclosed are new methods of fabricating metal oxide thin films and nanomaterial-derived metal composite thin films via solution processes at low temperatures (<400° C.). The present thin films are useful as thin film semiconductors, thin film dielectrics, or thin film conductors, and can be implemented into semiconductor devices such as thin film transistors and thin film photovoltaic devices.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: January 27, 2015
    Assignees: Northwestern University, Polyera Corporation
    Inventors: Antonio Facchetti, Tobin J. Marks, Mercouri G. Kanatzidis, Myung-Gil Kim, William Christopher Sheets, He Yan, Yu Xia
  • Patent number: 8940567
    Abstract: A III-nitride semiconductor device which includes a barrier body between the gate electrode and the gate dielectric thereof.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: January 27, 2015
    Assignee: International Rectifier Corporation
    Inventors: Robert Beach, Zhi He, Jianjun Cao
  • Patent number: 8921147
    Abstract: A multi-stage method and apparatus for vaporizing and depositing a tellurium containing semiconductor material on a substrate.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: December 30, 2014
    Assignee: First Solar, Inc.
    Inventors: Arnold Allenic, Zhigang Ban, John Barden, Benjamin Milliron, Rick C. Powell
  • Patent number: 8916459
    Abstract: A compound semiconductor device having mesa-shaped element region, and excellent characteristics are provided. The compound semiconductor device has: an InP substrate; an epitaxial lamination mesa formed above the InP substrate and including a channel layer, a carrier supply layer above the channel layer and a contact cap layer above the carrier supply layer; ohmic source electrode and drain electrode formed on the cap layer; a recess formed by removing the cap layer between the source and drain electrodes, and exposing the carrier supply layer; an insulating film formed on the cap layer and retracted from an edge of the cap layer away from the recess; a gate electrode extending from the carrier supply layer in the recess to outside of the mesa; and air gap formed by removing side portion of the channel layer facing the gate electrode outside the mesa.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: December 23, 2014
    Assignee: Fujitsu Limited
    Inventors: Tsuyoshi Takahashi, Kozo Makiyama
  • Patent number: 8895378
    Abstract: Two layers of protection films are formed such that a sheet resistance at a portion directly below the protection film is higher than that at a portion directly below the protection film. The protection films are formed, for example, of SiN film, as insulating films. The protection film is formed to be higher, for instance, in hydrogen concentration than the protection film so that the protection film is higher in refractive index the protection film. The protection film is formed to cover a gate electrode and extend to the vicinity of the gate electrode on an electron supplying layer. The protection film is formed on the entire surface to cover the protection film. According to this configuration, the gate leakage is significantly reduced by a relatively simple configuration to realize a highly-reliable compound semiconductor device achieving high voltage operation, high withstand voltage, and high output.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: November 25, 2014
    Assignee: Fujitsu Limited
    Inventors: Masahito Kanamura, Kozo Makiyama
  • Patent number: 8883599
    Abstract: A method for manufacturing a semiconductor device includes preparing a base substrate; forming a semiconductor layer on the base substrate; forming an ohmic electrode part having ohmic electrode lines, on the semiconductor layer; and forming a Schottky electrode part, which is disposed on the semiconductor layer to be spaced apart from the ohmic electrode lines and has Schottky electrode lines parallel to the ohmic electrode lines, wherein forming the ohmic electrode part further comprises forming an ohmic electrode plate connected to one end of the ohmic electrode lines, forming the Schottky electrode part further comprises forming a Schottky electrode plate connected one end of the Schottky electrode lines, and one line of the Schottky electrode lines is disposed between two of the ohmic electrode lines to thereby achieve an interdigited configuration in which the ohmic electrode part and the Schottky electrode part are formed.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: November 11, 2014
    Assignee: Samsung Electro-Mechanics Co., Ld.
    Inventors: Woo Chul Jeon, Jung Hee Lee, Young Hwan Park, Ki Yeol Park
  • Patent number: 8865494
    Abstract: A compound semiconductor light-emitting element characterized by high transmittance of an electrically conductive film, low contact resistance and low sheet resistance of electrically conductive film is manufactured. The manufacturing method for a compound semiconductor light-emitting element of the present invention includes the steps of: forming a semiconductor layer formed of a group III nitride semiconductor, including a light-emitting layer on a substrate; forming an electrically conductive film on the side of the semiconductor layer opposite to the side contacting the substrate; conducting first annealing on the electrically conductive film in an atmosphere containing oxygen; conducting second annealing on the electrically conductive film in an atmosphere not containing oxygen; and exposing the electrically conductive film to atmospheric air between the step of conducting first annealing and the step of conducting second annealing.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: October 21, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshimi Tanimoto, Takanori Sonoda, Hideaki Ikeda
  • Patent number: 8836049
    Abstract: A semiconductor structure includes a work function metal layer, a (work function) metal oxide layer and a main electrode. The work function metal layer is located on a substrate. The (work function) metal oxide layer is located on the work function metal layer. The main electrode is located on the (work function) metal oxide layer. Moreover a semiconductor process forming said semiconductor structure is also provided.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: September 16, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Min-Chuan Tsai, Hsin-Fu Huang, Chi-Mao Hsu, Chin-Fu Lin, Chien-Hao Chen, Wei-Yu Chen, Chi-Yuan Sun, Ya-Hsueh Hsieh, Tsun-Min Cheng
  • Publication number: 20140242788
    Abstract: One illustrative method disclosed herein includes performing an atomic layer deposition (ALD) process at a temperature of less than 400° C. to deposit a layer of silicon dioxide on a germanium-containing region of semiconductor material and forming a gate structure of a transistor device above the layer of silicon dioxide.
    Type: Application
    Filed: February 25, 2013
    Publication date: August 28, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Gabriela Dilliway, Dina Triyoso, Elke Erben, Rimoon Agaiby
  • Patent number: 8809133
    Abstract: There is provided a technique to form a single crystal semiconductor thin film or a substantially single crystal semiconductor thin film. A catalytic element for facilitating crystallization of an amorphous semiconductor thin film is added to the amorphous semiconductor thin film, and a heat treatment is carried out to obtain a crystalline semiconductor thin film. After the crystalline semiconductor thin film is irradiated with ultraviolet light or infrared light, a heat treatment at a temperature of 900 to 1200° C. is carried out in a reducing atmosphere. The surface of the crystalline semiconductor thin film is extremely flattened through this step, defects in crystal grains and crystal grain boundaries disappear, and the single crystal semiconductor thin film or substantially single crystal semiconductor thin film is obtained.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: August 19, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Tamae Takano
  • Patent number: 8809150
    Abstract: LDD regions are provided with high implant energy in devices with reduced thickness poly-silicon layers and source/drain junctions. Embodiments include forming an oxide layer on a substrate surface, forming a poly-silicon layer over the oxide layer, forming first and second trenches through the oxide and poly-silicon layers and below the substrate surface, defining a gate region therebetween, implanting a dopant in a LDD region through the first and second trenches, forming spacers on opposite side surfaces of the gate region and extending into the first and second trenches, and implanting a dopant in a source/drain region below each of the first and second trenches.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: August 19, 2014
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Guowei Zhang, Purakh Raj Verma, Zhiqing Li
  • Patent number: 8772139
    Abstract: A method of manufacturing a MOSFET includes the steps of preparing a silicon carbide substrate, forming an active layer on the silicon carbide substrate, forming a gate oxide film on the active layer, forming a gate electrode on the gate oxide film, forming a source contact electrode on the active layer, and forming a source interconnection on the source contact electrode. The step of forming the source interconnection includes the steps of forming a conductor film on the source contact electrode and processing the conductor film by etching the conductor film with reactive ion etching. Then, the method of manufacturing a MOSFET further includes the step of performing annealing of heating the silicon carbide substrate to a temperature not lower than 50° C. after the step of processing the conductor film.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: July 8, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Toru Hiyoshi, Takeyoshi Masuda
  • Patent number: 8748274
    Abstract: A method for fabricating a semiconductor device includes: forming a GaN-based semiconductor layer on a substrate; forming a gate insulating film of aluminum oxide on the GaN-based semiconductor layer at a temperature equal to or lower than 450° C.; forming a protection film on an upper surface of the gate insulating film; performing a process with an alkaline solution in a state in which the upper surface of the gate insulating film is covered with the protection film; and forming a gate electrode on the gate insulating film.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: June 10, 2014
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventors: Ken Nakata, Seiji Yaegashi
  • Patent number: 8741759
    Abstract: A method for fabricating a semiconductor device is disclosed. The method includes forming a gate stack over a substrate, forming spacers adjoining opposite sidewalls of the gate stack, forming a sacrificial layer adjoining the spacers, removing a portion of the sacrificial layer, removing a portion of the spacers to form a recess cavity below the left spacers. Then, a strain feature is formed in the recess cavity. The disclosed method provides an improved method by providing a space between the spacer and the substrate for forming the strained feature, therefor, to enhance carrier mobility and upgrade the device performance.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: June 3, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Yu-Lien Huang
  • Patent number: 8723227
    Abstract: A protection clamp is provided between a first terminal and a second terminal, and includes a multi-gate high electron mobility transistor (HEMT), a current limiting circuit, and a forward trigger control circuit. The multi-gate HEMT includes a drain/source, a source/drain, a first depletion-mode (D-mode) gate, a second D-mode gate, and an enhancement-mode (E-mode) gate disposed between the first and second D-mode gates. The drain/source and the first D-mode gate are connected to the first terminal and the source/drain and the second D-mode gate are connected to the second terminal. The forward trigger control and the current limiting circuits are coupled between the E-mode gate and the first and second terminals, respectively. The forward trigger control circuit provides an activation voltage to the E-mode gate when a voltage of the first terminal exceeds a voltage of the second terminal by a forward trigger voltage.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: May 13, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Srivatsan Parthasarathy, Javier Alejandro Salcedo, Shuyun Zhang
  • Publication number: 20140127893
    Abstract: A method for fabricating a semiconductor device is disclosed. The method includes forming a gate stack over a substrate, forming spacers adjoining opposite sidewalls of the gate stack, forming a sacrificial layer adjoining the spacers, removing a portion of the sacrificial layer, removing a portion of the spacers to form a recess cavity below the left spacers. Then, a strain feature is formed in the recess cavity. The disclosed method provides an improved method by providing a space between the spacer and the substrate for forming the strained feature, therefor, to enhance carrier mobility and upgrade the device performance.
    Type: Application
    Filed: November 8, 2012
    Publication date: May 8, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Yu-Lien Huang
  • Patent number: 8703566
    Abstract: A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain SiC. At least some of the peripheral devices do not include any carbonated portions. A transistor includes a first source/drain, a second source/drain, a channel including a carbonated portion of a semiconductive substrate that contains SiC between the first and second sources/drains and a gate operationally associated with opposing sides of the channel.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: April 22, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Patent number: 8673401
    Abstract: A method for depositing gallium using a gallium ink, comprising, as initial components: a gallium component comprising gallium; a stabilizing component; an additive; and, a liquid carrier; is provided comprising applying the gallium ink on the substrate; heating the applied gallium ink to eliminate the additive and the liquid carrier, depositing gallium on the substrate; and, optionally, annealing the deposited gallium.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: March 18, 2014
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: David Mosley, David Thorsen
  • Patent number: 8658488
    Abstract: A graphene layer is provided onto at least an upper surface of a first dielectric material which includes at least one first conductive region contained therein. At least one semiconductor device is formed using the graphene layer as an element of the at least one semiconductor device. After forming the at least one semiconductor device, a second dielectric material is formed covering the graphene layer, the at least one semiconductor device, and portions of the first dielectric material. The second dielectric that is formed includes at least one second conductive region contained therein, and the at least one second conductive region is in contact with a conductive element of the at least one semiconductor device.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: February 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Christos D. Dimitrakopoulos, Guy Cohen, Stephen M. Gates, Alfred Grill, Timothy J. McArdle, Chun-yung Sung
  • Patent number: 8652949
    Abstract: A method of manufacturing a semiconductor wafer, which includes: a semiconductor substrate made of silicon and having both a central area and an outer periphery area; and a compound semiconductor layer made of a nitride-based semiconductor and formed on the semiconductor substrate, the method comprising: forming a growth inhibition layer to inhibit the compound semiconductor layer from growing on a tapered part provided in the outer periphery area of the semiconductor substrate; and growing the compound semiconductor layer on at least the central area of the semiconductor substrate, after the growth inhibition layer has been formed.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: February 18, 2014
    Assignee: Sanken Electric Co., Ltd.
    Inventor: Ken Sato
  • Patent number: 8637373
    Abstract: In a method of manufacturing a transistor, a gate structure is formed on a substrate including silicon. An upper portion of the substrate adjacent to the gate structure is etched to form a first recess in the substrate. A preliminary first epitaxial layer including silicon-germanium is formed in the first recess. An upper portion of the preliminary first epitaxial layer is etched to form a second recess on the preliminary first epitaxial layer. In addition, a portion of the preliminary first epitaxial layer adjacent to the second recess is etched to thereby transform the preliminary first epitaxial layer into a first epitaxial layer. A second epitaxial layer including silicon-germanium is formed in the second recess located on the first epitaxial layer.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: January 28, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hoi-Sung Chung, Dong-Suk Shin, Dong-Hyuk Kim, Myung-Sun Kim
  • Patent number: 8629012
    Abstract: An integrated circuit structure includes a substrate and a first and a second plurality of III-V semiconductor layers. The first plurality of III-V semiconductor layers includes a first bottom barrier over the substrate; a first channel layer over the first bottom barrier; and a first top barrier over the first channel layer. A first field-effect transistor (FET) includes a first channel region, which includes a portion of the first channel layer. The second plurality of III-V semiconductor layers is over the first plurality of III-V semiconductor layers and includes a second bottom barrier; a second channel layer over the second bottom barrier; and a second top barrier over the second channel layer. A second FET includes a second channel region, which includes a portion of the second channel layer.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: January 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Heng-Kuang Lin, Pei-Chin Chiu, Jen-Inn Chyi, Han-Chieh Ho, Clement Hsingjen Wann, Chih-Hsin Ko, Cheng-Hsien Wu
  • Patent number: 8617941
    Abstract: Graphene or carbon nanotube-based transistor devices and techniques for the fabrication thereof are provided. In one aspect, a transistor is provided. The transistor includes a substrate; a carbon-based material on the substrate, wherein a portion of the carbon-based material serves as a channel region of the transistor and other portions of the carbon-based material serve as source and drain regions of the transistor; a patterned organic buffer layer over the portion of the carbon-based material that serves as the channel region of the transistor; a conformal high-k gate dielectric layer disposed selectively on the patterned organic buffer layer; metal source and drain contacts formed on the portions of the carbon-based material that serve as the source and drain regions of the transistor; and a metal top-gate contact formed on the high-k gate dielectric layer.
    Type: Grant
    Filed: January 16, 2011
    Date of Patent: December 31, 2013
    Assignee: International Business Machines Corporation
    Inventors: Damon Brooks Farmer, Qinghuang Lin, Yu-Ming Lin
  • Patent number: 8609482
    Abstract: In sophisticated transistor elements, long-term threshold voltage shifts in transistors comprising a threshold adjusting semiconductor alloy may be reduced by reducing the roughness of an interface formed between the threshold adjusting semiconductor material and the gate dielectric material. To this end, a portion of the threshold adjusting semiconductor material may be oxidized and may be removed prior to forming the high-k dielectric material.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: December 17, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Carsten Reichel, Annekathrin Zeun, Martin Trentzsch
  • Patent number: 8592800
    Abstract: A semiconductor emitter, or a precursor therefor, has a substrate and one or more textured semiconductor layers deposited onto the substrate in a nonpolar orientation. The textured layers enhance light extraction, and the use of nonpolar orientation greatly enhances internal quantum efficiency compared to conventional devices. Both the internal and external quantum efficiencies of emitters of the invention can be 70-80% or higher. The invention provides highly efficient light emitting diodes suitable for solid state lighting.
    Type: Grant
    Filed: March 9, 2009
    Date of Patent: November 26, 2013
    Assignee: Trustees of Boston University
    Inventors: Theodore D. Moustakas, Adam Moldawer, Anirban Bhattacharyya, Joshua Abell
  • Patent number: 8581261
    Abstract: Two layers of protection films are formed such that a sheet resistance at a portion directly below the protection film is higher than that at a portion directly below the protection film. The protection films are formed, for example, of SiN film, as insulating films. The protection film is formed to be higher, for instance, in hydrogen concentration than the protection film so that the protection film is higher in refractive index the protection film. The protection film is formed to cover a gate electrode and extend to the vicinity of the gate electrode on an electron supplying layer. The protection film is formed on the entire surface to cover the protection film. According to this configuration, the gate leakage is significantly reduced by a relatively simple configuration to realize a highly-reliable compound semiconductor device achieving high voltage operation, high withstand voltage, and high output.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: November 12, 2013
    Assignee: Fujitsu Limited
    Inventors: Masahito Kanamura, Kozo Makiyama
  • Patent number: 8563414
    Abstract: Conductive carbon films having a resistivity of less than about 0.2 Ohm-cm, preferably less than about 0.05 Ohm-cm, are deposited by PECVD. Conductive carbon films are essentially free of sp3-hybridized carbon and contain predominantly sp2 carbon, based on IR spectral features. Carbon content of the films is at least about 75% atomic C. Conductive carbon films may contain hydrogen, but are typically hydrogen-poor, containing less than about 20% H. In some embodiments, conductive carbon films further contain nitrogen (N). For example, conductive films having a CxHyNz composition, where nitrogen is present at between about 5-10% atomic, have both high conductivity and low roughness, because introduction of nitrogen delays formation of crystallites in the film. The films are deposited at a process temperature of at least about 620° C., and at a pressure of less than about 20 Torr in a dual-frequency plasma process dominated by low frequency (LF) plasma.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: October 22, 2013
    Assignee: Novellus Systems, Inc.
    Inventors: Keith Fox, Dennis Hausmann
  • Patent number: 8563088
    Abstract: A method for preparing a Group 1a-1b-3a-6a material using a selenium/Group 1b ink comprising, as initial components: a selenium component comprising selenium, an organic chalcogenide component having a formula selected from RZ—Z?R? and R2—SH, a Group 1b component and a liquid carrier; wherein Z and Z? are each independently selected from sulfur, selenium and tellurium; wherein R is selected from H, C1-20 alkyl group, a C6-20 aryl group, a C1-20 alkylhydroxy group, an arylether group and an alkylether group; wherein R? and R2 are selected from a C1-20 alkyl group, a C6-20 aryl group, a C1-20 alkylhydroxy group, an arylether group and an alkylether group; and wherein the selenium/Group 1b ink is a stable dispersion.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: October 22, 2013
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: Kevin Calzia, David Mosley, David L. Thorsen, Charles R. Szmanda
  • Patent number: 8557644
    Abstract: According to one disclosed embodiment, a monolithic vertically integrated composite device comprises a double sided semiconductor substrate having first and second sides, a group IV semiconductor layer formed over the first side and comprising at least one group IV semiconductor device, and a group III-V semiconductor body formed over the second side and comprising at least one group III-V semiconductor device electrically coupled to the at least one group IV semiconductor device. The composite device may further comprise a substrate via and/or a through-wafer via providing electric coupling. In one embodiment, the group IV semiconductor layer may comprise an epitaxial silicon layer, and the at least one group IV semiconductor device may be a combined FET and Schottky diode (FETKY) fabricated on the epitaxial silicon layer. In one embodiment, the at least one group III-V semiconductor device may be a III-nitride high electron mobility transistor (HEMT).
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: October 15, 2013
    Assignee: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Patent number: 8530978
    Abstract: A field effect transistor (FET) having a source contact to a channel layer, a drain contact to the channel layer, and a gate contact on a barrier layer over the channel layer, the FET including a dielectric layer on the barrier layer between the source contact and the drain contact and over the gate contact, and a field plate on the dielectric layer, the field plate connected to the source contact and extending over a space between the gate contact and the drain contact and the field plate comprising a sloped sidewall in the space between the gate contact and the drain contact.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: September 10, 2013
    Assignee: HRL Laboratories, LLC
    Inventors: Rongming Chu, Zijian “Ray” Li, Karim S. Boutros, Shawn Burnham
  • Patent number: 8501596
    Abstract: A manufacturing method of a microelectronic device including at least one semi-conductor zone which rests on a support and which exhibits a germanium concentration gradient in a direction parallel to the principal pane of the support.
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: August 6, 2013
    Assignee: Commissariat a l'Energie Atmoique
    Inventors: Benjamin Vincent, Vincent Destefanis
  • Patent number: 8492261
    Abstract: A method for manufacturing a III-V CMOS device is disclosed. The device includes a first and second main contact and a control contact. In one aspect, the method includes providing the control contact by using damascene processing. The method thus allows obtaining a control contact with a length of between about 20 nm and 5 ?m and with good Schottky behavior. Using low-resistive materials such as Cu allows reducing the gate resistance thus improving the high-frequency performance of the III-V CMOS device.
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: July 23, 2013
    Assignee: IMEC
    Inventors: Marleen Van Hove, Joff Derluyn
  • Patent number: 8476125
    Abstract: Fabrication methods of a high frequency (sub-micron gate length) operation of AlInGaN/InGaN/GaN MOS-DHFET, and the HFET device resulting from the fabrication methods, are generally disclosed. The method of forming the HFET device generally includes a novel double-recess etching and a pulsed deposition of an ultra-thin, high-quality silicon dioxide layer as the active gate-insulator. The methods of the present invention can be utilized to form any suitable field effect transistor (FET), and are particular suited for forming high electron mobility transistors (HEMT).
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: July 2, 2013
    Assignee: University of South Carolina
    Inventors: M. Asif Khan, Vinod Adivarahan
  • Publication number: 20130154019
    Abstract: A semiconductor device including an NMOS region and a PMOS region; the NMOS region having a gate structure including a first high-k gate dielectric, a first work function setting metal and a gate electrode fill material; the PMOS region having a gate structure comprising a second high-k gate dielectric, a second work function setting metal and a gate electrode fill material; wherein the first gate dielectric is different than the second gate dielectric and the first work function setting metal is different than the second work function setting metal. Also disclosed are methods for fabricating the semiconductor device which include a gate last process.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 20, 2013
    Applicant: International Business Machines Corporation
    Inventors: Takashi Ando, Changhwan Choi, Kisik Choi, Vijay Narayanan