Abstract: There is provided a method of producing an organic semiconductor device by which an organic semiconductor device having an optional configuration can easily be produced. A method of producing an organic semiconductor device comprising a gate insulating layer, a gate electrode, a source electrode, a drain electrode, and an organic semiconductor layer is provided which comprises the steps of: 1) forming a monomer layer of a conductive polymer precursor; 2) maintaining the monomer layer at a given temperature; and 3) applying an oxidizing agent solution to a desired location of the monomer layer to obtain a polymer layer of a desired conductivity.

Abstract: Very fast integrated OPL circuits, such as pseudo-NMOS OPL and dynamic OPL, comprising CMOS gate arrays having ultra-thin vertical NMOS transistors are disclosed. The ultra-thin vertical NMOS transistors of the CMOS gate arrays are formed with relaxed silicon germanium (SiGe) body regions with graded germanium content and strained silicon channels.

Abstract: A self-aligned enhancement mode metal-oxide-compound semiconductor field effect transistor (10) includes a gate insulating structure comprised of a first oxide layer that includes a mixture of indium and gallium oxide compounds (30) positioned immediately on top of the compound semiconductor structure, and a second insulating layer comprised of either gallium oxygen and rare earth elements or gallium sulphur and rare earth elements positioned immediately on top of said first layer. Together the lower indium gallium oxide compound layer and the second insulating layer form a gate insulating structure. The gate insulating structure and underlying compound semiconductor layer (15) meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure (14). The first oxide layer serves to passivate and protect the underlying compound semiconductor surface from the second insulating layer and atmospheric contamination.

Abstract: Methods are provided herein for treating substrate surfaces in preparation for subsequent nucleation-sensitive depositions (e.g., polysilicon or poly-SiGe) and adsorption-driven deposition (e.g. atomic layer deposition or ALD). Prior to depositing, the surface is treated with non-depositing plasma products. The treated surface more readily nucleates polysilicon and poly-SiGe (such as for a gate electrode), or more readily adsorbs ALD reactants (such as for a gate dielectric). The surface treatment provides surface moieties more readily susceptible to a subsequent deposition reaction, or more readily susceptible to further surface treatment prior to deposition. By changing the surface termination of the substrate with a low temperature radical treatment, subsequent deposition is advantageously facilitated without depositing a layer of any appreciable thickness and without significantly affecting the bulk properties of the underlying material.

Abstract: In a heterojunction FET in which source and drain areas are formed by carrying out high temperature annealing process after carrying out ion implantation in areas to be formed into source and drain areas, conventionally, the N-type carrier supply layer and the N-type active layer are doped with Si. In place of doping with Si, doping with Se or Te is adopted. Thereby, in high temperature annealing process for activating the ion implanted areas, which serves as source and drain areas, unlike the Si donor, inactivation of donor due to reaction with F-atoms occurs scarcely with respect to the diffusion of F-atoms on the surface of the epitaxial substrate, which adhered during the process. Further, since the Se and Te are impurities from VI-family, when the Se or Te occupies any grid position of atoms from III-family or V-family, the Se or Te serves as the donor. Accordingly, a high performance heterojunction FET of little deterioration of the FET characteristics can be obtained.

Abstract: In a method for fabricating a semiconductor device, a first semiconductor layer of aluminum gallium nitride is first formed on a substrate, and a protection film containing silicon is then formed on the first semiconductor layer in such a manner that a device-isolation region is uncovered. Thereafter, the method further includes the step of heat-treating the first semiconductor layer in an oxidizing atmosphere whose temperature is adjusted to be within a range of 950° C. or more and 1050° C. or less.

Abstract: A power semiconductor device including a non-doped GaN channel layer, an n-type Al0.2Ga0.8N barrier layer formed on the channel layer, a p-type Al0.1Ga0.9N semiconductor layer selectively formed on the barrier layer, a drain electrode positioned at one of both sides of the semiconductor layer and formed on the barrier layer, an insulating film formed on the barrier layer adjacent to the semiconductor layer between at least semiconductor layer and drain electrode, and a field plate electrode formed on the insulating film.

Abstract: Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.

Abstract: An embodiment of the invention is a gate electrode 70 having a nitrided high work function metal alloy 170 and a low work function nitrided metal alloy 190. Another embodiment of the invention is a method of manufacturing a gate electrode 70 that includes forming and then patterning and etching a layer of high work function nitrided metal alloy 170, forming a layer of low work function nitrided metal alloy 190, and then patterning and etching layers 170 and 190.

Abstract: A method of depositing a film of a metal chalcogenide. The first of these methods includes the steps of: contacting at least one metal chalcogenide, a hydrazine compound and optionally, an elemental chalcogen, to produce a solution of a hydrazinium-based precursor of the metal chalcogenide; applying the solution of the hydrazinium-based precursor of the metal chalcogenide onto a substrate to produce a film of the precursor; and thereafter annealing the film of the precursor to remove excess hydrazine and hydrazinium chalcogenide salts to produce a metal chalcogenide film on the substrate.

Abstract: A microwave field effect transistor (10) has a high conductivity gate (44) overlying a double heterojunction structure (14, 18, 22) that has an undoped channel layer (18). The heterojunction structure overlies a substrate (12). A recess layer that is a not intentionally doped (NID) layer (24) overlies the heterojunction structure and is formed with a predetermined thickness that minimizes impact ionization effects at an interface of a drain contact of source/drain ohmic contacts (30) and permits significantly higher voltage operation than previous step gate transistors. Another recess layer (26) is used to define a gate dimension. A Schottky gate opening (42) is formed within a step gate opening (40) to create a step gate structure. A channel layer (18) material of InxGa1?xAs is used to provide a region of electron confinement with improved transport characteristics that result in higher frequency of operation, higher power density and improved power-added efficiency.

Abstract: A field-effect transistor (FET) device and method of fabrication uses an electrically interconnected polycrystalline or microcrystalline silicon carbide (SiC) gate having a lower electron affinity and higher work function than a polysilicon gate FET. The smaller threshold voltage magnitude of the SiC gate FET allows reduced power supply voltages (lowering power consumption and facilitating downward scaling of transistor dimensions), and enables higher switching speeds and improved performance. The smaller threshold voltage magnitudes are obtained without ion-implantation, which is particularly useful for SOI and thin film transistor devices. Threshold voltage magnitudes are stable in spite of subsequent thermal processing steps. N-channel threshold voltages are optimized for enhancement mode.

Abstract: A method for forming and the structure of a strained lateral channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a single crystal semiconductor substrate wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region. The invention reduces the problem of leakage current from the source region via the hetero-junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials and alloy composition.

Abstract: The present invention provides a method for manufacturing a semiconductor device comprising a III-V semiconductor substrate, and an insulating layer deposited on the substrate by Atomic Layer Deposition (ALD). The use of ALD to deposit the insulating layer was found to facilitate the creation of active devices that avoid Fermi layer pinning. In addition, such insulating layer may be advantageously used as a passivation layer in III-V substrate based active devices and transistors.

Abstract: In a field effect transistor, an Si layer 11, an SiC (Si1-yCy) channel layer 12, a CN gate insulating film 13 made of a carbon nitride layer (CN) and a gate electrode 14 are deposited in this order on an Si substrate 10. The thickness of the SiC channel layer 12 is set to a value that is less than or equal to the critical thickness so that a dislocation due to a strain does not occur according to the carbon content. A source region 15 and a drain region 16 are formed on opposite sides of the SiC channel layer 12, and a source electrode 17 and a drain electrode 18 are provided on the source region 15 and the drain region 16, respectively.

Abstract: A semiconductor device includes an AlGaN film formed on a GaN film on a substrate, a gate electrode formed on the AlGaN film, and source and drain electrodes formed on either side of the gate electrode on the AlGaN film. An n-type InxGayAl1-x-yN film is interposed between the source and drain electrodes and the AlGaN film. Alternatively, the semiconductor device includes an n-type InxGayAl1-x-yN film formed on a GaN film on a substrate, a gate electrode formed on the InxGayAl1-x-yN film, and source and drain electrodes formed on either side of the gate electrode on the InxGayAl1-x-yN film.

Abstract: The quantum semiconductor device comprises a first semiconductor layer 18 on a substrate 10 with a two-dimensional carrier gas formed in; a quantum dot 20 formed on the first semiconductor layer 18; a second semiconductor layer 22 formed on the first semiconductor layer 18, covering the quantum dot 20; a dot-shaped structure 24 formed on the surface of the second semiconductor layer 22 at the position above the quantum dot 20; and an oxide layer 26a, 26b formed on the surface of the second semiconductor layer 22 on both sides of the dot-shaped structure 24. The crystal strains generated in the surface of the semiconductor layer 22 due to the presence of the quantum dot 20 causes the dot-shaped structure 24 to grow on the semiconductor layer 22 surface at the position which is accurately above the quantum dot 20. This permits the oxide layer 26a, 26b to be formed with the dot-shaped structure 24 as a mark, and the source/drain regions 30a, 30b can be formed with the oxide layer 26a, 26b as a mark.

Abstract: The present invention is a field effect transistor having a strained semiconductor substrate and Schottky-barrier source and drain electrodes, and a method for making the transistor. The bulk charge carrier transport characteristic of the Schottky barrier field effect transistor minimizes carrier surface scattering, which enables the strained substrate to provide improved power and speed performance characteristics in this device, as compared to conventional devices.

Abstract: A semiconductor device and its manufacturing method. The semiconductor device has a semi-insulating GaAs substrate 310, a GaAs buffer layer 321 that is formed on the semi-insulating GaAs substrate 310, AlGaAs buffer layer 322, a channel layer 323, a spacer layer 324. a carrier supply layer 325, a spacer layer 326, a Schottky layer 327 that is composed of an undope In0.48Ga0.52P, an n+-type GaAs cap layer 328, a gate electrode 330 that is formed on the Schottky layer 327, is composed of LaB6 and has a Schottky contact with the Schottky layer 327 and ohmic electrodes 340 that are formed on the n+-type GaAs cap layer 328.

Abstract: A polysilicon FET is built atop a SiC diode to form a MOSgated device. The polysilicon FET includes an invertible layer of polysilicon atop the surface of a SiC diode which has spaced diode diffusions. A MOSgate is formed on the polysilicon layer and the energization of the gate causes an inversion channel in the invertible layer to form a majority carrier conduction path from a top source electrode to a bottom drain electrode. Forward voltage is blocked in part by the polysilicon FET and in larger part by the depletion of the silicon carbide area between the spaced diode diffusions.

Abstract: A method of producing a strain-relaxed Si—Ge virtual substrate for use in a semiconductor substrate which is planar and of less defects for improving the performance of a field effect semiconductor device, which method comprises covering an Si—Ge layer formed on an SOI substrate with an insulating layer to prevent evaporation of Ge, heating the mixed layer of silicon and germanium at a temperature higher than a solidus curve temperature determined by the germanium content of the Si—Ge layer into a partially melting state, and diffusing germanium to the Si layer on the insulating layer, thereby solidifying the molten Si—Ge layer to obtain a strain-relaxed Si—Ge virtual substrate.

Abstract: Contacts for a nitride based transistor and methods of fabricating such contacts provide a recess through a regrowth process. The contacts are formed in the recess. The regrowth process includes fabricating a first cap layer comprising a Group III-nitride semiconductor material. A mask is fabricated and patterned on the first cap layer. The pattern of the mask corresponds to the pattern of the recesses for the contacts. A second cap layer comprising a Group III-nitride semiconductor material is selectively fabricated (e.g. grown) on the first cap layer utilizing the patterned mask. Additional layers may also be formed on the second cap layer. The mask may be removed to provide recess(es) to the first cap layer, and contact(s) may be formed in the recess(es). Alternatively, the mask may comprise a conductive material upon which a contact may be formed, and may not require removal.

Abstract: The field effect device consisting of a substrate, a conducting backplane formed in the substrate, a source and a drain disposed above the conductive backplane, a gate insultatively disposed above the substrate between the source and drain, and a backgate contact electrically coupled to the conducting backplane.

Abstract: A structure with an optically active layer embedded in a Si wafer, such that the outermost epitaxial layer exposed to the CMOS processing equipment is always Si or another CMOS-compatible material such as SiO2. Since the optoelectronic layer is completely surrounded by Si, the wafer is fully compatible with standard Si CMOS manufacturing. For wavelengths of light longer than the bandgap of Si (1.1 &mgr;m), Si is completely transparent and therefore optical signals can be transmitted between the embedded optoelectronic layer and an external waveguide using either normal incidence (through the Si substrate or top Si cap layer) or in-plane incidence (edge coupling).

Abstract: A hot-electron bolometric mixer/detector, which uses the nonlinearities of the heated two-dimensional electron gas medium, is described. Electrons in the illustrative embodiment of the present invention are “velocity-cooled” rather than “diffusion-cooled” or “phonon-cooled” like hot-electron bolometric mixer/detectors in the prior art. The illustrative embodiment is velocity-cooled when the elastic mean-free path of the electrons is greater than the channel length, L, of the mixer/detector. In this case, the motion of the hot electrons is more accurately modeled by their speed rather than in accordance with diffusion models. This leads to a mixer/detector with a wider modulation bandwidth at a lower power than is exhibited by mixer/detectors in the prior art.

Abstract: A method for fabricating heterojunction field effect transistors (HFET) and a family of HFET layer structures are presented. In the method, a step of depositing a HFET semiconductor structure onto a substrate is performed. Next, a photoresist material is deposited. Portions of the photoresist material are removed corresponding to source and drain pad pairs. A metal layer is deposited onto the structure, forming source pad and drain pad pairs. The photoresist material is removed, exposing the structure in areas other than the source and drain pad pairs. Each source and drain pad pair has a corresponding exposed area. The structure is annealed and devices are electrically isolated. The exposed area of each device is etched to form a gate recess and a gate structure is formed in the recess. Semiconductor layer structures for GaN/AlGaN HFETs are also presented.

Abstract: A semiconductor device has a semiconductor substrate, a first transistor having a first gate electrode formed of a polycrystalline silicon germanium film as formed above said semiconductor substrate, and a second transistor having a second gate electrode which is formed of a polycrystalline silicon germanium film as formed above the semiconductor substrate and which is different in concentration of germanium from the first gate electrode.

Abstract: A compound semiconductor device includes a gate electrode, a drain electrode, and a source electrode, and a p-type semiconductor layer provided between the gate electrode and the drain electrode. The p-type semiconductor layer has a lower acceptor concentration on a drain side thereof than that on a gate side thereof.

Abstract: A semiconductor switching device of mirror logic includes two FETs having a gate width of 600 &mgr;m, a common input terminal, two control terminal and two output terminals. The resistors connecting the control terminals and the gate electrodes of FETs are placed underneath a pad metal layer extending from the common input terminal. Both FETs extend into the space between the control terminals and the output terminals. The device can be housed in the same package as the device of non-mirror logic.

Abstract: The present invention provides for a method of manufacturing a Group III-V compound semiconductor, which grows a nitrogen-contained Group III-V compound semiconductor of the p-type conductivity, without performing any particular post-processing after growing the compound semiconductor, and which prevents a deterioration in the yield of manufacturing light emitting elements due to post-processing. A first embodiment is directed to a method of manufacturing a Group III-V compound semiconductor which contains p-type impurities and which is expressed by a general formula InxGayAlzN (0≧x≧1,0≧z≧1, x+y+z=1), by thermal decomposition vapor phase method using metalorganics, the method being characterized in that carrier gas is inert gas in which the concentration of hydrogen is 0.5 % or smaller by volume.

Abstract: Disclosed is an ISFET comprising a H+-sensing membrane consisting of RF-sputtering a-WO3. The a-WO3/SiO2-gate ISFET of the present invention is very sensitive in aqueous solution, and particularly in acidic aqueous solution. The sensitivity of the present ISFET ranges from 50 to 58 mV/pH. In addition, the disclosed ISFET has high linearity. Accordingly, the disclosed ISFET can be used to detect effluent.

Abstract: A field-effect semiconductor device includes a channel layer; a barrier structure formed on the channel layer and including a plurality of semiconductor layers; a plurality of ohmic electrodes formed above the barrier structure; and a Schottky electrode formed on the barrier structure between the ohmic electrodes. The barrier structure has an electron-affinity less than that of the channel layer and includes at least two heavily doped layers and a lightly doped layer provided therebetween.

Abstract: An improved optical modulator and photodetector suitable for high frequency operation and compatible with monolithic microwave integrated circuit technology. Typical implementations use a reversed biased diode containing not intentionally doped (NID) optically active region sandwiched between conductive layers of p-doped and n-doped semiconductor layers, respectively. With monochromatic optical radiation incident upon the device a photocurrent (comprising of an electron-hole pair created for each photon absorbed) can be generated using the optical nonlinearity of the multiple quantum well structure inside the active region. This photocurrent can be used in an external circuit to provide photocurrent feedback to the device itself.

Abstract: A semiconductor switching device includes two FETs with different device characteristics, a common input terminal, and two output terminals. A signal transmitting FET has a gate width of 500 &mgr;m and a signal receiving FET has a gate width of 400 &mgr;m. A resistor connecting a gate electrode and a control terminal of the signal transmitting FET is tightly configured to provide expanding space for the FET. Despite the reduced size, the switching device can allow a maximum power of 22.5 dBm to pass through because of the asymmetrical device design. The switching device operates at frequencies of 2.4 GHz or higher without use of shunt FET.

Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.

Abstract: Non-volatile, resistance variable memory devices, integrated circuit elements, and methods of forming such devices are provided. According to one embodiment of a method of the invention, a memory device can be fabricated by depositing a chalcogenide material onto a first (lower) electrode, sputter depositing a thin diffusion layer of a conductive material over the chalcogenide material, diffusing metal from the diffusion layer into the chalcogenide material resulting in a metal-comprising resistance variable material, and then plating a conductive material to a desired thickness to form a second (upper) electrode.

Abstract: A method for fabricating a quantum dot, which can be used to fabricate a single electron memory device. The method includes forming a first insulation layer on a semiconductor layer, then forming a second insulation layer on the first insulation layer. Next, the second insulation layer is patterned to form an opening to partially expose the upper surface of the first insulation layer. Using the opening in the second insulation layer, a silicon ion is then implanted into the first insulation layer through the opening by using a tilt angle ion implantation method. Finally, the semiconductor layer is treated to re-crystallize the silicon ion implanted into the first insulation layer.

Abstract: The present invention provides a field effect transistor (FET) having, on a semi-insulating compound semiconductor substrate, a buffer layer; an active layer that includes a channel layer made of a first conductive-type epitaxial growth layer (e.g. InGaAs); source/drain electrodes formed on a first conductive-type contact layer which is formed either on said active layer or on a lateral face thereof; a gate layer made of a second conductive-type epitaxial growth layer (e.g. p+-GaAs); and a gate electrode formed on said gate layer; which further has, between said second conductive-type gate layer and said channel layer, a semiconductor layer (e.g. InGaP) that rapidly lowers the energy of the valance band spreading from said gate layer to said channel layer. The present invention improves withstand voltage characteristic of a FET having a pn junction in a gate region (JFET) and realizes stable operations of a JFET.

Abstract: Method for fabricating a polycide dual gate in a semiconductor device fabricates a dual gate having polycide gate electrodes. The polycide can be a cobalt polycide, for example. The method can include forming polysilicon pattern layers on a first and a second regions of a semiconductor substrate, forming a blocking layer to expose top surfaces of the polysilicon pattern layers and mask the substrate, and forming a metal layer on an entire surface and then is annealed to form a gate electrode having a stack of the polysilicon pattern layer under a silicide layer. Impurity ions of opposite conductivities in the first and second regions can be respectively deposited and diffused to form source/drain regions in surfaces of the substrate on both sides of the gate electrode. The implanted impurity ions can further implant ions in the silicide/polysilicon pattern layer gate to reduce fabrication steps or simplify the fabrication process.

Abstract: A method of eliminating weakness caused by high-density plasma (HDP) dielectric layer is provided. Before forming the HDP dielectric layer, a hot thermal oxide (HTO) layer is previously formed on the semiconductor substrate to serve as a buffer layer. The HTO layer eliminates the defect between the HDP dielectric layer and a cap nitride layer and releases the stress therebetween, and thereby preventing bit line leakage issue.

Abstract: A process for forming a dual damascene opening, in a composite layer comprised with low k layers, to accommodate a dual damascene type, copper structure, has been developed. The process features the use of a silicon oxide layer, formed on the surfaces of the composite layer, exposed in the narrow diameter, via hole component of the dual damascene opening. The silicon oxide layer prevents via poisoning, or outgassing of amines or hydroxyls from the low k layers exposed in the via hole opening, that can evolve during a subsequent photolithographic development cycle, used to define the trench shape component of the dual damascene opening. The protective silicon oxide layer is conformally formed on the exposed-surfaces of the via hole component, via a liquid phase deposition procedure, performed at room temperature.

Abstract: An n type InP buried layer 22 with Se or S added in an above 5×1018 cm−3 concentration is formed on an active layer mesa stripe 18 having a surface with an SiO2 film 16 formed on at a peripheral part of the mesa stripe 18 other than the surface with the SiO2 film 16 formed on. Accordingly, the buried layer can be grown without the over growth.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials.

Abstract: A method is disclosed for forming multiple gate insulators on a strained semiconductor heterostructure as well as the devices and circuits formed therefrom. In an embodiment, the method includes the steps of depositing a first insulators on the strained semiconductor heterostructure, removing at least a portion of the first insulators from the strained semiconductor heterostructure, and depositing a second insulators on the strained semiconductor heterostructure.

Abstract: A high electron mobility transistor has a channel layer overlain by an electron supply layer held in contact with a gate electrode, and source/drain electrodes form ohmic contact together with cap layers, and resistive etching stopper are inserted between the cap layers and the electron supply layers for preventing the electron supply layer from over-etching, wherein extremely thin delta-doped layers are formed between the etching stopper layers and the electron supply layer so that the resistance between the electron supply layer and the source/drain electrodes are reduced.

Abstract: The field effect device consisting of a substrate, a conducting backplane formed in the substrate, a source and a drain disposed above the conductive backplane, a gate insultatively disposed above the substrate between the source and drain, and a backgate contact electrically coupled to the conducting backplane.

Abstract: Provided are a semiconductor device which shows excellent negative differential conductance or negative transconductance and is manufactured without a complicated manufacturing process and a method of manufacturing the same. The semiconductor device includes a channel layer serving as a conduction region and a floating region electrically separated from the channel layer. Provided between the channel layer and the floating region is a quantum well layer constituted with a pair of barrier layers and a quantum well layer sandwiched between the pair of barrier layers. A source electrode and a drain electrode are electrically connected to the channel layer. A gate electrode is provided in an opposite position from the well layer in the floating region. When changing a drain voltage relative to a predetermined gate voltage, drain current characteristics show negative differential conductance.

Abstract: A method of fabricating a vertical channel transistor, comprising the following steps. A semiconductor substrate having an upper surface is provided. A high doped N-type lower epitaxial silicon layer is formed on the semiconductor substrate. A low doped P-type middle epitaxial silicon layer is formed on the lower epitaxial silicon layer. A high doped N-type upper epitaxial silicon layer is formed on the middle epitaxial silicon layer. The lower, middle, and upper epitaxial silicon layers are etched to form a epitaxial layer stack defined by isolation trenches. Oxide is formed within the isolation trenches. The oxide is etched to form a gate trench within one of the isolation trenches exposing a sidewall of the epitaxial layer stack facing the gate trench. Multi-quantum wells or a stained-layer super lattice is formed on the exposed epitaxial layer stack sidewall. A gate dielectric layer is formed on the multi-quantum wells or the stained-layer super lattice and within the gate trench.

Abstract: A CMOS inverter having a heterostructure including a Si substrate, a relaxed Si1−xGex, layer on the Si substrate, and a strained surface layer on said relaxed Si1−xGex, layer; and a pMOSFET and an nMOSFET, wherein the channel of said pMOSFET and the channel of the nMOSFET are formed in the strained surface layer. Another embodiment provides an integrated circuit having a heterostructure including a Si substrate, a relaxed Si1−xGex, layer on the Si substrate, and a strained layer on the relaxed Si1−xGex, layer; and a p transistor and an n transistor formed in the heterostructure, wherein the strained layer comprises the channel of the n transistor and the p transistor, and the n transistor and the p transistor are interconnected in a CMOS circuit.

Abstract: A process of manufacturing a semiconductor device includes the steps of forming a stacked structure of a first III-V compound semiconductor layer containing In and having a composition different from InP and a second III-V compound semiconductor layer containing In. The second III-V compound semiconductor layer is formed over the first III-V compound semiconductor layer and growing an InP layer at regions adjacent the stacked structure to form a stepped structure of InP. The process further includes the step of wet-etching the stepped structure and the second III-V compound semiconductor layer using an etchant containing hydrochloric acid and acetic acid to remove at least the second III-V compound semiconductor layer.