Abstract: Methods for forming conductive layers. A layer of metal composite is applied on a substrate, comprising a plurality of metal flakes, a plurality of nanometer metal spheres, and a plurality of mixed metal precursors. The plurality of mixed metal precursors comprises a mixture of inorganic salts and organic acidic salts. The layer of metal composite is cured to induce an exothermic reaction, thereby forming a conductive layer on the substrate at a relatively low temperature (<200° C.).

Abstract: Provided is a method for preparing a compound semiconductor substrate. The method includes coating a plurality of spherical balls on a substrate, growing a compound semiconductor epitaxial layer on the substrate coated with the spherical balls while allowing voids to be formed under the spherical balls, and cooling the substrate on which the compound semiconductor epitaxial layer is grown so that the substrate and the compound semiconductor epitaxial layer are self-separated along the voids. The spherical ball treatment can reduce dislocation generations. In addition, because the substrate and the compound semiconductor epitaxial layer are separated through the self-separation, there is no need for laser lift-off process.

Abstract: A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch a gate stack (30, 32) formed over a substrate (36), thereby forming an etched gate (33) having a vertical sidewall profile (35). By constructing the gate stack (30, 32) with a graded material composition of silicon-based layers, the composition of which is selected to counteract the etching tendencies of the predetermined sequence of patterning and etching steps, a more idealized vertical gate sidewall profile (35) may be obtained.

Abstract: Disclosed is a producing method of a semiconductor device comprising a step of forming a tunnel insulating film of a flash device comprising a first nitridation step of forming a first silicon oxynitride film by nitriding a silicon oxide film formed on a semiconductor silicon base by one of plasma nitridation and thermal nitridation, the plasma nitridation carrying out nitridation process by using a gas activated by plasma discharging a first gas including a first compound which has at least a nitrogen atom in a chemical formula thereof, and the thermal nitridation carrying out nitridation process using heat by using a second gas including a second compound which has at least a nitrogen atom in a chemical formula thereof, and a second nitridation step of forming a second silicon oxynitride film by nitriding the first silicon oxynitride film by the other of the plasma nitridation and the thermal nitridation.

Abstract: A method is disclosed for preparing a surface of a Group III-Group V compound semiconductor for epitaxial deposition. The III-V semiconductor surface is treated with boron (B) at a temperature of between about 250° C. and about 350° C. A suitable form for supplying B for the surface treatment is diborane. The B treatment can be followed by epitaxial growth, for instance by a Group IV semiconductor, at temperatures similar to those of the B treatment. The method yields high quality heterojunction, suitable for fabricating a large variety of device structures.

Abstract: A semiconductor-based structure includes a substrate layer, a compressively strained semiconductor layer adjacent to the substrate layer to provide a channel for a component, and a tensilely strained semiconductor layer disposed between the substrate layer and the compressively strained semiconductor layer. A method for making an electronic device includes providing, on a strain-inducing substrate, a first tensilely strained layer, forming a compressively strained layer on the first tensilely strained layer, and forming a second tensilely strained layer on the compressively strained layer. The first and second tensilely strained layers can be formed of silicon, and the compressively strained layer can be formed of silicon and germanium.

Abstract: Pile ups of threading dislocations in thick graded buffer layer are reduced by enhancing dislocation gliding. During formation of a graded SiGe buffer layer, deposition of SiGe from a silicon precursor and a germanium precursor is interrupted one or more times with periods in which the flow of the silicon precursor to the substrate is stopped while the flow of the germanium precursor to the substrate is maintained.

Abstract: A method for forming a semiconductor structure. The method includes providing a semiconductor structure which includes (a) substrate, (b) a first semiconductor region on top of the substrate, wherein the first semiconductor region comprises a first semiconductor material and a second semiconductor material, which is different from the first semiconductor material, and wherein the first semiconductor region has a first crystallographic orientation, and (c) a third semiconductor region on top of the substrate which comprises the first and second semiconductor materials and has a second crystallographic orientation. The method further includes forming a second semiconductor region and a fourth semiconductor region on top of the first and the third semiconductor regions respectively. Both second and fourth semiconductor regions comprise the first and second semiconductor materials.

Abstract: A method of providing a p-type substrate, disposing a pad oxide layer on the p-type substrate, disposing a nitride layer on the pad oxide layer, forming a nitride window in the nitride layer, disposing a field oxide in the nitride window, disposing a polysilicon gate over the field oxide, and diffusing a n-doped region in the p-type substrate, thereby forming at least one single-electron tunnel junction between the polysilicon gate and the n-doped region.

Abstract: A method for manufacturing a III-V CMOS device is disclosed. The device includes a first and second main contact and a control contact. In one aspect, the method includes providing the control contact by using damascene processing. The method thus allows obtaining a control contact with a length of between about 20 nm and 5 ?m and with good Schottky behavior. Using low-resistive materials such as Cu allows reducing the gate resistance thus improving the high-frequency performance of the III-V CMOS device.

Abstract: In one aspect, a method includes fabricating a device. The device includes a gallium nitride (GaN) layer, a diamond layer disposed on the GaN layer and a gate structure disposed in contact with the GaN layer and the diamond layer. In another aspect, a device includes a gallium nitride (GaN) layer, a diamond layer disposed on the GaN layer and a gate structure disposed in contact with the GaN layer and the diamond layer.

Abstract: Transistors are fabricated by forming a protective layer having a first opening extending therethrough on a substrate, forming a dielectric layer on the protective layer having a second opening extending therethrough that is wider than the first opening, and forming a gate electrode in the first and second openings. A first portion of the gate electrode laterally extends on surface portions of the protective layer outside the first opening, and a second portion of the gate electrode is spaced apart from the protective layer and laterally extends beyond the first portion on portions of the dielectric layer outside the second opening. Related devices and fabrication methods are also discussed.

Abstract: There is provided a method of manufacturing a semiconductor device, including the following steps: flowing a first precursor gas to the semiconductor substrate within the ALD chamber to form a first discrete monolayer on the semiconductor substrate; flowing an inert purge gas to the semiconductor substrate within the ALD chamber; flowing a second precursor gas to the ALD chamber to react with the first precursor gas which has formed the first monolayer, thereby forming a first discrete compound monolayer; and flowing an inert purge gas; and forming a second discrete compound monolayer above the semiconductor substrate by the same process as that for forming the first discrete compound monolayer. There is also provided a semiconductor device in which the charge trapping layer is a dielectric layer containing the first and second discrete compound monolayers formed by the ALD method.

Abstract: In a manufacturing flow for adapting the band gap of the semiconductor material with respect to the work function of a metal-containing gate electrode material, a strain-inducing material may be deposited to provide an additional strain component in the channel region. For instance, a layer stack with silicon/carbon, silicon and silicon/germanium may be used for providing the desired threshold voltage for a metal gate while also providing compressive strain in the channel region.

Abstract: A method of forming a III-V compound semiconductor structure (10) comprises providing a III-V compound semiconductor substrate including a semi-insulating substrate (12) having at least one epitaxial layer formed thereon and further having a gate insulator (14) overlying the at least one epitaxial layer. The at least one epitaxial layer formed on the semi-insulating substrate comprises an epi-structure suitable for use in the formation of a channel of a III-V compound semiconductor MOSFET device, wherein the channel (30) having a first polarity. The method further comprises forming a charge layer (22) at a surface of the gate insulator, the charge layer having a second polarity, wherein the second polarity is opposite to the first polarity.

Abstract: A semiconductor device, includes: a first conductivity type semiconductor base having a main face; a hetero semiconductor region contacting the main face of the semiconductor base and forming a hetero junction in combination with the semiconductor base, the semiconductor base and the hetero semiconductor region in combination defining a junction end part; a gate insulating film defining a junction face in contact with the semiconductor base and having a thickness; and a gate electrode disposed adjacent to the junction end part via the gate insulating film and defining a shortest point in a position away from the junction end part by a shortest interval, a line extending from the shortest point to a contact point vertically relative to the junction face, forming such a distance between the contact point and the junction end part as to be smaller than the thickness of the gate insulating film contacting the semiconductor base.

Abstract: An embodiment of the invention is a transistor formed in part by a ferromagnetic semiconductor with a sufficiently high ferromagnetic transition temperature to coherently amplify spin polarization of a current. For example, an injected non-polarized control current creates ferromagnetic conditions within the transistor base, enabling a small spin-polarized signal current to generate spontaneous magnetization of a larger output current.

Abstract: A method of depositing a film of a metal chalcogenide including the steps of: contacting an isolated hydrazinium-based precursor of a metal chalcogenide and a solvent having therein a solubilizing additive to form a solution of a complex thereof; applying the solution of the complex onto a substrate to produce a coating of the solution on the substrate; removing the solvent from the coating to produce a film of the complex on the substrate; and thereafter annealing the film of the complex to produce a metal chalcogenide film on the substrate. Also provided is a process for preparing an isolated hydrazinium-based precursor of a metal chalcogenide as well as a thin-film field-effect transistor device using the metal chalcogenides as the channel layer.

Abstract: A method of forming surface irregularities comprises preparing a GaN substrate; forming a mask on a surface of the GaN substrate, the mask defining a surface-irregularity formation region; and wet-etching portions of the surface of the GaN substrate by using the mask as an etching mask. The wet-etching of the GaN substrate is performed until the end of one surface of the GaN substrate to be formed by the wet-etching using the mask meets the end of another surface of the GaN substrate to be formed by the wet-etching using the mask, the another surface being adjacent to the one surface.

Abstract: A method for fabricating heterojunction field effect transistors (HFET) and a family of HFET layer structures are presented. In the method, a step of depositing a HFET semiconductor structure onto a substrate is performed. Next, a photoresist material is deposited. Portions of the photoresist material are removed corresponding to source and drain pad pairs. A metal layer is deposited onto the structure, forming source pad and drain pad pairs. The photoresist material is removed, exposing the structure in areas other than the source and drain pad pairs. Each source and drain pad pair has a corresponding exposed area. The structure is annealed and devices are electrically isolated. The exposed area of each device is etched to form a gate recess and a gate structure is formed in the recess. Semiconductor layer structures for GaN/AlGaN HFETs are also presented.

Abstract: An object of the present invention is to provide a semiconductor device and a manufacturing method thereof which can realize a normally-off field-effect transistor made of a III group nitride semiconductor. The present invention includes: placing a sapphire substrate in a crystal growth chamber; forming a low-temperature GaN buffer layer made of GaN as the III group nitride semiconductor, on a main surface of the sapphire substrate by a MOCVD method; and forming a GaN layer on the low-temperature GaN buffer layer by the MOCVD method. Here, a [11-20] axis of the GaN layer is perpendicular to the main surface of the sapphire substrate.

Abstract: A method of producing a semiconductor device includes the steps of: forming an oxide film on a silicon carbide substrate; forming a gate electrode layer on the oxide film; patterning the gate electrode layer to form a gate electrode; and processing thermally the gate electrode layer or the gate electrode under an oxidation environment. Further, the gate electrode layer or the gate electrode is thermally processed under the oxidation environment at a temperature between 750° C. and 900° C.

Abstract: In one embodiment, the present invention includes an apparatus for forming a transistor that includes a silicon (Si) substrate, a dislocation filtering buffer formed over the Si substrate having a first buffer layer including gallium arsenide (GaAs) nucleation and buffer layers and a second buffer layer including a graded indium aluminium arsenide (InAlAs) buffer layer, a lower barrier layer formed on the second buffer layer formed of InAlAs, and a strained quantum well (QW) layer formed on the lower barrier layer of indium gallium arsenide (InGaAs). Other embodiments are described and claimed.

Abstract: In formation-by-growth of an AlGaN layer 3 as having a double-layered structure, a non-doped AlGaN layer (i-AlGaN layer) having an Al compositional ratio of approximately 15% is formed to a thickness of approximately 3 nm on an i-GaN layer, and further thereon, an AlGaN layer (n-AlGaN layer) doped with Si in a concentration of approximately 2×1018/cm3 and having an Al compositional ratio of approximately 15% is formed to a thickness of approximately 17 nm.

Abstract: The present invention generally is a method for forming a high-k dielectric layer, comprising depositing a hafnium compound by atomic layer deposition to a substrate, comprising, delivering a hafnium precursor to a surface of the substrate, reacting the hafnium precursor and forming a hafnium containing layer to the surface, delivering a nitrogen precursor to the hafnium containing layer, forming at least one hafnium nitrogen bond and depositing the hafnium compound to the surface.

Abstract: In the SiC vertical MOSFET having a low-concentration p-type deposition film provided therein with a channel region and a base region resulting from reverse-implantation to n-type through ion implantation, dielectric breakdown of gate oxide film used to occur at the time of off, thereby preventing a further blocking voltage enhancement. This problem has been resolved by interposing of a low-concentration n-type deposition film between a low-concentration p-type deposition film and a high-concentration gate layer and selectively forming of a base region resulting from reverse-implantation to n-type through ion implantation in the low-concentration p-type deposition film so that the thickness of deposition film between the high-concentration gate layer and each of channel region and gate oxide layer is increased.

Abstract: A field effect transistor with a heterostructure includes a strained monocrystalline semiconductor layer formed on a carrier material, which has a relaxed monocrystalline semiconductor layer made of a first semiconductor material (Si) as the topmost layer. The strained monocrystalline semiconductor layer has a semiconductor alloy (GexSi1-x), where the proportion x of a second semiconductor material can be set freely. Furthermore, a gate insulation layer and a gate layer are formed on the strained semiconductor layer. To define an undoped channel region, drain/source regions are formed laterally with respect to the gate layer at least in the strained semiconductor layer. The possibility of freely setting the Ge proportion x enables a threshold voltage to be set as desired, whereby modern logic semiconductor components can be realized.

Abstract: A method of manufacturing a semiconductor device having: forming a hetero semiconductor layer on at least the major surface of the semiconductor substrate body of a first conductivity type; etching the hetero semiconductor layer selectively by use of a mask layer having openings in way that the hetero semiconductor layer remains to be not etched with a predetermined thickness; oxidizing an exposed parts of the hetero semiconductor layer; forming the hetero semiconductor region by etching a oxidized film formed in the oxidizing; and forming the gate insulating film in a way that the gate insulating film makes an intimate contact with the hetero semiconductor region and the semiconductor substrate body. The bandgap of the hetero semiconductor layer is different from that of the semiconductor substrate body.

Abstract: A method for fabricating heterojunction field effect transistors (HFET) and a family of HFET layer structures are presented. In the method, a step of depositing a HFET semiconductor structure onto a substrate is performed. Next, a photoresist material is deposited. Portions of the photoresist material are removed corresponding to source and drain pad pairs. A metal layer is deposited onto the structure, forming source pad and drain pad pairs. The photoresist material is removed, exposing the structure in areas other than the source and drain pad pairs. Each source and drain pad pair has a corresponding exposed area. The structure is annealed and devices are electrically isolated. The exposed area of each device is etched to form a gate recess and a gate structure is formed in the recess. Semiconductor layer structures for GaN/AlGaN HFETs are also presented.

Abstract: An apparatus in one example comprises an antimonide-based compound semiconductor (ABCS) stack, an upper barrier layer formed on the ABCS stack, and a gate stack formed on the upper barrier layer. The upper barrier layer comprises indium, aluminum, and arsenic. The gate stack comprises a base layer of titanium and tungsten formed on the upper barrier layer.

Abstract: A SiC semiconductor device includes: a SiC substrate having a main surface; a channel region on the substrate; first and second impurity regions on upstream and downstream sides of the channel region, respectively; a gate on the channel region through a gate insulating film. The channel region for flowing current between the first and second impurity regions is controlled by a voltage applied to the gate. An interface between the channel region and the gate insulating film has a hydrogen concentration equal to or greater than 2.6×1020 cm?3. The interface provides a channel surface perpendicular to a (0001)-orientation plane.

Abstract: In an MIS-type GaN-FET, a base layer made of a conductive nitride including no oxygen, here, TaN, is provided on a surface layer as a nitride semiconductor layer to cover at least an area of a lower face of a gate insulation film made of Ta2O5 under a gate electrode.

Abstract: A photodetecting device which is capable of performing photodetection with a high sensitivity in a wide temperature range. A quantum dot structure including an embedding layer and quantum dots embedded by the embedding layer is formed. A quantum well structure including embedding layers and a quantum well layer whose band gap is smaller than those of the embedding layers is formed at a location downstream of the quantum dot structure in the direction of flow of electrons which flow perpendicularly to the quantum dot structure during operation of the photodetecting device. This reduces the temperature dependence of the potential barrier of a photodetecting section, which has to be overcome by electrons, whereby it is possible to lower the potential barrier of the embedding layers at high temperature.

Abstract: A method of using an III-V semiconductor material as a gate electrode is provided. The method includes steps of providing a substrate; forming a gate dielectric layer on the substrate; and forming the III-V semiconductor material on the gate dielectric layer.

Abstract: The invention relates to a laminated layer structure that includes a substrate and a stack of a plurality of layers of a material that includes at least two compounds A and B, wherein compound A has a crystalline structure being sufficient to allow a homo- or heteroepitaxial growth of compound A on the substrate, and wherein at least a part of the layers of the stack have a gradient composition AxB(1-xg), with x being a composition parameter within the range of 0 and 1 and with the composition parameter (1-xg) increasing gradually, in particular linearly, over the thickness of the corresponding layer. In order to improve the quality of the laminated layer structure with respect to the surface roughness and dislocation density, the composition parameter at the interface between the layer in the stack with the gradient composition and the subsequent layer in the stack is chosen to be smaller than the composition parameter (1-xg) of the layer with a gradient composition.

Abstract: A highly reliable electrical device having a multilayered structure of a plurality of thin-film device layers and a method for manufacturing the same are provided. An electrical device includes a plurality of thin-film layers deposited and including a plurality of thin-film device layers each having a semiconductor device, and conductive layers with a predetermined thermal conductivity provided between adjacent thin-film layers. Examples of materials for the conductive layers include metals, metal compounds, resins with a metal or metal compound dispersed, and electrically conductive polymers.

Abstract: Metal chalcogenide films comprising at least one transition metal chalcogenide are prepared by dissolving a metal chalcogenide containing at least one transition metal chalcogenide in a hydrazine compound and, optionally, an excess of chalcogen to provide a precursor of the metal chalcogenide; applying a solution of said precursor onto a substrate to produce a film of said precursor; and annealing the film of the precursor to produce the metal chalcogenide film comprising at least one transition metal chalcogenide. The process can be used to prepare field-effect transistors and photovoltaic devices.

Abstract: A method of growing planar non-polar m-plane III-Nitride material, such as an m-plane gallium nitride (GaN) epitaxial layer, wherein the III-Nitride material is grown on a suitable substrate, such as an m-plane silicon carbide (m-SiC) substrate, using metalorganic chemical vapor deposition (MOCVD). The method includes performing a solvent clean and acid dip of the substrate to remove oxide from the surface, annealing the substrate, growing a nucleation layer such as an aluminum nitride (AlN) on the annealed substrate, and growing the non-polar m-plane III-Nitride epitaxial layer on the nucleation layer using MOCVD.

Abstract: A semiconductor structure including a uniform etch-stop layer. The uniform etch stop layer has a relative etch rate which is less than approximately the relative etch rate of Si doped with 7×1019 boron atoms/cm3. A method for forming a semiconductor structure includes forming a uniform etch-stop layer providing a handle wafer, and bonding the uniform etch-stop layer to the handle wafer. The uniform etch-stop layer has a relative etch rate which is less than approximately the relative etch rate of Si doped with 7×1019 boron atoms/cm3.

Abstract: The present invention provides a method of passivating an oxide compound disposed on a III-V semiconductor substrate. The method is intended for use with dielectric stacks, gallate compounds, and gallium compounds used in gate quality oxide layers. The method includes heating a semiconductor structure at an elevated temperature of between about 230° C. and about 400° C. The semiconductor structure is exposed to an atmosphere that is supersaturated with water vapor or vapor of deuterium oxide. The exposure takes place at elevated temperature and continues for a period of time between about 5 minutes to about 120 minutes. It has been found that the method of the present invention results in a semiconductor product that has significantly improved performance characteristics over semiconductors that are not passivated, or that use a dry hydrogen method of passivation.

Abstract: A method of forming a semiconductor device includes the following steps: providing a plurality of semiconductor layers; providing means for coupling signals to and/or from layers of the device; providing a layer of quantum dots disposed between adjacent layers of the device; and providing an auxiliary layer disposed in one of the adjacent layers, and spaced from the layer of quantum dots, the auxiliary layer being operative to communicate carriers with the layer of quantum dots.

Abstract: A semiconductor device has a sapphire substrate, a semiconductor layer made of GaN provided on the sapphire substrate, a multilayer film provided on the semiconductor layer, and an electrode in ohmic contact with the multilayer film. The multilayer film has been formed by alternately stacking two types of semiconductor layers having different amounts of piezopolarization or different amounts of spontaneous polarization and each containing an n-type impurity so that electrons are induced at the interface between the two types of semiconductor layers. This allows the contact resistance between the electrode and the multilayer film and a parasitic resistance in a current transmission path to be reduced to values lower than in a conventional semiconductor device.

Abstract: A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate structure and in portions of the semiconductor substrate not occupied by the gate structure or by dummy spacers located on the sides of the conductive gate structure. The selectively defined recesses will be used to subsequently accommodate silicon-germanium shapes, with the silicon-germanium shapes located in the recesses in the semiconductor substrate inducing the desired strained channel region. The recessing of the conductive gate structure and of semiconductor substrate portions reduces the risk of silicon-germanium bridging across the surface of sidewall spacers during epitaxial growth of the alloy layer, thus reducing the risk of gate to substrate leakage or shorts.

Abstract: A semiconductor device is disclosed, which comprises a semiconductor substrate, source/drain regions formed in the semiconductor substrate, a gate insulating film formed on a channel region between the source/drain regions, a gate electrode formed on the gate insulating film, and a sidewall insulating film formed on a sidewall surface of the gate electrode, wherein the gate electrode is made of SiGe, the sidewall insulating film is an insulating film obtained by oxidizing the sidewall surface of the gate electrode, and the sidewall insulating film contains silicon oxide as a main component.

Abstract: A method and a layered heterostructure for forming high mobility Ge channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, and a channel structure of a compressively strained epitaxial Ge layer having a higher barrier or a deeper confining quantum well and having extremely high hole mobility for complementary MODFETs and MOSFETs. The invention overcomes the problem of a limited hole mobility due to alloy scattering for a p-channel device with only a single compressively strained SiGe channel layer. This invention further provides improvements in mobility and transconductance over deep submicron state-of-the art Si pMOSFETs in addition to having a broad temperature operation regime from above room temperature (425 K) down to cryogenic low temperatures (0.4 K) where at low temperatures even high device performances are achievable.

Abstract: A method for manufacturing a nitride film including a high-resistivity GaN layer includes a step of allowing a Group-III source gas containing an organic metal compound, a Group-V source gas containing ammonia, a carrier gas for the Group-III source gas, and a carrier gas for the Group-V source gas to flow over a predetermined monocrystalline wafer maintained at 1,000° C. or more and also includes a step of epitaxially growing a nitride film, including a GaN layer, on the monocrystalline wafer by a vapor phase reaction of the source gases. At least one of the carrier gases contains nitrogen while the wafer temperature is being increased before the reaction is carried out. At least one of the carrier gases contains hydrogen and nitrogen and has a total hydrogen and nitrogen content of 90 percent by volume or more in at least one part of the epitaxially growing step.

Abstract: A dielectric layer (50) is formed over a semiconductor (10) that contains a first region (20) and a second region (30). A polysilicon layer is formed over the dielectric layer (50) and over the first region (20) and the second region (30). The polysilicon layer can comprise 0 to 50 atomic percent of germanium. A metal layer is formed over the polysilicon layer and one of the regions and reacted with the underlying polysilicon layer to form a metal silicide or a metal germano silicide. The polysilicon and metal silicide or germano silicide regions are etched to form transistor gate regions (60) and (90) respectively. If desired a cladding layer (100) can be formed above the metal gate structures.

Abstract: A method of depositing a film of a metal chalcogenide including the steps of: contacting an isolated hydrazinium-based precursor of a metal chalcogenide and a solvent having therein a solubilizing additive to form a solution of a complex thereof; applying the solution of the complex onto a substrate to produce a coating of the solution on the substrate; removing the solvent from the coating to produce a film of the complex on the substrate; and thereafter annealing the film of the complex to produce a metal chalcogenide film on the substrate. Also provided is a process for preparing an isolated hydrazinium-based precursor of a metal chalcogenide as well as a thin-film field-effect transistor device using the metal chalcogenides as the channel layer.

Abstract: A method for producing thin, below 6 nm of equivalent oxide thickness, germanium oxynitride layer on Ge-based materials for use as gate dielectric is disclosed. The method involves a two step process. First, nitrogen is incorporated in a surface layer of the Ge-based material. Second, the nitrogen incorporation is followed by an oxidation step. The method yields excellent thickness control of high quality gate dielectrics for Ge-based field effect devices, such as MOS transistors. Structures of devices having the thin germanium oxynitride gate dielectric and processors made with such devices are disclosed, as well.

Abstract: A semiconductor device has a first semiconductor layer composed of a group III–V nitride, an oxide film formed by oxidizing a second semiconductor layer composed of a group III–V nitride to be located on the gate electrode formation region of the first semiconductor layer, an insulating film formed on the oxide film to have a composition different from the composition of the oxide film, and a gate electrode formed on the insulating film.