Tunnelling Dielectric Layer Patents (Class 438/594)
  • Patent number: 10283513
    Abstract: A memory opening is formed through an alternating stack of insulating layers and sacrificial material layers located over a substrate. Annular recesses are formed around the memory opening by laterally recessing the sacrificial material layers with respect to the insulating layers. Annular metal portions are formed over recessed sidewalls of the sacrificial material layers within each of the annular recesses by a selective deposition process. Annular backside blocking dielectrics are formed selectively on inner sidewalls of the annular metal portions employing a layer of a self-assembly material that covers surfaces of the insulating layers and inhibits deposition of a dielectric material thereupon. A memory stack structure is formed in the memory opening, and the sacrificial material layers are replaced with electrically conductive layers. The annular backside blocking dielectrics provide electrical isolation for the annular metal portions, which function as control gate electrodes.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: May 7, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Fei Zhou, Raghuveer S. Makala, Rahul Sharangpani, Adarsh Rajashekhar
  • Patent number: 9960032
    Abstract: Provided herein are methods of forming thin films. In some embodiments, to form a thin film, a precursor adsorption layer including an organic ligand is formed by supplying a precursor including a metal or silicon central atom, and the organic ligand onto a lower structure. An intermediate result layer is formed by supplying a non-oxidant onto the precursor adsorption layer. In forming the intermediate result layer, the organic ligand included in the precursor adsorption layer is substituted with a substituent. An oxide film including the central atom is formed from the intermediate result layer by supplying an oxidant onto the intermediate result layer.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: May 1, 2018
    Assignees: Samsung Electronics Co., Ltd., ADEKA CORPORATION
    Inventors: Jae wan Chang, Youn soo Kim, Tsubasa Shiratori
  • Patent number: 9617638
    Abstract: Disclosed are methods of depositing films of material on semiconductor substrates employing the use of a secondary purge. The methods may include flowing a film precursor into a processing chamber and adsorbing the film precursor onto a substrate in the processing chamber such that the precursor forms an adsorption-limited layer on the substrate. The methods may further include removing at least some unadsorbed film precursor from the volume surrounding the adsorbed precursor by purging the processing chamber with a primary purge gas, and thereafter reacting adsorbed film precursor while a secondary purge gas is flowed into the processing chamber, resulting in the formation of a film layer on the substrate. The secondary purge gas may include a chemical species having an ionization energy and/or a disassociation energy equal to or greater than that of O2. Also disclosed are apparatuses which implement the foregoing processes.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: April 11, 2017
    Assignee: Lam Research Corporation
    Inventors: Adrien LaVoie, Hu Kang, Purushottam Kumar, Shankar Swaminathan, Jun Qian, Frank Pasquale, Chloe Baldasseroni
  • Patent number: 9177807
    Abstract: Even when a semiconductor device having field effect transistors driven by relatively different power supply voltages provided over a semiconductor substrate is manufactured by the gate-last process, the breakdown voltage of the transistor on the higher voltage side can be ensured. When forming, over the substrate by the gate-last process, a MOSFET of a core region driven by a first power supply voltage and a MOSFET of a high-voltage region driven by a second power supply voltage higher than the first power supply voltage, the thickness of the hard mask film formed over a dummy gate film of the high-voltage region is made thicker than that of the hard mask film formed over a dummy gate film of the core region, prior to a process of patterning a dummy gate of the MOSFET of the core region and the MOSFET of the high-voltage region. Thereby, the breakdown voltage of MOSFET of the high-voltage region can be ensured.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: November 3, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Hirofumi Shinohara
  • Patent number: 9117754
    Abstract: Methods are disclosed for extending floating gate regions within floating gate cells to form sub-lithographic features. Related floating gate cells and non-volatile memory (NVM) systems are also disclosed. In part, the disclosed embodiments utilize a spacer etch to form extended floating gate regions and floating gate slits with sub-lithographic dimensions thereby achieving desired increased spacing between control gate layers and doped regions underlying floating gate structures while still allowing for reductions in the overall size of floating-gate NVM cells. These advantageous results are achieved in part by depositing an additional floating gate layer over previously formed floating gate regions and then using the spacer etch to form the extended floating gate regions as sidewall structures and sub-lithographic floating gate slits. The resulting floating gate structures reduce breakdown down risks, thereby improving device reliability.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: August 25, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Anirban Roy, Craig A. Cavins
  • Patent number: 9041088
    Abstract: Disclosed are non-volatile memory devices and methods of manufacturing the same. The non-volatile memory device includes device isolation patterns defining active portions in a substrate and gate structures disposed on the substrate. The active portions are spaced apart from each other in a first direction and extend in a second direction perpendicular to the first direction. The gate structures are spaced apart from each other in the second direction and extend in the first direction. Each of the device isolation patterns includes a first air gap, and each of a top surface and a bottom surface of the first air gap has a wave-shape in a cross-sectional view taken along the second direction.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: May 26, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hwang Sim, Jinhyun Shin, HoJun Seong
  • Patent number: 9034707
    Abstract: A nonvolatile memory device includes a floating gate formed over a semiconductor substrate, an insulator formed on a first sidewall of the floating gate, a dielectric layer formed on a second sidewall and an upper surface of the floating gate, and a control gate formed over the dielectric layer.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: May 19, 2015
    Assignee: SK Hynix Inc.
    Inventor: Nam-Jae Lee
  • Patent number: 9029256
    Abstract: Methods of fabricating 3D charge-trap memory cells are described, along with apparatus and systems that include them. In a planar stack formed by alternate layers of electrically conductive and insulating material, a substantially vertical opening may be formed. Inside the vertical opening a substantially vertical structure may be formed that comprises a first layer, a charge-trap layer, a tunneling oxide layer, and an epitaxial silicon portion. Additional embodiments are also described.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: May 12, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Nirmal Ramaswamy, Gurtej S. Sandhu
  • Patent number: 9023707
    Abstract: Methods of ONO integration into MOS flow are provided. In one embodiment, the method comprises: (i) forming a pad dielectric layer above a MOS device region of a substrate; and (ii) forming a patterned dielectric stack above a non-volatile device region of the substrate, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer, the charge-trapping layer comprising multiple layers including a first nitride layer formed on the tunnel layer and a second nitride layer, wherein the first nitride layer is oxygen rich relative to the second nitride layer. Other embodiments are also described.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: May 5, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Bo Jin, Fredrick B. Jenne
  • Publication number: 20150099354
    Abstract: A semiconductor device includes vertical channel layers, control gates and interlayer insulating layers stacked alternately with each other on the substrate and surrounding the vertical channel layers, floating gates interposed between the vertical channel layers and the control gates and separated from each other by the interlayer insulating layers, and charge blocking layers interposed between the floating gates and the control gates.
    Type: Application
    Filed: December 11, 2014
    Publication date: April 9, 2015
    Inventor: Seiichi ARITOME
  • Patent number: 8980711
    Abstract: A system and method for manufacturing a memory device is provided. A preferred embodiment comprises manufacturing a flash memory device with a tunneling layer. The tunneling layer is formed by introducing a bonding agent into the dielectric material to bond with and reduce the number of dangling bonds that would otherwise be present. Further embodiments include initiating the formation of the tunneling layer without the bonding agent and then introducing a bonding agent containing precursor and also include a reduced concentration region formed in the tunneling layer adjacent to a substrate.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: March 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Pang Hsieh, Kun-Tsang Chuang, Chia Hsing Huang
  • Patent number: 8980752
    Abstract: A method of forming a plurality of spaced features includes forming sacrificial hardmask material over underlying material. The sacrificial hardmask material has at least two layers of different composition. Portions of the sacrificial hardmask material are removed to form a mask over the underlying material. Individual features of the mask have at least two layers of different composition, with one of the layers of each of the individual features having a tensile intrinsic stress of at least 400.0 MPa. The individual features have a total tensile intrinsic stress greater than 0.0 MPa. The mask is used while etching into the underlying material to form a plurality of spaced features comprising the underlying material. Other implementations are disclosed.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: March 17, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Farrell Good, Baosuo Zhou, Xiaolong Fang, Fatma Arzum Simsek-Ege
  • Patent number: 8975684
    Abstract: Disclosed are non-volatile memory devices and methods of manufacturing the same. The non-volatile memory device includes device isolation patterns defining active portions in a substrate and gate structures disposed on the substrate. The active portions are spaced apart from each other in a first direction and extend in a second direction perpendicular to the first direction. The gate structures are spaced apart from each other in the second direction and extend in the first direction. Each of the device isolation patterns includes a first air gap, and each of a top surface and a bottom surface of the first air gap has a wave-shape in a cross-sectional view taken along the second direction.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: March 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hwang Sim, Jinhyun Shin, HoJun Seong
  • Patent number: 8946048
    Abstract: High-density semiconductor memory is provided with enhancements to gate-coupling and electrical isolation between discrete devices in non-volatile memory. The intermediate dielectric between control gates and charge storage regions is varied in the row direction, with different dielectric constants for the varied materials to provide adequate inter-gate coupling while protecting from fringing fields and parasitic capacitances. Electrical isolation is further provided, at least in part, by air gaps that are formed in the column (bit line) direction and/or air gaps that are formed in the row (word line) direction.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: February 3, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Vinod Robert Purayath, George Matamis, Henry Chien, James Kai, Yuan Zhang
  • Patent number: 8946808
    Abstract: A semiconductor device includes word lines and interlayer insulating layers alternately stacked over a substrate, vertical channel layers protruding from the substrate and passing through the word lines and the interlayer insulating layers, a tunnel insulating layer surrounding each of the vertical channel layers, a charge trap layer surrounding the tunnel insulating layer, wherein first regions of the charge trap layer between the tunnel insulating layer and the word lines have a thickness smaller than a thickness of second regions thereof between the tunnel insulating layer and the interlayer insulating layers, and first charge blocking layer patterns surrounding the first regions of the charge trap layer.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: February 3, 2015
    Assignee: SK Hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Hyun Soo Shon
  • Patent number: 8946022
    Abstract: Nanostructure-based charge storage regions are included in non-volatile memory devices and integrated with the fabrication of select gates and peripheral circuitry. One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: February 3, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Vinod Robert Purayath, James K Kai, Masaaki Higashitani, Takashi Orimoto, George Matamis, Henry Chien
  • Patent number: 8946024
    Abstract: A nonvolatile memory device includes a floating gate formed over a semiconductor substrate, an insulator formed on a first sidewall of the floating gate, a dielectric layer formed on a second sidewall and an upper surface of the floating gate, and a control gate formed over the dielectric layer.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: February 3, 2015
    Assignee: SK Hynix Inc.
    Inventor: Nam-Jae Lee
  • Publication number: 20150031198
    Abstract: According to one embodiment, first, a core pattern is formed above a hard mask layer that is formed above a process object. Then, a spacer film is formed above the hard mask layer. Next, the spacer film is etch-backed. Subsequently, an embedded layer is embedded between the core patterns whose peripheral areas are surrounded by the spacer film. Then, the core pattern and the embedded layer are removed simultaneously. Subsequently, using the spacer pattern as a mask, the hard mask layer and the process object are processed.
    Type: Application
    Filed: March 4, 2014
    Publication date: January 29, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Seiro MIYOSHI, Maki MIYAZAKI, Kentaro MATSUNAGA
  • Patent number: 8889510
    Abstract: A method for forming a surrounding stacked gate fin FET nonvolatile memory structure includes providing a silicon-on-insulator (SOI) substrate of a first conductivity type, patterning a fin active region on a region of the substrate, forming a tunnel oxide layer on the fin active region, and depositing a first gate electrode of a second conductivity type on the tunnel oxide layer and upper surface of the substrate. The method further includes forming a dielectric composite layer on the first gate electrode, depositing a second gate electrode on the dielectric composite layer, patterning the first and second gate electrodes to define a surrounding stacked gate area, forming a spacer layer on a sidewall of the stacked gate electrode, and forming elevated source/drain regions in the fin active region on both sides of the second gate electrode.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: November 18, 2014
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: De Yuan Xiao, Lily Jiang, Gary Chen, Roger Lee
  • Patent number: 8883588
    Abstract: A method of manufacturing a semiconductor device, the method including forming a tunnel insulating layer on an upper surface of a substrate, forming gate patterns on an upper surface of the tunnel insulating layer, forming capping layer patterns on sidewalls of the gate patterns and on the upper surface of the tunnel insulating layer, etching a portion of the tunnel insulating layer that is not covered with the gate patterns or the capping layer patterns to form a tunnel insulating layer pattern, and forming a first insulating layer on the upper surface of the substrate to cover the gate patterns, the capping layer patterns, and the tunnel insulating layer pattern, wherein the first insulating layer has an air gap between the capping layer patterns.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: November 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Soo Ahn, O Ik Kwon, Bum-Soo Kim, Hyun-Sung Kim, Kyoung-Sub Shin, Min-Kyung Yun, Seung-Pil Chung, Won-Bong Jung
  • Patent number: 8871645
    Abstract: Semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof are described herein. In some embodiments, a semiconductor device may include a floating gate having a first width proximate a base of the floating gate that is greater than a second width proximate a top of the floating gate. In some embodiments, a method of shaping a material layer may include (a) oxidizing a surface of a material layer to form an oxide layer at an initial rate; (b) terminating formation of the oxide layer when the oxidation rate is about 90% or below of the initial rate; (c) removing at least some of the oxide layer by an etching process; and (d) repeating (a) through (c) until the material layer is formed to a desired shape. In some embodiments, the material layer may be a floating gate of a semiconductor device.
    Type: Grant
    Filed: September 11, 2009
    Date of Patent: October 28, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Udayan Ganguly, Yoshita Yokota, Jing Tang, Sunderraj Thirupapuliyur, Christopher Sean Olsen, Shiyu Sun, Tze Wing Poon, Wei Liu, Johanes Swenberg, Vicky U. Nguyen, Swaminathan Srinivasan, Jacob Newman
  • Patent number: 8865546
    Abstract: A method for manufacturing a semiconductor device includes the steps of forming a flash memory cell provided with a floating gate, an intermediate insulating film, and a control gate, forming first and second impurity diffusion regions, thermally oxidizing surfaces of a silicon substrate and the floating gate, etching a tunnel insulating film in a partial region through a window of a resist pattern; forming a metal silicide layer on the first impurity diffusion region in the partial region, forming an interlayer insulating film covering the flash memory cell, and forming, in a first hole of the interlayer insulating film, a conductive plug connected to the metal silicide layer.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: October 21, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Tetsuya Yamada
  • Patent number: 8865582
    Abstract: Disclosed are methods for manufacturing floating gate memory devices and the floating gate memory devices thus manufactured. In one embodiment, the method comprises providing a monocrystalline semiconductor substrate, forming a tunnel oxide layer on the substrate, and depositing a protective layer on the tunnel oxide layer to form a stack of the tunnel oxide layer and the protective layer. The method further includes forming at least one opening in the stack, thereby exposing at least one portion of the substrate, and cleaning the at least one exposed portion with a cleaning liquid. The method still further includes loading the substrate comprising the stack into a reactor and, thereafter, performing an in-situ etch to remove the protective layer, using the at least one exposed portion as a source to epitaxially grow a layer comprising the monocrystalline semiconductor material, and forming the layer into at least one columnar floating gate structure.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: October 21, 2014
    Assignee: IMEC
    Inventors: Roger Loo, Matty Caymax, Pieter Blomme, Geert Van den Bosch
  • Patent number: 8853027
    Abstract: In one aspect, a disclosed method of fabricating a split gate memory device includes forming a gate dielectric layer overlying an channel region of a semiconductor substrate and forming an electrically conductive select gate overlying the gate dielectric layer. The method further includes forming a counter doping region in an upper region of the substrate. A proximal boundary of the counter doping region is laterally displaced from a proximal sidewall of the select gate. The method further includes forming a charge storage layer comprising a vertical portion adjacent to the proximal sidewall of the select gate and a lateral portion overlying the counter doping region and forming an electrically conductive control gate adjacent to the vertical portion of the charge storage layer and overlying the horizontal portion of the charge storage layer.
    Type: Grant
    Filed: October 1, 2012
    Date of Patent: October 7, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Cheong Min Hong, Sung-Taeg Kang
  • Publication number: 20140264535
    Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a plurality of charge storage layers each including a lower portion and an upper portion provided on the lower portion and having a smaller width than the lower portion, and a plurality of sacrificial films provided between the upper portions of adjacent ones of the charge storage layers. The sacrificial films are projected higher than the upper portions and spaced by first gaps from sidewalls of the upper portions. The method includes forming a plurality of intermediate insulating films on the upper portions and in the first gaps. The method includes removing the sacrificial films and forming second gaps between adjacent ones of the intermediate insulating films. The method includes forming a control electrode on the intermediate insulating films and in the second gaps.
    Type: Application
    Filed: June 27, 2013
    Publication date: September 18, 2014
    Inventor: Toshiyuki SASAKI
  • Publication number: 20140264538
    Abstract: In a method of manufacturing a semiconductor device, a split gate structure is formed on a cell region of a substrate including the cell region and a logic region. The logic region has a high voltage region, an ultra high voltage region and a low voltage region, and the split gate structure includes a first gate insulation layer pattern, a floating gate, a tunnel insulation layer pattern and a control gate. A spacer layer is formed on the split gate structure and the substrate. The spacer layer is etched to form a spacer on a sidewall of the split gate structure and a second gate insulation layer pattern on the ultra high voltage region of the substrate. A gate electrode is formed on each of the high voltage region of the substrate, the second gate insulation layer pattern, and the low voltage region of the substrate.
    Type: Application
    Filed: March 7, 2014
    Publication date: September 18, 2014
    Inventors: Tea-Kwang YU, Bae-Seong KWON, Yong-Tae KIM, Chul-Ho CHUNG, Yong-Suk CHOI
  • Publication number: 20140252447
    Abstract: A memory device and a method of making a memory device that includes a semiconductor channel, a tunnel dielectric layer located over the semiconductor channel, a floating gate located over the tunnel dielectric layer, the floating gate comprising a continuous layer of an electrically conductive material and at least one protrusion of an electrically conductive material facing the tunnel dielectric layer and electrically shorted to the continuous layer, a blocking dielectric region located over the floating gate, and a control gate located over the blocking dielectric layer.
    Type: Application
    Filed: March 11, 2013
    Publication date: September 11, 2014
    Applicant: SANDISK TECHNOLOGIES, INC.
    Inventors: Donovan Lee, James K. Kai, George Samachisa, Henry Chien, George Matamis, Vinod R. Purayath
  • Patent number: 8829596
    Abstract: The nonvolatile memory device includes a semiconductor layer including trenches formed in a first direction, isolation layers filling the trenches, and active regions divided by the isolation layer, first insulating patterns formed on the semiconductor substrate in a second direction crossing the first direction, charge storage layer patterns formed over the respective active regions between the first insulating patterns, and second insulating patterns formed on the isolation layers between the charge storage layer patterns.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: September 9, 2014
    Assignee: SK Hynix Inc.
    Inventor: Jong Man Kim
  • Patent number: 8829592
    Abstract: A non-volatile storage element and a method of forming the storage element. The non-volatile storage element comprises: a first electrode including a first material having a first work function; a second electrode including a second material having a second work function higher than the first work function; a first dielectric disposed between the first electrode and the second electrode, the first dielectric having a first bandgap; a second dielectric disposed between the first dielectric and the second electrode, the second dielectric having a second bandgap wider than the first bandgap and being disposed such that a quantum well is created in the first dielectric; and a third dielectric disposed between the first electrode and the first dielectric, the third dielectric being thinner than the second dielectric and having a third bandgap wider than the first bandgap.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: September 9, 2014
    Assignee: Intel Corporation
    Inventors: Walid M. Hafez, Anisur Rahman
  • Patent number: 8809177
    Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a gate pattern formed by patterning a tunnel insulating layer, a conductive film for a floating gate, a dielectric film, a conductive film for a control gate, and a gate metal film sequentially formed on a semiconductor substrate; a first barrier film formed on side walls of the gate metal film; and a second barrier film formed on an upper surface of the gate metal film.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: August 19, 2014
    Assignee: SK Hynix Inc.
    Inventor: Jong Man Kim
  • Patent number: 8803218
    Abstract: A nonvolatile memory device includes a floating gate formed over a semiconductor substrate, an insulator formed on a first sidewall of the floating gate, a dielectric layer formed on a second sidewall and an upper surface of the floating gate, and a control gate formed over the dielectric layer.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: August 12, 2014
    Assignee: SK Hynix Inc.
    Inventor: Nam-Jae Lee
  • Patent number: 8772852
    Abstract: Provided is a nonvolatile memory device including a common source. The device includes a first active region crossing a second active region, a common source disposed in the second active region, and a source conductive line disposed on the common source in parallel to the common source. The source conductive line is electrically connected to the common source.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: July 8, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-Soo Kim, Keon-Soo Kim
  • Patent number: 8735271
    Abstract: A gate tunable diode is provided. The gate tunable diode includes a gate dielectric formed on a gate electrode and a graphene electrode formed on the gate dielectric. Also, the gate tunable diode includes a tunnel dielectric formed on the graphene electrode and a tunnel electrode formed on the tunnel dielectric.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: May 27, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Damon Farmer
  • Publication number: 20140126290
    Abstract: The disclosure is related to memory arrays and methods. One such memory array has a substantially vertical pillar. A memory cell adjacent to the pillar where the pillar has a first size has a greater channel length than a memory cell adjacent to the pillar where the pillar has a second size larger than the first size.
    Type: Application
    Filed: November 2, 2012
    Publication date: May 8, 2014
    Applicant: MICRON TECEHNOLOGY, INC
    Inventors: Koji Sakui, Peter Feeley
  • Patent number: 8692266
    Abstract: A circuit substrate structure including a substrate, a dielectric stack layer, a first plating layer and a second plating layer is provided. The substrate has a pad. The dielectric stack layer is disposed on the substrate and has an opening exposing the pad, wherein the dielectric stack layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer located between the first dielectric layer and the second dielectric layer, and there is a gap between the portion of the first dielectric layer surrounding the opening and the portion of the second dielectric layer surrounding the opening. The first plating layer is disposed at the dielectric stack layer. The second plating layer is disposed at the pad, wherein the gap isolates the first plating layer from the second plating layer.
    Type: Grant
    Filed: April 2, 2013
    Date of Patent: April 8, 2014
    Assignee: Optromax Electronics Co., Ltd
    Inventor: Kuo-Tso Chen
  • Publication number: 20140061759
    Abstract: A nonvolatile memory device includes a plurality of gate structures, each gate structure formed over a substrate and including a tunnel insulating layer, a floating gate, an inter-gate dielectric layer, and a control gate, which are sequentially stacked, and an interlayer dielectric layer covering the plurality of gate structures and having an air gap formed between adjacent gate structures, wherein the bottom surface of the air gap is positioned at a lower level than the surface of the tunnel insulating layer.
    Type: Application
    Filed: December 17, 2012
    Publication date: March 6, 2014
    Applicant: SK HYNIX INC.
    Inventors: Byung-In LEE, Tae-Gyun KIM
  • Publication number: 20140061755
    Abstract: A nonvolatile memory device includes gate structures formed over a substrate, each gate structure including a tunnel insulating layer, a floating gate, an inter-gate dielectric layer, and a control gate that are sequentially stacked, a protective layer formed on sidewalls of the floating gate, and a second insulating layer covering the gate structures and having an air gap formed between the gate structures, wherein an adhesive strength between the second insulating layer and the protective layer is smaller than an adhesive strength between the second insulating layer and the gate structure.
    Type: Application
    Filed: December 18, 2012
    Publication date: March 6, 2014
    Applicant: SK HYNIX INC.
    Inventor: Jeong-Seob OH
  • Publication number: 20140057426
    Abstract: A high dielectric constant (high-k) gate dielectric for a field effect transistor (FET) and a high-k tunnel dielectric for a non-volatile random access memory (NVRAM) device are simultaneously formed on a semiconductor substrate. A stack of at least one conductive material layer, a control gate dielectric layer, and a disposable material layer is subsequently deposited and lithographically patterned. A planarization dielectric layer is deposited and patterned, and disposable material portions are removed. A remaining portion of the control gate dielectric layer is preserved in the NVRAM device region, but is removed in the FET region. A conductive material is deposited in gate cavities to provide a control gate for the NVRAM device and a gate portion for the FET. Alternately, the control gate dielectric layer may replaced with a high-k control gate dielectric in the NVRAM device region.
    Type: Application
    Filed: October 29, 2013
    Publication date: February 27, 2014
    Applicant: International Business Machines Corporation
    Inventors: Nicolas Breil, Michael P. Chudzik, Rishikesh Krishnan, Siddarth A. Krishnan, Unoh Kwon
  • Publication number: 20140057425
    Abstract: A gate tunable diode is provided. The gate tunable diode includes a gate dielectric formed on a gate electrode and a graphene electrode formed on the gate dielectric. Also, the gate tunable diode includes a tunnel dielectric formed on the graphene electrode and a tunnel electrode formed on the tunnel dielectric.
    Type: Application
    Filed: August 24, 2012
    Publication date: February 27, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Afzali-Ardakani, Damon Farmer
  • Patent number: 8658499
    Abstract: A monolithic three dimensional NAND string includes a vertical semiconductor channel and a plurality of control gate electrodes in different device levels. The string also includes a blocking dielectric layer, a charge storage region and a tunnel dielectric. A first control gate electrode is separated from a second control gate electrode by an air gap located between the major surfaces of the first and second control gate electrodes and/or the charge storage region includes silicide nanoparticles embedded in a charge storage dielectric.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: February 25, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Raghuveer S. Makala, Johann Alsmeier, Yao-Sheng Lee
  • Patent number: 8652902
    Abstract: Disclosed are methods for manufacturing a floating gate memory device and the floating gate memory device thus obtained. In one embodiment, a method is disclosed that includes providing a semiconductor-on-insulator substrate, forming at least two trenches in the semiconductor-on-insulator substrate, and, as a result of forming the at least two trenches, forming at least one elevated structure. The method further includes forming isolation regions at a bottom of the at least two trenches by partially filling the at least two trenches, thermally oxidizing sidewall surfaces of at least a top portion of the at least one elevated structure, thereby providing a gate dielectric layer on at least the exposed sidewall surfaces; and forming a conductive layer over the at least one elevated structure, the gate dielectric layer, and the isolation regions to form at least one floating gate semiconductor memory device.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: February 18, 2014
    Assignee: IMEC
    Inventors: Pieter Blomme, Antonino Cacciato, Gouri Sankar Kar
  • Patent number: 8637389
    Abstract: A method of making a memory array is provided that includes forming a layer over a substrate, forming features over the layer, forming sidewall spacers on each of the features, filling spaces between adjacent sidewall spacers with filler features, removing the sidewall spacers to leave the features and the filler features, and etching the layer using the features and the filler features as a mask to form pillar shaped nonvolatile memory cells. Numerous other aspects are provided.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: January 28, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Yung-Tin Chen, Steven J. Radigan
  • Patent number: 8629047
    Abstract: Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: January 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zhiyuan Cheng, Calvin Sheen
  • Publication number: 20140001533
    Abstract: A method of fabricating a memory device includes providing multiple coatings of nanodots on a tunnel dielectric layer to form a floating gate layer having a high nanodot density. The memory device may have a nanodot-containing floating gate layer with a density greater than 4×1012 dots/cm2. Further methods include forming an oxidation barrier layer, such as a silicon nitride shell, over a surface of the nanodots, and depositing a dielectric material over the nanodots to form a floating gate layer.
    Type: Application
    Filed: December 7, 2012
    Publication date: January 2, 2014
    Applicant: SANDISK TECHNOLOGIES, INC.
    Inventors: Vinod Purayath, George Samachisa, George Matamis, James Kai, Yuan Zhang
  • Patent number: 8617951
    Abstract: A method of manufacturing a semiconductor memory device which includes forming a conductive layer for a floating gate above a semiconductor layer intervening a gate insulating film therebetween, then, forming, over the conductive layer, a first spacer comprising a first silicon oxide material and a second spacer adjacent with the first spacer and comprising a second silicon oxide material, the second silicon oxide material having an etching rate lower than that of the first silicon oxide material, selectively removing the conductive layer by using the first and the second spacers as a mask, and removing the first spacer to expose a portion of the conductive layer. Since the etching rate for the second spacer is lower compared with the etching rate for the first spacer, the etching amount of the second spacer caused upon removal of the first spacer can be suppressed and, as a result, the productivity and the reliability of the semiconductor memory device can be improved.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: December 31, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Tomokazu Matsuzaki, Makoto Sasaki, Masakuni Shimizu
  • Publication number: 20130337643
    Abstract: A method of fabricating a semiconductor device includes etching a substrate to form a field trench defining an active region and a lower gate pattern on the active region, the lower gate pattern including a tunneling insulating pattern and a lower gate electrode pattern, filling a field insulating material in the field trench to form a field region, forming an upper gate pattern on the lower gate pattern, sequentially forming a stopping layer and a buffer layer on the field region and the upper gate pattern, forming a first resistive pattern on the buffer layer of the field region, and forming a second resistive pattern on the buffer layer on the upper gate pattern, forming an interlayer insulating layer covering the first and second resistive patterns, and performing a planarization process to remove a top surface of the interlayer insulating layer and to remove the second resistive pattern.
    Type: Application
    Filed: March 14, 2013
    Publication date: December 19, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ho-Jun SEONG, Jae-Hwang SIM
  • Publication number: 20130313625
    Abstract: A semiconductor device includes a semiconductor substrate and at least a first gate structure disposed on the semiconductor substrate. Furthermore, a spacer only disposed at a side of the first gate structure, and a material of the spacer does not comprise nitride.
    Type: Application
    Filed: May 28, 2012
    Publication date: November 28, 2013
    Inventor: Ching-Hung Kao
  • Publication number: 20130292757
    Abstract: A semiconductor device includes vertical channel layers, control gates and interlayer insulating layers stacked alternately with each other on the substrate and surrounding the vertical channel layers, floating gates interposed between the vertical channel layers and the control gates and separated from each other by the interlayer insulating layers, and charge blocking layers interposed between the floating gates and the control gates.
    Type: Application
    Filed: September 6, 2012
    Publication date: November 7, 2013
    Inventor: Seiichi ARITOME
  • Patent number: 8575017
    Abstract: A non-volatile semiconductor memory device comprises a plurality of memory cells, each including a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a floating gate formed on the semiconductor substrate with the inclusion of the first insulating film, a second insulating film formed on the floating gate, and a control gate formed on the floating gate with the inclusion of the second insulating film; an element isolation insulating film formed in the semiconductor substrate and extending in a gate-length direction to isolate between memory cells adjoining in a gate-width direction; and an air gap formed on the element isolation insulating film and between floating gates adjoining in the gate-width direction.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: November 5, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takuji Kuniya
  • Patent number: 8564043
    Abstract: An electrically erasable programmable read only memory (EEPROM) cell structure and a method of fabricating the same. The EEPROM cell comprising a substrate comprising two shallow trench isolation (STI) structures separated by a substrate portion; an intermediate patterned layer formed on the substrate such that the patterned layer covers respective portions of each STI structure; a floating gate bridging between the STI structures such that the floating gate extends over the intermediate patterned layer; a dielectric layer formed over the floating gate; and a control gate formed over the dielectric layer.
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: October 22, 2013
    Assignee: Systems On Silicon Manufacturing Co. Pte. Ltd.
    Inventors: Sheng He Huang, Eng Keong Ho, Ping Yaw Peh